Jung-Hyun Park
Jung-Hyun Park, Hwasung-Si KR
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20110100952 | METHOD OF MANUFACTURING PRINTED CIRCUIT BOARD HAVING BUMP - A method of manufacturing a printed circuit board having a bump is disclosed. The method includes preparing a first carrier having a first circuit formed thereon, compressing the first carrier to one surface of an insulation layer such that the first circuit is buried, stacking an etching resist on the first carrier in accordance with where the bump is to be formed and forming the bump by etching the first carrier. In accordance with an embodiment of the present invention, the difference in height between a bump and its adjacent bump in a printed circuit board can be reduced, and thus electrical connection between an electronic component and the printed circuit board can be better implemented. | 05-05-2011 |
20110110058 | BOARD ON CHIP PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF - A single-layer board on chip package substrate and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, the single-layer board on chip package substrate includes an insulator, a circuit pattern and a flip-chip bonding pad, which are formed on an upper surface of the insulator, a conductive bump, which is in contact with a lower surface of the circuit pattern and penetrates through the insulator, a solder resist layer, which is formed on the upper surface of the insulator such that at least a portion of the flip-chip bonding pad is exposed, and a flip-chip bonding bump, which is formed on an upper surface of the flip-chip bonding pad in order to make a flip-chip connection with an electronic component. | 05-12-2011 |
20110186342 | SINGLE-LAYERED PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF - A single layered printed circuit board and a method of manufacturing the same are disclosed. In accordance with an embodiment of the present invention, the method can include forming a bonding pad, a circuit pattern and a post on a surface of an insulation film, in which one end part of the post is electrically connected to at least a portion of the circuit pattern, pressing an insulator on the surface of the insulation film, in which the circuit pattern and the post are buried in the insulator, selectively etching the insulator such that the other end part of the post is exposed, and opening a portion of the insulation film such that at least a portion of the bonding pad is exposed. | 08-04-2011 |
20120244662 | BOARD ON CHIP PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF - A single-layer board on chip package substrate and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, the single-layer board on chip package substrate includes an insulator, a circuit pattern and a flip-chip bonding pad, which are formed on an upper surface of the insulator, a conductive bump, which is in contact with a lower surface of the circuit pattern and penetrates through the insulator, a solder resist layer, which is formed on the upper surface of the insulator such that at least a portion of the flip-chip bonding pad is exposed, and a flip-chip bonding bump, which is formed on an upper surface of the flip-chip bonding pad in order to make a flip-chip connection with an electronic component. | 09-27-2012 |
Jung-Hyun Park, Seoul KR
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20110053365 | METHOD OF MANUFACTURING GATE STRUCTURE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING THE SAME - In a method for manufacturing a semiconductor device, a silicon oxide layer is formed on a substrate. The silicon oxide layer is treated with a solution comprising ozone. Then, a conductive layer is formed on the silicon oxide layer treated with the solution. | 03-03-2011 |
20110260234 | NON-VOLATILE MEMORY DEVICE - A semiconductor device may include a tunnel insulating layer disposed on an active region of a substrate, field insulating patterns disposed in surface portions of the substrate to define the active region, each of the field insulating patterns having an upper recess formed at an upper surface portion thereof, a stacked structure disposed on the tunnel insulating layer, and impurity diffusion regions disposed at surface portions of the active region adjacent to the stacked structure. | 10-27-2011 |
20120015490 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device includes forming a gate structure on a substrate; forming a sacrificial spacer may be formed on a sidewall of the gate substrate; implanting first impurities into portions of the substrate by a first ion implantation process using the gate structure and the sacrificial spacer as ion implantation masks to form source and drain regions; removing the sacrificial spacer; and implanting second impurities and carbon atoms into portions of the substrate by a second ion implantation process using the gate structure as an ion implantation mask to form source and drain extension regions and carbon doping regions, respectively. | 01-19-2012 |
20130162312 | DELAY LOCKED LOOP - A delay locked loop in accordance with some embodiments of the inventive concept may include a delay signal generation part generating a first delay signal having a first phase and a second delay signal having a second phase by delaying a reference signal on the basis of a delay control signal; a phase synthesizing part generating at least one third signal having a third phase using the first delay signal and the second delay signal; and a phase detection part generating a control code by comparing the reference signal with each of the first delay signal, the second delay signal and the third signal. | 06-27-2013 |
20140203854 | DELAY LOCKED LOOP AND METHOD OF GENERATING CLOCK - Provided is a delay locked loop (DLL) including a ring oscillator (RO) including a delay line to delay a reference clock signal and generate a delayed clock signal, wherein the RO circulates, through the delay line, a feedback clock signal corresponding to the delayed clock signal to synchronize N cycles of the feedback clock signal with a cycle of the reference clock signal (where N is an integer number equal to or larger than 2); and a first frequency divider dividing the frequency of the delayed clock signal by 1/N (where N is an integer number equal to or larger than 2) to generate an output clock signal. | 07-24-2014 |
Jung-Hyun Park, Gyeonggi-Do KR
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20100193491 | UNIT FOR SUPPORTING A SUBSTRATE AND APPARATUS FOR PROCESSING A SUBSTRATE HAVING THE SAME - A substrate support unit of a substrate processing apparatus includes a first support member, a second support member, a buffer member and a tube. The first support member has an electrode and a heater built-in and supports the substrate. The second support member is disposed beneath the first support member to support the first support member. The buffer member is disposed between the first support member and the second support member to form an air gap between the first support member and the second support member so as to reduce heat transfer between the first support member and the second support member. The tube is connected with a lower surface of the first support member. Further, the tube extends through the second support member and receives lines for applying power to the electrode and the heater. | 08-05-2010 |
20110308845 | PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME - The present invention provides a printed circuit board including: an insulating member having a through via hole; a circuit pattern disposed on the insulating member; a solder resist disposed on the insulating member while exposing a portion of the circuit pattern; a via plating pad connected to the circuit pattern, disposed inside the via hole, and covering a lower opening of the via hole along an inner wall of the via hole; and an external connection means having a center portion coinciding with a center portion of the via hole and disposed on the via plating pad, and a method of manufacturing the same. | 12-22-2011 |
Jung-Hyun Park, Daejeon KR
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20090011220 | Carrier and method for manufacturing printed circuit board - A carrier and a method for manufacturing a printed circuit board are disclosed. The method for manufacturing a printed circuit board may include: forming a first circuit pattern on each of a pair of release layers, which are attached respectively to either side of a base layer by adhesive layers; detaching the pair of release layers from the base layer; stacking and pressing the pair of release layers onto either side of an insulation substrate such that the first circuit patterns are buried in the insulation substrate; and separating the pair of release layers. By forming a circuit pattern on each of a pair of release layers with a single process, and transferring the circuit pattern into each side of an insulation substrate, the manufacturing process can be shortened and circuit patterns can be formed to a high density. | 01-08-2009 |
20090233400 | Rigid-flexible printed circuit board manufacturing method for package on package - A manufacturing method for rigid-flexible multi-layer printed circuit board including: a flexible substrate of which circuits are formed on both sides and which is bendable; a rigid substrate which is laminated on the flexible substrate and circuits are formed on both sides and a cavity within which a semiconductor chip is mounted is formed; and a bonding sheet adhering the flexible substrate and the rigid substrate and having a insulating property. When the same numbers of the semiconductor chips are mounted or the POP is embodied, the whole thickness of the package can be lower. Also, two more semiconductor chips can be mounted using the space as the thickness of the core layer, and the structure impossible when the number of semiconductor chip mounted on the bottom substrate becomes two from one in conventional technology can be embodied. | 09-17-2009 |
20100132876 | MANUFACTURING METHOD OF PRINTED CIRCUIT BOARD - Disclosed is a method of manufacturing a printed circuit board. The method of manufacturing a printed circuit board having a via for interlayer connection can include forming a circuit pattern on one side of a carrier, pressing one side of the carrier into one side of the insulator, removing the carrier, forming a hole penetrating through the insulator by processing one end of the circuit pattern, and forming a conductive material inside the hole to have the conductive material correspond to the via. | 06-03-2010 |
Jung-Hyun Park, Boeun-Gun KR
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20100099936 | COMPLEX OXIDE CATALYST OF BI/MO/FE FOR THE OXIDATIVE DEHYDROGENATION OF 1-BUTENE TO 1,3-BUTADIENE AND PROCESS THEREOF - The present invention relates to a complex oxide catalyst of Bi/Mo/Fe and an oxidative dehydrogenation of 1-butene in the presence of a catalyst herein. A catalyst of the present invention is superior to the conventional Bi/Mo catalyst in thermal and mechanical stabilities, conversion and selectivity toward 1,3-butadiene, while showing a long-term catalytic activity. | 04-22-2010 |
Jung-Hyun Park, Yeongi-Gun KR
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20100018633 | METHOD OF MANUFACTURING PRINTED CIRCUIT BOARD - Disclosed is a method of manufacturing a printed circuit board. The method of manufacturing a printed circuit board having a via for connecting one layer to another layer can include forming a circuit pattern on one surface of a carrier; processing a hole corresponding to the via on one surface of the carrier; compressing the surface of the carrier into one surface of an insulation body; removing the carrier; processing a via hole on the insulation body, corresponding to a position of the hole; and forming a conductive material in the via hole, to thereby easily process a hole for forming a via and have high design freedom | 01-28-2010 |
Jung-Hyun Park, Suwon-Si KR
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20080251494 | Method for manufacturing circuit board - A method of manufacturing a circuit board is disclosed. The method may include: forming a relievo pattern, which is in a corresponding relationship with a circuit pattern, on a metal layer that is stacked on a carrier; stacking and pressing the carrier onto an insulation layer with the relievo pattern facing the insulation layer; transcribing the metal layer and the relievo pattern into the insulation layer by removing the carrier; forming a via hole in the insulation layer on which the metal layer is transcribed; and filling the via hole and forming a plating layer over the metal layer by performing plating over the insulation layer on which the metal layer is transcribed. As the relievo pattern may be formed on the metal layer stacked on the carrier, and the relievo pattern may be transcribed into the insulation layer, high-density circuit patterns can be formed. | 10-16-2008 |
20080264676 | Circuit board and method for manufaturing thereof - A method of manufacturing a circuit board that includes: forming a conductive relievo pattern, including a first plating layer, a first metal layer, and a second plating layer stacked sequentially in correspondence with a first circuit pattern, on a seed layer stacked on a carrier; stacking and pressing together the carrier and an insulator, such that a surface of the carrier having the conductive relievo pattern faces the insulator; transcribing the conductive relievo pattern into the insulator by removing the carrier; forming a conduction pattern, including a third plating layer and a second metal layer stacked sequentially in correspondence with a second circuit pattern, on the surface of the insulator having the conductive relievo pattern transcribed; removing the first plating layer and seed layer; and removing the first and second metal layers, can provide a circuit board that has high-density circuit patterns without an increased amount of insulator. | 10-30-2008 |
20090242238 | Buried pattern substrate - A buried pattern substrate includes an insulation layer; a circuit pattern buried in the insulation layer such that a part thereof is exposed at a surface of the insulation layer; and a stud bump buried in the insulation layer such that one end portion is exposed at one surface of the insulation layer, and such that the other end portion is exposed at the other surface of the insulation layer. | 10-01-2009 |
20110259627 | Circuit board with buried circuit pattern - A circuit board includes: an insulator having a groove; a circuit layer filling a portion of the groove; a solder pad on the circuit layer filling the remainder of the groove; and a circuit pattern electrically connected with the circuit layer, the circuit pattern buried in the insulator such that a portion of the circuit pattern is exposed at a surface of the insulator. | 10-27-2011 |
20120111607 | CIRCUIT BOARD WITH HIGH-DENSITY CIRCUIT PATTERNS - A circuit board including: an insulator having a trench; a first circuit pattern formed to bury a portion of the trench; and a second circuit pattern formed on a surface of the insulator having the trench formed therein. | 05-10-2012 |
20150061093 | INTERPOSER AND SEMICONDUCTOR PACKAGE USING THE SAME, AND METHOD OF MANUFACTURING INTERPOSER - Disclosed herein is an interposer, including: an interposer substrate configured by stacking an insulating layer of one layer or more and interlayer connected through a via; a cavity penetrating through a center of the interposer substrate in a thickness direction; and a connection electrode having a post part which is disposed on at least one of an upper surface and a lower surface of the interposer substrate, thereby increasing electrical characteristics and reducing manufacturing cost and time. | 03-05-2015 |
Jung-Hyun Park, Cheongju-Si KR
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20090206468 | Board on chip package and manufacturing method thereof - A method of manufacturing a board on chip package including laminating a dry film on a carrier film, one side of which is laminated by a thin metal film; patterning the dry film in accordance with a circuit wire through light exposure and developing process, and forming a solder ball pad and a circuit wire; removing the dry film; laminating an upper photo solder resist excluding a portion where the solder ball pad is formed; etching the thin metal film formed on a portion where the upper photo solder resist is not laminated; mounting a semiconductor chip on the solder ball pad by a flip chip bonding; molding the semiconductor chip with a passivation material; removing the carrier film and the thin metal film; and laminating a lower photo solder resist under the solder ball pad. The board on chip package provides a high density circuit since a circuit pattern is formed using a seed layer. | 08-20-2009 |
20110221074 | Board on chip package - A board on chip package including a photo solder resist having a cavity and a pattern on one side, the pattern corresponding to a circuit wire; a solder ball pad accommodated in the cavity; a circuit wire electrically connected with the solder ball pad, and formed on the other side of the photo solder resist; a semiconductor chip mounted on the solder ball pad by a flip chip bonding; and a passivation material to mold the semiconductor chip. | 09-15-2011 |
Jung-Hyun Park, Dong-Gu KR
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20090095508 | Printed circuit board and method for manufacturing the same - A printed circuit board and a method for manufacturing the same are disclosed. The manufacturing method includes: forming a first plating resist corresponding to the circuit pattern on a surface of each of a first carrier and a second carrier; forming a second plating resist corresponding to the pad on each of the surfaces; forming the pad by performing plating over each of the surfaces; stripping the second plating resists; forming the circuit pattern by performing plating over each of the surfaces; pressing the first carrier and the second carrier with an insulation layer interposed between the first carrier and the second carrier such that the circuit patterns face each other; and removing the first carrier and the second carrier. Since plating bars need not be used, the degree of freedom in designing circuits can be increased, and circuits of higher densities can be designed. | 04-16-2009 |
Jung-Hyun Park, Gimpo-Si KR
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20120319561 | FIELD EMISSION PANEL, LIQUID CRYSTAL DISPLAY AND FIELD EMISSION DISPLAY HAVING THE SAME - A field emission panel, a liquid crystal display and a field emission display having the same are provided. The field emission panel includes a lower plate emitting electrons and an upper plate generating white light or a color image through collision with the electrons. The lower plate includes plural field emission elements, plural cathode electrodes and plural gate electrodes forming an electric field for electron emission from the electron emission elements, and a glass plate supporting the electron emission elements, the cathode electrodes, and the gate electrodes. The gate electrodes are arranged on an upper surface of the glass plate, and the glass plate has plural accommodation grooves for accommodating the plural electron emission elements and the plural cathode electrodes. | 12-20-2012 |
Jung-Hyun Park, Ulsan KR
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20130037004 | TWO SOLENOID VALVE RELAY TWO-STAGE FUEL INJECTION VALVE FOR DIESEL ENGINES - The present invention provides a two solenoid valve relay with a two-phase fuel injection valve for a diesel engine, which is installed on a valve itself to enable injection at pressure greater than opening pressure, at which the fuel enters into a fuel valve, thereby improving fuel injection performance, and which is configured to enable adjustment of an injection timing at the opening pressure within the valve, wherein injection timings through a solenoid valve is provided for low load and high load, respectively, such that a distinct difference exists between the injection timings to open the nozzle hole of the nozzle in a differential manner at pressure higher than the pressure, at which the fuel enters to the fuel valve and internal spring opening pressure, thereby injecting fuel at high pressure even at low load to facilitate vaporization, and wherein, in case of a high speed operation or high load, low pressure/high pressure needle valves are opened at the same time to quickly inject fuel of a high volume through a plurality of nozzle holes, thereby improving combustion performance of an engine, and wherein a space between the needle valve and the nozzle hole which are closed after the injection is minimized because the nozzle hole is opened differentially and sequentially according to pressure, thereby avoiding waste of fuel and reducing harmful gas (smoke, Nox). | 02-14-2013 |
Jung-Hyun Park, Yongin KR
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20130302611 | ORDERED MESOPOROUS CARBON-CARBON NANOTUBE NANOCOMPOSITES AND METHOD FOR MANUFACTURING THE SAME - Disclosed are ordered mesoporous carbon-carbon nanotube nanocomposites and a method for manufacturing the same. The method for manufacturing ordered carbon-carbon nanotube nanocomposites according to the present invention includes: forming a mixture of a carbon precursor and ordered mesoporous silica; carbonizing the mixture to form a ordered mesoporous silica-carbon composite; and removing the mesoporous silica from the ordered mesoporous silica-carbon composite. | 11-14-2013 |
Jung-Hyun Park, Chungbuk KR
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20130209351 | Complex Oxide Catalyst of Bi/Mo/Fe for the Oxidative Dehydrogenation of 1-Butene to 1,3-Butadiene and Process Thereof - The present invention relates to a complex oxide catalyst of Bi/Mo/Fe and an oxidative dehydrogenation of 1-butene in the presence of a catalyst herein. A catalyst of the present invention is superior to the conventional Bi/Mo catalyst in thermal and mechanical stabilities, conversion and selectivity toward 1,3-butadiene, while showing a long-term catalytic activity. | 08-15-2013 |
Jung-Hyun Park, Yongin-Si KR
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20140220424 | RECHARGEABLE BATTERY - A rechargeable battery includes an electrode assembly including a first electrode plate, a second electrode plate, and a separator between the first electrode plate and the second electrode plate, a can in which the electrode assembly is accommodated, the can including an opening at one side, the opening being hermetically sealed by a cap plate, and a top plate on the cap plate. The top plate includes a first welding unit and a second welding unit that are coupled to the cap plate, and a third welding unit that is between the first welding unit and the second welding unit. The first welding unit is connected to the cap plate and includes first through third welding points. The first through third welding points collectively forming a triangular shape. | 08-07-2014 |
Jung-Hyun Park, Asan-Si KR
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20140197861 | Test Equipment for Testing Semiconductor Device and Methods of Testing Semiconductor Device Using the Same - A method of testing a semiconductor device using the test equipment includes loading an undivided printed circuit board (PCB) including unit PCBs in a test equipment. A semiconductor device is mounted in each of the unit PCBs. Product information of the undivided PCB loaded in the test equipment is confirmed. The undivided PCB whose product information has been confirmed is electrically connected to one of a plurality of main testers of the test equipment. Each of the main testers includes a main test interface directly connected to a cloud server in which firmwares for various kinds of tests are stored. The product information of the undivided PCB is transmitted to the main tester electrically connected to the undivided PCB. The main tester to which the product information has been transmitted performs a main test of the undivided PCB using the product information. The undivided PCB on which the main test has been performed by the main tester is unloaded from the test equipment. | 07-17-2014 |
Jung-Hyun Park, Hwaseong-Si KR
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20150092882 | TRANSMITTING APPARATUS, RECEIVING APPARATUS, AND CONTROL METHODS THEREOF - A transmitting apparatus, a receiving apparatus and methods of controlling these apparatuses are provided. The transmitting apparatus includes: an input processor configured to process a plurality of input streams to generate a plurality of base band frames; a bit interleaved and coded modulation (BICM) processor configured to perform forward error correction (FEC) coding, constellation mapping, and interleaving on the plurality of baseband frames; a symbol generator configured to add signaling data to the plurality of baseband frames output from the BICM processor to generate an orthogonal frequency division multiplexing (OFDM) symbol; and a transmitter configured to select at least one of a plurality of pilot patterns based on a fast Fourier transform (FFT) size and a guard interval fraction, insert a pilot in the OFDM symbol according to the selected pilot pattern, and transmit a stream including the pilot-inserted OFDM symbol. Thus, a data transmission rate is increased and accurate channel estimation is performed, through inserting different pilots according to different FFT sizes and guard interval fractions. | 04-02-2015 |