Patent application number | Description | Published |
20080205156 | Method of operating nonvolatile memory device - Provided is a method of operating a nonvolatile memory device to perform an erase operation. The method includes applying a composite pulse including a direct current (DC) pulse and a DC perturbation pulse to the nonvolatile memory device to perform the erase operation. | 08-28-2008 |
20080206932 | DATA LINE LAYOUT IN SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME - In one aspect, a semiconductor device is provided which includes a data block including M parallel and sequentially arranged data lines numbered {0, 1, 2, . . . n, n+1, . . . , m−1, m}, where M, n and m are positive integers, and where n08-28-2008 | |
20080237700 | Nonvolatile memory device having cell and peripheral regions and method of making the same - A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance. | 10-02-2008 |
20090122622 | LEVEL SHIFTER WITH REDUCED LEAKAGE CURRENT AND BLOCK DRIVER FOR NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A level shifter is disclosed and generates an output signal having a swing voltage shifted by a positive boost voltage with respect to an input signal. The level shifter comprises; an enable unit adapted to enable the output signal in response to the input signal, and a disable unit adapted to disable the output signal in response to the input signal. The enable unit comprises; a shifting voltage terminal adapted to receive the boost voltage, a control node, a shifting unit disposed between the shifting voltage terminal and the control node and responsive to the output signal, such that a voltage having a difference with the boost voltage lower than a voltage of the output signal is provided to the control node, whereby the output signal is boosted by the positive boost voltage, a control PMOS transistor disposed between the control node and the output signal and gated by the input signal, and bulk voltage generation unit adapted to generate a predetermined bulk voltage having a voltage difference with the boost voltage lower than that of the control node to a bulk of the control PMOS transistor. | 05-14-2009 |
20090315099 | METHOD OF MAKING FLASH MEMORY CELLS AND PERIPHERAL CIRCUITS HAVING STI, AND FLASH MEMORY DEVICES AND COMPUTER SYSTEMS HAVING THE SAME - An integrated circuit includes flash memory cells, and peripheral circuitry including low voltage transistors (LVT) and high voltage transistors (HVT). The integrated circuit includes a tunnel barrier layer comprising SiON, SiN or other high-k material. The tunnel barrier layer may comprise a part of the gate dielectric of the HVTs. The tunnel barrier layer may constitute the entire gate dielectric of the HVTs. The corresponding tunnel barrier layer may be formed between or upon shallow trench isolation (STIs). Therefore, the manufacturing efficiency of a driver chip IC may be increased. | 12-24-2009 |
20100065894 | Semiconductor Device Having a Field Effect Source/Drain Region - A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by a fringe field of the gate. The other source/drain region is a PN-junction source/drain region having different impurity fields and different conductivity than the substrate. At least one of the source/drain regions is a field effect source/drain region. Accordingly, a short channel effect is reduced or eliminated in the device. | 03-18-2010 |
20100091571 | NONVOLATILE MEMORY DEVICE WITH NAND CELL STRINGS - A nonvolatile memory device comprises a memory cell array wherein a plurality of memory cell transistors are divided into multiple erase blocks. The multiple erase blocks are separated from each other by dummy word lines. During an erase operation of one of the multiple blocks, a dummy word line separating the one of the multiple blocks from other erase blocks is driven with a coupling inhibition voltage. | 04-15-2010 |
20100184263 | METHODS OF FABRICATING FLASH MEMORY DEVICES HAVING SHARED SUB ACTIVE REGIONS - Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact plug is provided on, and electrically contacting, the sub active region and being at least as wide as the sub active region. An elongated bit line is provided on, and electrically contacting, the bit line contact plug remote from the sub active region. | 07-22-2010 |
20100301425 | SEMICONDUCTOR DEVICE HAVING A GATE CONTACT STRUCTURE CAPABLE OF REDUCING INTERFACIAL RESISTANCE - A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycrystalline silicon layer through the opening. | 12-02-2010 |
20100317157 | CELL ARRAY OF SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FORMING THE SAME - A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second region is at a different level than a top surface of the first region. The cell array also includes a plurality of word lines crossing over the first region. The cell array also includes a selection line crossing over the active region, wherein at least a portion of the selection line is located over the transition region. | 12-16-2010 |
20110037118 | Nonvolatile memory device having cell and peripheral regions and method of making the same - A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance. | 02-17-2011 |
20110095351 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a device isolation layer in a semiconductor substrate, an active region defined by the device isolation layer, the active region including a main surface and a recess region including a bottom surface that is lower than the main surface, and a gate electrode formed over the recess region, wherein a top surface of the device isolation layer adjacent to the recess region is lower than the bottom surface of the recess region. | 04-28-2011 |
20110117713 | METHOD OF MAKING FLASH MEMORY CELLS AND PERIPHERAL CIRCUITS HAVING STI, AND FLASH MEMORY DEVICES AND COMPUTER SYSTEMS HAVING THE SAME - An integrated circuit includes flash memory cells, and peripheral circuitry including low voltage transistors (LVT) and high voltage transistors (HVT). The integrated circuit includes a tunnel barrier layer comprising SiON, SiN or other high-k material. The tunnel barrier layer may comprise a part of the gate dielectric of the HVTs. The tunnel barrier layer may constitute the entire gate dielectric of the HVTs. The corresponding tunnel barrier layer may be formed between or upon shallow trench isolation (STIs). Therefore, the manufacturing efficiency of a driver chip IC may be increased. | 05-19-2011 |
20110280066 | SEMICONDUCTOR DEVICE HAVING A FIELD EFFECT SOURCE/DRAIN REGION - A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by a fringe field of the gate. The other source/drain region is a PN-junction source/drain region having different impurity fields and different conductivity than the substrate. At least one of the source/drain regions is a field effect source/drain region. Accordingly, a short channel effect is reduced or eliminated in the device. | 11-17-2011 |
20140106518 | NONVOLATILE MEMORY DEVICES - A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers. | 04-17-2014 |
20140160854 | NON-VOLATILE MEMORY DEVICES AND METHODS OF OPERATING THE SAME - A non-volatile memory device includes a semiconductor substrate and a tunnel insulating layer and a gate electrode. A multiple tunnel insulation layer with a plurality of layers, a charge storage insulation layer, and a multiple blocking insulation layer with layers are sequentially stacked between the gate electrode and the tunnel insulating layer. A first diffusion region and a second diffusion region in the semiconductor substrate are adjacent to opposite respective sides of the gate electrode. When a voltage is applied to the gate electrode and the semiconductor substrate to form a voltage level difference therebetween, a minimum field in the tunnel insulation layer is stronger than in the blocking insulation layer. A minimum field at a blocking insulation layer can be stronger than at a tunnel insulation layer, and the migration probability of charges through the tunnel insulation layer can be higher than through the blocking insulation layer. | 06-12-2014 |