Patent application number | Description | Published |
20080197338 | Bottom electrode for memory device and method of forming the same - Contacts having use in an integrated circuit and exemplary methods of forming the contacts are disclosed. The methods involve forming a conductive cap over a metal plug. The invention can mitigate keyholes in the contacts by capping and encapsulating the conductive material used to form the contact. The exemplary cap may be made of a nitride material. | 08-21-2008 |
20080247225 | Variable resistance memory with lattice array using enclosing transistors - A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations. | 10-09-2008 |
20080247226 | Memory devices having electrodes comprising nanowires, systems including same and methods of forming same - Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices. | 10-09-2008 |
20080258125 | Resistive memory cell fabrication methods and devices - A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom electrode. The shapes of the variable resistance region and the top electrode are configured to evenly distribute a current with a generally hemispherical current density distribution around the first electrode. | 10-23-2008 |
20080268568 | MATERIAL SIDEWALL DEPOSITION METHOD - A method of forming a layer of material on a sidewall of a via with good thickness control. The method involves forming a layer of material with a conventional deposition process. The material formed on a field region surrounding the via is removed with a sputter etch process. Another layer of material is deposited thereon, wherein the sputter etch-deposition cycle is repeated as necessary to achieve a desired sidewall thickness. With this method, the thickness of the material deposited on the sidewall is linearly dependent on the number of process cycles, thus providing good thickness control. The method may be used to form a resistance variable material, e.g., a phase-change material, on a via sidewall for use in a memory element. | 10-30-2008 |
20080291718 | VARIABLE RESISTANCE MEMORY DEVICE WITH AN INTERFACIAL ADHESION HEATING LAYER, SYSTEMS USING THE SAME AND METHODS OF FORMING THE SAME - A variable resistance memory element and method of forming the same. The memory element includes a first electrode, a resistivity interfacial layer having a first surface coupled to said first electrode; a resistance changing material, e.g. a phase change material, having a first surface coupled to a second surface of said resistivity interfacial layer, and a second electrode coupled to a second surface of said resistance changing material. | 11-27-2008 |
20080298113 | Resistive memory architectures with multiple memory cells per access device - A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices. | 12-04-2008 |
20080310209 | Circuit, biasing scheme and fabrication method for diode accesed cross-point resistive memory array - Methods, systems, structures and arrays are disclosed, such as a resistive memory array which includes access devices, for example, back-to-back Zener diodes, that only allow current to pass through a coupled resistive memory cell when a voltage drop applied to the access device is greater than a critical voltage. The array may be biased to reduce standby currents and improve delay times between programming and read operations. | 12-18-2008 |
20090072341 | BURIED LOW-RESISTANCE METAL WORD LINES FOR CROSS-POINT VARIABLE-RESISTANCE MATERIAL MEMORIES - Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line. | 03-19-2009 |
20090073741 | NAND-STRUCTURED SERIES VARIABLE-RESISTANCE MATERIAL MEMORIES, PROCESSES OF FORMING SAME, AND METHODS OF USING SAME - A variable-resistance material memory array includes a series of variable-resistance material memory cells. The series of variable-resistance material memory cells is in parallel with a corresponding series of control gates. A select gate is also in series with the variable-resistance material memory cells. Writing/reading/erasing to a given variable-resistance material memory cell includes turning off the corresponding control gate, while turning on all other control gates. Devices include the variable-resistance material memory array. | 03-19-2009 |
20090108292 | Floating Body Field-Effect Transistors, and Methods of Forming Floating Body Field-Effect Transistors - In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor Si | 04-30-2009 |
20090124041 | RESISTANCE VARIABLE MEMORY DEVICE WITH NANOPARTICLE ELECTRODE AND METHOD OF FABRICATION - A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of the nanoparticle. | 05-14-2009 |
20090166605 | PHASE CHANGE MEMORY ELEMENTS USING SELF-ALIGNED PHASE CHANGE MATERIAL LAYERS AND METHOS OF MAKING AND USING SAME - A phase change memory element and method of forming the same. The memory element includes a substrate supporting a first electrode. An insulating material element is positioned over the first electrode, and a phase change material layer is formed over the first electrode and surrounding the insulating material element such that the phase change material layer has a lower surface that is in electrical communication with the first electrode. The memory element also has a second electrode in electrical communication with an upper surface of the phase change material layer. | 07-02-2009 |
20090196095 | MULTIPLE MEMORY CELLS AND METHOD - Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further, methods and devices for addressing and accessing cells are shown that provide a simple and efficient way to manage devices with multiple cells associated with each access transistor. Examples of multiple cell devices include phase change memory devices with multiple cells associated with each access transistor. | 08-06-2009 |
20090196096 | Memory Cells, Methods Of Forming Memory Cells, And Methods Of Forming Programmed Memory Cells - In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region; and a drain region on an opposing side of the channel region from the source region. The channel region has phase change material adjacent the drain region. In some embodiments, the phase change material may be adjacent both the source region and the drain region. Some embodiments include methods of programming a memory cell that has phase change material adjacent a drain region. An inversion layer is formed within the channel region adjacent the gate dielectric, with the inversion layer having a pinch-off region within the phase change material adjacent the drain region. Hot carriers (for instance, electrons) within the pinch-off region are utilized to change a phase within the phase change material. | 08-06-2009 |
20090219751 | PHASE CHANGE MEMORY - A PCRAM cell has a high resistivity bottom electrode cap to provide partial heating near the interface between the cell and the bottom electrode, preventing separation of the amorphous GST region from the bottom electrode, and reducing the programming current requirements. | 09-03-2009 |
20090231910 | NON-VOLATILE MEMORY WITH RESISTIVE ACCESS COMPONENT - Some embodiments include apparatus and methods having a memory element configured to store information and an access component configured to allow conduction of current through the memory element when a first voltage difference in a first direction across the memory element and the access component exceeds a first voltage value and to prevent conduction of current through the memory element when a second voltage difference in a second direction across the memory element and the access component exceeds a second voltage value, wherein the access component includes a material excluding silicon. | 09-17-2009 |
20090231911 | PHASE CHANGE MEMORY CELL WITH CONSTRICTION STRUCTURE - Some embodiments include apparatus and methods having a memory cell with a first electrode and a second electrode, and a memory element directly contacting the first and second electrodes. The memory element may include a programmable portion having a material configured to change between multiple phases. The programmable portion may be isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. | 09-17-2009 |
20090231912 | PHASE CHANGE MEMORY ADAPTIVE PROGRAMMING - Some embodiments include methods and apparatus having a module configured to program a memory cell using a signal to cause the memory cell to have a programmed resistance value, to adjust a programming parameter value of the signal if the programmed resistance value is outside a target resistance value range, and to repeat at least one of the programming and the adjusting if the programmed resistance value is outside the target resistance value range, the signal including a different programming parameter value each time the programming is repeated. | 09-17-2009 |
20090251952 | STATE MACHINE SENSING OF MEMORY CELLS - The present disclosure includes methods, devices, modules, and systems for sensing memory cells using a state machine. One method embodiment includes generating a first sensing reference according to a first output of a state machine. The method includes bifurcating a range of possible programmed levels to which a memory cell can be programmed with the first sensing reference. The method also includes generating a second sensing reference according to a second output of the state machine. The method further includes determining a programmed level of the memory cell with the second generated sensing reference. | 10-08-2009 |
20090261316 | ENHANCED MEMORY DENSITY RESISTANCE VARIABLE MEMORY CELLS, ARRAYS, DEVICES AND SYSTEMS INCLUDING THE SAME, AND METHODS OF FABRICATION - A resistance variable memory cell and method of forming the same. The memory cell includes a first electrode and at least one layer of resistance variable material in contact with the first electrode. A first, second electrode is in contact with a first portion of the at least one layer of resistance variable material and a second, second electrode is in contact with a second portion of the at least one layer of resistance variable material. | 10-22-2009 |
20090316467 | Memory Device Constructions, Memory Cell Forming Methods, and Semiconductor Construction Forming Methods - Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a row line above the second column line and extending perpendicular to the first column line and the second column line; memory material disposed to be selectively and reversibly configured in one of two or more different resistive states; a first diode configured to conduct a first current between the first column line and the row line via the memory material; and a second diode configured to conduct a second current between the second column line and the row line via the memory material. In some embodiments, the first diode is a Schottky diode having a semiconductor anode and a metal cathode and the second diode is a Schottky diode having a metal anode and a semiconductor cathode. | 12-24-2009 |
20100001250 | VARIABLE RESISTANCE MEMORY DEVICE WITH AN INTERFACIAL ADHESION HEATING LAYER, SYSTEMS USING THE SAME AND METHODS FORMING THE SAME - A variable resistance memory element and method of forming the same. The memory element includes a first electrode, a resistivity interfacial layer having a first surface coupled to said first electrode; a resistance changing material, e.g. a phase change material, having a first surface coupled to a second surface of said resistivity interfacial layer, and a second electrode coupled to a second surface of said resistance changing material. | 01-07-2010 |
20100008163 | MEMORY ARCHITECTURE AND CELL DESIGN EMPLOYING TWO ACCESS TRANSISTORS - An improved memory array architecture and cell design is disclosed in which the cell employs two access transistors. In one embodiment, the two access transistors in each cell are coupled at one of their channel terminals to a memory element, which in turn is connected to a bit line. The other of the channel terminals are effectively tied together via reference lines. The word lines (i.e., gates) of the two access transistors are also tied together. The result in a preferred embodiment is a cell having two access transistors wired and accessed in parallel. With such a configuration, the widths of the access transistors can be made one-half the width of more-traditional one-access-transistor designs, saving layout space in that (first) dimension. Moreover, because the word lines of adjacent cells will be deselected, the improved design does not require cell-to-cell isolation (e.g., trench isolation) in the other (second) dimension. The result, when applied to a phase change memory, comprises about a 37% reduction in layout area from previous cell designs. | 01-14-2010 |
20100034016 | PHASE CHANGE MEMORY STRUCTURES AND METHODS - Methods, devices, and systems associated with phase change memory structures are described herein. One or more embodiments of the present disclosure can reduce thermal crosstalk associated with phase change memory cells, which can provide various benefits including improved data reliability and retention and decreased read and/or write times, among various other benefits. One or more embodiments can reduce the number of processing steps associated with providing local interconnects to phase change memory arrays. | 02-11-2010 |
20100044664 | MEMORY DEVICES AND METHODS OF FORMING THE SAME - Memory devices having a plurality of memory cells, with each memory cell including a phase change material having a laterally constricted portion thereof. The laterally constricted portions of adjacent memory cells are vertically offset and positioned on opposite sides of the memory device. Also disclosed are memory devices having a plurality of memory cells, with each memory cell including first and second electrodes having different widths. Adjacent memory cells have the first and second electrodes offset on vertically opposing sides of the memory device Methods of forming the memory devices are also disclosed. | 02-25-2010 |
20100065806 | PROGRAMMABLE RESISTANCE MEMORY DEVICES AND SYSTEMS USING THE SAME AND METHODS OF FORMING THE SAME - A programmable resistance memory element and method of forming the same. The memory element includes a first electrode, a dielectric layer over the first electrode and a second electrode over the dielectric layer. The dielectric layer and the second electrode each have sidewalls. A layer of programmable resistance material, e.g., a phase change material, is in contact with the first electrode and at least a portion of the sidewalls of the dielectric layer and the second electrode. Memory devices including memory elements and systems incorporating such memory devices are also disclosed. | 03-18-2010 |
20100068879 | CONTACT FOR MEMORY CELL - A contact for memory cells and integrated circuits having a conductive layer supported by the sidewall of a dielectric mesa, memory cells incorporating such a contact, and methods of forming such structures. | 03-18-2010 |
20100080036 | UNIDIRECTIONAL SPIN TORQUE TRANSFER MAGNETIC MEMORY CELL STRUCTURE - Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents. | 04-01-2010 |
20100080047 | SPIN CURRENT GENERATOR FOR STT-MRAM OR OTHER SPINTRONICS APPLICATIONS - Spin current generators and systems and methods for employing spin current generators. A spin current generator may be configured to generate a spin current polarized in one direction, or a spin current selectively polarized in two directions. The spin current generator may by employed in spintronics applications, wherein a spin current is desired. | 04-01-2010 |
20100080048 | STT-MRAM CELL STRUCTURE INCORPORATING PIEZOELECTRIC STRESS MATERIAL - A magnetic memory cell including a piezoelectric material, and methods of operating the memory cell are provided. The memory cell includes a stack, and the piezoelectric material may be formed as a layer in the stack or adjacent the layers of the cell stack. The piezoelectric material may be used to induce a transient stress during programming of the memory cell to reduce the critical switching current of the memory cell. | 04-01-2010 |
20100108970 | Memory Devices and Formation Methods - A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite conductivity types. After activating the dopant, the substrate is bonded to the insulator material and at least some of the substrate is removed where bonded to the insulator material. After the removing, a memory cell is formed having a word line, an access diode, a state-changeable memory element containing chalcogenide phase change material, and a bit line all electrically connected in series, the access diode containing the junction as a p-n junction. A memory device includes an adhesion material over the insulator material and bonding the word line to the insulator material. | 05-06-2010 |
20100110757 | RESISTIVE MEMORY - The present disclosure includes resistive memory devices and systems having resistive memory cells, as well as methods for operating the resistive memory cells. One memory device embodiment includes at least one resistive memory element, a programming circuit, and a sensing circuit. For example, the programming circuit can include a switch configured to select one of N programming currents for programming the at least one resistive memory element, where each of the N programming currents has a unique combination of current direction and magnitude, with N corresponding to the number of resistance states of the at least one memory element. In one or more embodiments, the sensing circuit can be arranged for sensing of the N resistance states. | 05-06-2010 |
20100110779 | MULTILEVEL PHASE CHANGE MEMORY OPERATION - Methods, devices, and systems associated with multilevel phase change memory cells are described herein. One or more embodiments of the present disclosure include operating a phase change memory device by placing a phase change memory cell in a reset state and applying a selected programming pulse to the phase change memory cell in order to program the cell to one of a number of intermediate states between the reset state and a set state associated with the cell. The selected programming pulse includes an uppermost magnitude applied for a particular duration, the particular duration depending on to which one of the number of intermediate states the memory cell is to be programmed. | 05-06-2010 |
20100110783 | SPIN TORQUE TRANSFER CELL STRUCTURE UTILIZING FIELD-INDUCED ANTIFERROMAGNETIC OR FERROMAGNETIC COUPLING - A magnetic memory cell including a soft magnetic layer and a coupling layer, and methods of operating the memory cell are provided. The memory cell includes a stack with a free ferromagnetic layer and a pinned ferromagnetic layer, and a soft magnetic layer and a coupling layer may also be formed as layers in the stack. The coupling layer may cause antiferromagnetic coupling to induce the free ferromagnetic layer to be magnetized in a direction antiparallel to the magnetization of the soft magnetic layer, or the coupling layer may cause ferromagnetic coupling to induce the free ferromagnetic layer to be magnetized in a direction parallel to the magnetization of the soft magnetic layer. The coupling layer, through a coupling effect, reduces the critical switching current of the memory cell. | 05-06-2010 |
20100140581 | BOTTOM ELECTRODE FOR MEMORY DEVICE AND METHOD OF FORMING THE SAME - Contacts having use in an integrated circuit and exemplary methods of forming the contacts are disclosed. The methods involve forming a conductive cap over a metal plug. The invention can mitigate keyholes in the contacts by capping and encapsulating the conductive material used to form the contact. The exemplary cap may be made of a nitride material. | 06-10-2010 |
20100151623 | PHASE CHANGE MEMORY - A PCRAM cell has a high resistivity bottom electrode cap to provide partial heating near the interface between the cell and the bottom electrode, preventing separation of the amorphous GST region from the bottom electrode, and reducing the programming current requirements. | 06-17-2010 |
20100151637 | Resistive memory architectures with multiple memory cells per access device - A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices. | 06-17-2010 |
20100176367 | MEMORY CELL HAVING DIELECTRIC MEMORY ELEMENT - Some embodiments include apparatus and methods having a memory cell with a first electrode, a second electrode, and a dielectric located between the first and second electrodes. The dielectric may be configured to allow the memory cell to form a conductive path in the dielectric from a portion of a material of the first electrode to represent a first value of information stored in the memory cell. The dielectric may also be configured to allow the memory cell to break the conductive path to represent a second value of information stored in the memory cell. | 07-15-2010 |
20100177557 | STT-MRAM CELL STRUCTURES - A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, and a nonmagnetic bridge electrically connecting the free layer and the pinned layer. The shape and/or configuration of the nonmagnetic bridge directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer of the structure is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell. | 07-15-2010 |
20100177561 | MEMORY CELL HAVING NONMAGNETIC FILAMENT CONTACT AND METHODS OF OPERATING AND FABRICATING THE SAME - A magnetic cell structure including a nonmagnetic filament contact, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, an insulative layer between the free and pinned layers, and a nonmagnetic filament contact in the insulative layer which electrically connects the free and pinned layers. The nonmagnetic filament contact is formed from a nonmagnetic source layer, also between the free and pinned layers. The filament contact directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell. | 07-15-2010 |
20100193759 | REDUCED POWER CONSUMPTION PHASE CHANGE MEMORY AND METHODS FOR FORMING THE SAME - Memory cells for reduced power consumption and methods for forming the same are provided. A memory cell has a layer of phase change material. A first portion of the phase change material layer includes the programmable volume of the memory cell and its crystalline state has a higher resistivity than that of the crystalline state of a second portion of the phase change material layer. | 08-05-2010 |
20100200830 | MEMORY DEVICE HAVING SELF-ALIGNED CELL STRUCTURE - Some embodiments include apparatus and methods having a memory device with diodes coupled to memory elements. Each diode may be formed in a recess of the memory device. The recess may have a polygonal sidewall. The diode may include a first material of a first conductivity type (e.g., n-type) and a second material of a second conductive type (e.g., p-type) formed within the recess. | 08-12-2010 |
20100230654 | RESISTIVE MEMORY CELL FABRICATION METHODS AND DEVICES - A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom electrode. The shapes of the variable resistance region and the top electrode are configured to evenly distribute a current with a generally hemispherical current density distribution around the first electrode. | 09-16-2010 |
20100264395 | PHASE CHANGE MEMORY STRUCTURES AND METHODS - Methods, devices, and systems associated with phase change memory structures are described herein. One or more embodiments of the present disclosure can reduce thermal crosstalk associated with phase change memory cells, which can provide various benefits including improved data reliability and retention and decreased read and/or write times, among various other benefits. One or more embodiments can reduce the number of processing steps associated with providing local interconnects to phase change memory arrays. | 10-21-2010 |
20100271863 | Memory Cells, Memory Cell Programming Methods, Memory Cell Reading Methods, Memory Cell Operating Methods, and Memory Devices - Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline. | 10-28-2010 |
20100283030 | MEMORY DEVICES AND METHODS OF FORMING THE SAME - Memory devices having a plurality of memory cells, with each memory cell including a phase change material having a laterally constricted portion thereof. The laterally constricted portions of adjacent memory cells are vertically offset and positioned on opposite sides of the memory device. Also disclosed are memory devices having a plurality of memory cells, with each memory cell including first and second electrodes having different widths. Adjacent memory cells have the first and second electrodes offset on vertically opposing sides of the memory device. Methods of forming the memory devices are also disclosed. | 11-11-2010 |
20100295011 | ENHANCED MEMORY DENSITY RESISTANCE VARIABLE MEMORY CELLS, ARRAYS, DEVICES AND SYSTEMS INCLUDING THE SAME, AND METHODS OF FABRICATION - A resistance variable memory cell and method of forming the same. The memory cell includes a first electrode and at least one layer of resistance variable material in contact with the first electrode. A first, second electrode is in contact with a first portion of the at least one layer of resistance variable material and a second, second electrode is in contact with a second portion of the at least one layer of resistance variable material. | 11-25-2010 |
20100320436 | ENCAPSULATED PHASE CHANGE CELL STRUCTURES AND METHODS - Methods and devices associated with phase change cell structures are described herein. In one or more embodiments, a method of forming a phase change cell structure includes forming a substrate protrusion that includes a bottom electrode, forming a phase change material on the substrate protrusion, forming a conductive material on the phase change material, and removing a portion of the conductive material and a portion of the phase change material to form an encapsulated stack structure. | 12-23-2010 |
20100321988 | CROSS-POINT MEMORY DEVICES, ELECTRONIC SYSTEMS INCLUDING CROSS-POINT MEMORY DEVICES AND METHODS OF ACCESSING A PLURALITY OF MEMORY CELLS IN A CROSS-POINT MEMORY ARRAY - Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed. | 12-23-2010 |
20100321992 | PHASE CHANGE MEMORY ELEMENTS USING ENERGY CONVERSION LAYERS, MEMORY ARRAYS AND SYSTEMS INCLUDING SAME, AND METHODS OF MAKING AND USING SAME - A phase change memory element and method of forming the same. The memory element includes a phase change material layer electrically coupled to first and second conductive material layers. A energy conversion layer is formed in association with the phase change material layer, and electrically coupled to a third conductive material layer. An electrically isolating material layer is formed between the phase change material layer and the energy conversion layer. | 12-23-2010 |
20110032754 | PHASE CHANGE MEMORY ADAPTIVE PROGRAMMING - Some embodiments include methods and apparatus having a module configured to program a memory cell using a signal to cause the memory cell to have a programmed resistance value, to adjust a programming parameter value of the signal if the programmed resistance value is outside a target resistance value range, and to repeat at least one of the programming and the adjusting if the programmed resistance value is outside the target resistance value range, the signal including a different programming parameter value each time the programming is repeated. | 02-10-2011 |
20110057161 | THERMALLY SHIELDED RESISTIVE MEMORY ELEMENT FOR LOW PROGRAMMING CURRENT - Various embodiments described herein provide a memory device including a variable resistance material having a thermally isolating and electrically conductive isolation region arranged between the variable resistance material and an electrode to allow for efficient heating of the variable resistance material by a programming current. An electrically and thermally isolating isolation region may be arranged around the variable resistance material. | 03-10-2011 |
20110058406 | RESISTIVE MEMORY - The present disclosure includes resistive memory devices and systems having resistive memory cells, as well as methods for operating the resistive memory cells. One memory device embodiment includes at least one resistive memory element, a programming circuit, and a sensing circuit. For example, the programming circuit can include a switch configured to select one of N programming currents for programming the at least one resistive memory element, where each of the N programming currents has a unique combination of current direction and magnitude, with N corresponding to the number of resistance states of the at least one memory element. In one or more embodiments, the sensing circuit can be arranged for sensing of the N resistance states. | 03-10-2011 |
20110062406 | Memory Devices and Formation Methods - A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite conductivity types. After activating the dopant, the substrate is bonded to the insulator material and at least some of the substrate is removed where bonded to the insulator material. After the removing, a memory cell is formed having a word line, an access diode, a state-changeable memory element containing chalcogenide phase change material, and a bit line all electrically connected in series, the access diode containing the junction as a p-n junction. A memory device includes an adhesion material over the insulator material and bonding the word line to the insulator material. | 03-17-2011 |
20110065235 | PHASE CHANGE MEMORY CELL WITH CONSTRICTION STRUCTURE - Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described. | 03-17-2011 |
20110068313 | MEMORY DEVICES WITH ENHANCED ISOLATION OF MEMORY CELLS, SYSTEMS INCLUDING SAME AND METHODS OF FORMING SAME - Memory cells of a memory device including a variable resistance material have a cavity between the memory cells. Electronic systems include such memory devices. Methods of forming a memory device include providing a cavity between memory cells of the memory device. | 03-24-2011 |
20110069522 | VARIABLE RESISTANCE MEMORY WITH LATTICE ARRAY USING ENCLOSING TRANSISTORS - A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations. | 03-24-2011 |
20110070714 | REPRODUCIBLE RESISTNANCE VARIABLE INSULATING MEMORY DEVICES AND METHODS FOR FORMING SAME - The present invention relates to the use of a shaped bottom electrode in a resistance variable memory device. The shaped bottom electrode ensures that the thickness of the insulating material at the tip of the bottom electrode is thinnest, creating the largest electric field at the tip of the bottom electrode. The arrangement of electrodes and the structure of the memory element makes it possible to create conduction paths with stable, consistent and reproducible switching and memory properties in the memory device. | 03-24-2011 |
20110076827 | MEMORY DEVICES HAVING ELECTRODES COMPRISING NANOWIRES, SYSTEMS INCLUDING SAME AND METHODS OF FORMING SAME - Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices. | 03-31-2011 |
20110095256 | Memory Cells - In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region; and a drain region on an opposing side of the channel region from the source region. The channel region has phase change material adjacent the drain region. In some embodiments, the phase change material may be adjacent both the source region and the drain region. Some embodiments include methods of programming a memory cell that has phase change material adjacent a drain region. An inversion layer is formed within the channel region adjacent the gate dielectric, with the inversion layer having a pinch-off region within the phase change material adjacent the drain region. Hot carriers (for instance, electrons) within the pinch-off region are utilized to change a phase within the phase change material. | 04-28-2011 |
20110103129 | VARIABLE-RESISTANCE MATERIAL MEMORIES, PROCESSES OF FORMING SAME, AND METHODS OF USING SAME - A variable-resistance material memory array includes a series of variable-resistance material memory cells. The series of variable-resistance material memory cells can be arranged in parallel with a corresponding series of control gates. A select gate can also be disposed in series with the variable-resistance material memory cells. Writing/reading/erasing to a given variable-resistance material memory cell can include turning off the corresponding control gate, while turning on all other control gates. Various devices can include such a variable-resistance material memory array. | 05-05-2011 |
20110110148 | MEMORY ARRAYS AND ASSOCIATED METHODS OF MANUFACTURING - Memory arrays and associated methods of manufacturing are disclosed herein. In one embodiment, a memory array includes an access line extending along a first direction and a first contact line and a second contact line extending along a second direction different from the first direction. The first and second contact lines are generally parallel to each other. The memory array also includes a memory node that includes a first memory cell electrically connected between the access line and the first contact line to form a first circuit, and a second memory cell electrically connected between the access line and the second contact line to form a second circuit different from the first circuit. | 05-12-2011 |
20110116301 | STATE MACHINE SENSING OF MEMORY CELLS - The present disclosure includes methods, devices, modules, and systems for sensing memory cells using a state machine. One method embodiment includes generating a first sensing reference according to a first output of a state machine. The method includes bifurcating a range of possible programmed levels to which a memory cell can be programmed with the first sensing reference. The method also includes generating a second sensing reference according to a second output of the state machine. The method further includes determining a programmed level of the memory cell with the second generated sensing reference. | 05-19-2011 |
20110116304 | SPIN CURRENT GENERATOR FOR STT-MRAM OR OTHER SPINTRONICS APPLICATIONS - Spin current generators and systems and methods for employing spin current generators. A spin current generator may be configured to generate a spin current polarized in one direction, or a spin current selectively polarized in two directions. The spin current generator may by employed in spintronics applications, wherein a spin current is desired. | 05-19-2011 |
20110143516 | SELF-ALIGNED, PLANAR PHASE CHANGE MEMORY ELEMENTS AND DEVICES, SYSTEMS EMPLOYING THE SAME AND METHOD OF FORMING THE SAME - Phase change memory elements, devices and systems using the same and methods of forming the same are disclosed. A memory element includes first and second electrodes, and a phase change material layer between the first and second electrodes. The phase change material layer has a first portion with a width less than a width of a second portion of the phase change material layer. The first electrode, second electrode and phase change material layer may be oriented at least partially along a same horizontal plane. | 06-16-2011 |
20110149637 | METHOD AND APPARATUS PROVIDING HIGH DENSITY CHALCOGENIDE-BASED DATA STORAGE - A data storage device and methods for storing and reading data are provided. The data storage device includes a data storage medium and second device. The data storage medium has an insulating layer, a first electrode layer over the insulating layer and at least one layer of resistance variable material over the first electrode layer. The second device includes a substrate and at least one conductive point configured to electrically contact the data storage medium. | 06-23-2011 |
20110149645 | MULTI-LEVEL PROGRAMMABLE PCRAM MEMORY - A series of phase change material layers sandwiched between a bottom electrode and a top electrode may have different phase change temperatures selected to provide a memory device having three or more discrete resistance levels, and thus three or more discrete logic levels. The non-volatile memory may form part of a logic device and/or a memory array device, as well as other devices and systems. The phase change material layers may be formed using physical deposition methods, chemical deposition methods, or using atomic layer deposition. Atomic layer deposition may reduce the overall device thermal exposure and provide improved layer thickness uniformity and sharp material boundaries at the interface of different phase change materials, thus providing improved resistance level accuracy. | 06-23-2011 |
20110149646 | TRANSIENT HEAT ASSISTED STTRAM CELL FOR LOWER PROGRAMMING CURRENT - A memory cell including magnetic materials and heating materials, and methods of programming the memory cell are provided. The memory cell includes a free region, a pinned region, and a heating region configured to generate and transfer heat to the free region when a programming current is directed to the cell. The heat transferred from the heating region increases the temperature of the free region, which decreases the magnetization and the critical switching current density of the free region. In some embodiments, the heating region may also provide a current path to the free region, and the magnetization of the free region may be switched according to the spin polarity of the programming current, programming the memory cell to a high resistance state or a low resistance state. | 06-23-2011 |
20110193165 | Floating Body Field-Effect Transistors, And Methods Of Forming Floating Body Field-Effect Transistors - In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor Si | 08-11-2011 |
20110216581 | SPIN TORQUE TRANSFER CELL STRUCTURE UTILIZING FIELD-INDUCED ANTIFERROMAGNETIC OR FERROMAGNETIC COUPLING - A magnetic memory cell including a soft magnetic layer and a coupling layer, and methods of operating the memory cell are provided. The memory cell includes a stack with a free ferromagnetic layer and a pinned ferromagnetic layer, and a soft magnetic layer and a coupling layer may also be formed as layers in the stack. The coupling layer may cause antiferromagnetic coupling to induce the free ferromagnetic layer to be magnetized in a direction antiparallel to the magnetization of the soft magnetic layer, or the coupling layer may cause ferromagnetic coupling to induce the free ferromagnetic layer to be magnetized in a direction parallel to the magnetization of the soft magnetic layer. The coupling layer, through a coupling effect, reduces the critical switching current of the memory cell. | 09-08-2011 |
20110227029 | MEMORY ELEMENTS USING SELF-ALIGNED PHASE CHANGE MATERIAL LAYERS AND METHODS OF MANUFACTURING SAME - A memory element and method of forming the same. The memory element includes a substrate supporting a first electrode, a dielectric layer over the first electrode having a via exposing a portion of the first electrode, a phase change material layer formed over sidewalls of the via and contacting the exposed portion of the first electrode, insulating material formed over the phase change material layer and a second electrode formed over the insulating material and contacting the phase change material layer. | 09-22-2011 |
20110233504 | NON-VOLATILE MEMORY WITH RESISTIVE ACCESS COMPONENT - Some embodiments include apparatus and methods having a memory element configured to store information and an access component configured to allow conduction of current through the memory element when a first voltage difference in a first direction across the memory element and the access component exceeds a first voltage value and to prevent conduction of current through the memory element when a second voltage difference in a second direction across the memory element and the access component exceeds a second voltage value, wherein the access component includes a material excluding silicon. | 09-29-2011 |
20110236568 | MEMORY CELL HAVING NONMAGNETIC FILAMENT CONTACT AND METHODS OF OPERATING AND FABRICATING THE SAME - A magnetic cell structure including a nonmagnetic filament contact, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, an insulative layer between the free and pinned layers, and a nonmagnetic filament contact in the insulative layer which electrically connects the free and pinned layers. The nonmagnetic filament contact is formed from a nonmagnetic source layer, also between the free and pinned layers. The filament contact directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell. | 09-29-2011 |
20110253965 | VERTICAL TRANSISTOR PHASE CHANGE MEMORY - Vertical transistor phase change memory and methods of processing phase change memory are described herein. One or more methods include forming a dielectric on at least a portion of a vertical transistor, forming an electrode on the dielectric, and forming a vertical strip of phase change material on a portion of a side of the electrode and on a portion of a side of the dielectric extending along the electrode and the dielectric into contact with the vertical transistor. | 10-20-2011 |
20110255331 | MEMORY CELLS WITH RECTIFYING DEVICE - Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further, methods and devices for addressing and accessing cells are shown that provide a simple and efficient way to manage devices with multiple cells associated with each access transistor. Examples of multiple cell devices include phase change memory devices with multiple cells associated with each access transistor. | 10-20-2011 |
20110299329 | BOTTOM ELECTRODE GEOMETRY FOR PHASE CHANGE MEMORY - A PCRAM cell has a gradated or layered resistivity bottom electrode with higher resistivity closer to a phase change material, to provide partial heating near the interface between the cell and the bottom electrode, preventing separation of the amorphous GST region from the bottom electrode, and reducing the programming current requirements. The bottom electrode can also be tapered to have a smaller cross-sectional area at the top of the bottom electrode than at the bottom of the bottom electrode. | 12-08-2011 |
20120014166 | RESISTIVE MEMORY - The present disclosure includes resistive memory devices and systems having resistive memory cells, as well as methods for operating the resistive memory cells. One memory device embodiment includes at least one resistive memory element, a programming circuit, and a sensing circuit. For example, the programming circuit can include a switch configured to select one of N programming currents for programming the at least one resistive memory element, where each of the N programming currents has a unique combination of current direction and magnitude, with N corresponding to the number of resistance states of the at least one memory element. In one or more embodiments, the sensing circuit can be arranged for sensing of the N resistance states. | 01-19-2012 |
20120015475 | Methods Of Forming Memory Cells, And Methods Of Patterning Chalcogenide-Containing Stacks - Some embodiments include methods of forming memory cells. Chalcogenide is formed over a plurality of bottom electrodes, and top electrode material is formed over the chalcogenide. Sacrificial material is formed over the top electrode material. A plurality of memory cell structures is formed by etching through the sacrificial material, top electrode material and chalcogenide. Each of the memory cell structures has a cap of the sacrificial material thereover. The etching forms polymeric residue over the sacrificial material caps, and damages chalcogenide along sidewalls of the structures. The sacrificial material is removed with an HF-containing solution, and such removes the polymeric residue off of the memory cell structures. After the sacrificial material is removed, the sidewalls of the structures are treated with one or both of H | 01-19-2012 |
20120018694 | REPRODUCIBLE RESISTANCE VARIABLE INSULATING MEMORY DEVICES AND METHODS FOR FORMING SAME - The present invention relates to the use of a shaped bottom electrode in a resistance variable memory device. The shaped bottom electrode ensures that the thickness of the insulating material at the tip of the bottom electrode is thinnest, creating the largest electric field at the tip of the bottom electrode. The arrangement of electrodes and the structure of the memory element makes it possible to create conduction paths with stable, consistent and reproducible switching and memory properties in the memory device. | 01-26-2012 |
20120037878 | ENCAPSULATED PHASE CHANGE CELL STRUCTURES AND METHODS - Methods and devices associated with phase change cell structures are described herein. In one or more embodiments, a method of forming a phase change cell structure includes forming a substrate protrusion that includes a bottom electrode, forming a phase change material on the substrate protrusion, forming a conductive material on the phase change material, and removing a portion of the conductive material and a portion of the phase change material to form an encapsulated stack structure. | 02-16-2012 |
20120056146 | RESISTIVE MEMORY ARCHITECTURES WITH MULTIPLE MEMORY CELLS PER ACCESS DEVICE - A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices. | 03-08-2012 |
20120057391 | Memory Cells, Memory Cell Programming Methods, Memory Cell Reading Methods, Memory Cell Operating Methods, and Memory Devices - Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline. | 03-08-2012 |
20120063198 | Methods Of Forming Memory Cells And Methods Of Forming Programmed Memory Cells - In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region; and a drain region on an opposing side of the channel region from the source region. The channel region has phase change material adjacent the drain region. In some embodiments, the phase change material may be adjacent both the source region and the drain region. Some embodiments include methods of programming a memory cell that has phase change material adjacent a drain region. An inversion layer is formed within the channel region adjacent the gate dielectric, with the inversion layer having a pinch-off region within the phase change material adjacent the drain region. Hot carriers (for instance, electrons) within the pinch-off region are utilized to change a phase within the phase change material. | 03-15-2012 |
20120074370 | PHASE CHANGE MEMORY STRUCTURES AND METHODS - Methods, devices, and systems associated with phase change memory structures are described herein. One or more embodiments of the present disclosure can reduce thermal crosstalk associated with phase change memory cells, which can provide various benefits including improved data reliability and retention and decreased read and/or write times, among various other benefits. One or more embodiments can reduce the number of processing steps associated with providing local interconnects to phase change memory arrays. | 03-29-2012 |
20120074371 | RESISTANCE VARIABLE MEMORY DEVICE WITH NANOPARTICLE ELECTRODE AND METHOD OF FABRICATION - A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of the nanoparticle. | 03-29-2012 |
20120097913 | Integrated Circuitry Comprising Nonvolatile memory Cells And Methods Of Forming A Nonvolatile Memory Cell - An integrated circuit has a nonvolatile memory cell that includes a first electrode, a second electrode, and an ion conductive material there-between. At least one of the first and second electrodes has an electrochemically active surface received directly against the ion conductive material. The second electrode is elevationally outward of the first electrode. The first electrode extends laterally in a first direction and the ion conductive material extends in a second direction different from and intersecting the first direction. The first electrode is received directly against the ion conductive material only where the first and second directions intersect. Other embodiments, including method embodiments, are disclosed. | 04-26-2012 |
20120120721 | UNIDIRECTIONAL SPIN TORQUE TRANSFER MAGNETIC MEMORY CELL STRUCTURE - Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents. | 05-17-2012 |
20120132881 | CROSS-POINT MEMORY WITH SELF-DEFINED MEMORY ELEMENTS - Some embodiments include a memory device having first structures arranged in a first direction and second structures arranged in a second direction. At least one structure among the first and second structures includes a semiconductor material. The second structures contact the first structures at contact locations. A region at each of the contact locations is configured as memory element to store information based on a resistance of the region. The structures can include nanowires. Other embodiments are described. | 05-31-2012 |
20120132884 | SELF-ALIGNED, PLANAR PHASE CHANGE MEMORY ELEMENTS AND DEVICES, SYSTEMS EMPLOYING THE SAME AND METHODS OF FORMING THE SAME - Phase change memory elements, devices and systems using the same and methods of forming the same are disclosed. A memory element includes first and second electrodes, and a phase change material layer between the first and second electrodes. The phase change material layer has a first portion with a width less than a width of a second portion of the phase change material layer. The first electrode, second electrode and phase change material layer may be oriented at least partially along a same horizontal plane. | 05-31-2012 |
20120135581 | MEMORY DEVICES AND METHODS OF FORMING THE SAME - Memory devices having a plurality of memory cells, with each memory cell including a phase change material having a laterally constricted portion thereof. The laterally constricted portions of adjacent memory cells are vertically offset and positioned on opposite sides of the memory device. Also disclosed are memory devices having a plurality of memory cells, with each memory cell including first and second electrodes having different widths. Adjacent memory cells have the first and second electrodes offset on vertically opposing sides of the memory device. Methods of forming the memory devices are also disclosed. | 05-31-2012 |
20120140542 | Arrays of Nonvolatile Memory Cells - Disclosed is an array of nonvolatile memory cells includes five memory cells per unit cell. Also disclosed is an array of vertically stacked tiers of nonvolatile memory cells that includes five memory cells occupying a continuous horizontal area of 4F | 06-07-2012 |
20120140555 | MULTILEVEL PHASE CHANGE MEMORY OPERATION - Methods, devices, and systems associated with multilevel phase change memory cells are described herein. One or more embodiments of the present disclosure include operating a phase change memory device by placing a phase change memory cell in a reset state and applying a selected programming pulse to the phase change memory cell in order to program the cell to one of a number of intermediate states between the reset state and a set state associated with the cell. The selected programming pulse includes an uppermost magnitude applied for a particular duration, the particular duration depending on to which one of the number of intermediate states the memory cell is to be programmed. | 06-07-2012 |
20120168705 | Bipolar Switching Memory Cell With Built-in "On" State Rectifying Current-Voltage Characteristics - A memory array is disclosed having bipolar current-voltage (IV) resistive random access memory cells with built-in “on” state rectifying IV characteristics. In one embodiment, a bipolar switching resistive random access memory cell may have a metal/solid electrolyte/semiconductor stack that forms a Schottky diode when switched to the “on” state. In another embodiment, a bipolar switching resistive random access memory cell may have a metal/solid electrolyte/tunnel barrier/electrode stack that forms a metal-insulator-metal device when switched to the “on” state. Methods of operating the memory array are also disclosed. | 07-05-2012 |
20120168708 | Memory Device Constructions, Memory Cell Forming Methods, and Semiconductor Construction Forming Methods - Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a row line above the second column line and extending perpendicular to the first column line and the second column line; memory material disposed to be selectively and reversibly configured in one of two or more different resistive states; a first diode configured to conduct a first current between the first column line and the row line via the memory material; and a second diode configured to conduct a second current between the second column line and the row line via the memory material. In some embodiments, the first diode is a Schottky diode having a semiconductor anode and a metal cathode and the second diode is a Schottky diode having a metal anode and a semiconductor cathode. | 07-05-2012 |
20120182787 | CROSS-POINT MEMORY DEVICES, ELECTRONIC SYSTEMS INCLUDING CROSS-POINT MEMORY DEVICES AND METHODS OF ACCESSING A PLURALITY OF MEMORY CELLS IN A CROSS-POINT MEMORY ARRAY - Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed. | 07-19-2012 |
20120193598 | Memory Devices and Formation Methods - A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite conductivity types. After activating the dopant, the substrate is bonded to the insulator material and at least some of the substrate is removed where bonded to the insulator material. After the removing, a memory cell is formed having a word line, an access diode, a state-changeable memory element containing chalcogenide phase change material, and a bit line all electrically connected in series, the access diode containing the junction as a p-n junction. A memory device includes an adhesion material over the insulator material and bonding the word line to the insulator material. | 08-02-2012 |
20120212999 | Methods Of Forming Programmed Memory Cells - In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region; and a drain region on an opposing side of the channel region from the source region. The channel region has phase change material adjacent the drain region. In some embodiments, the phase change material may be adjacent both the source region and the drain region. Some embodiments include methods of programming a memory cell that has phase change material adjacent a drain region. An inversion layer is formed within the channel region adjacent the gate dielectric, with the inversion layer having a pinch-off region within the phase change material adjacent the drain region. Hot carriers (for instance, electrons) within the pinch-off region are utilized to change a phase within the phase change material. | 08-23-2012 |
20120218806 | Memory Cells, Methods of Forming Memory Cells, and Methods of Programming Memory Cells - Some embodiments include methods in which a memory cell is formed to have programmable material between first and second access lines, with the programmable material having two compositionally different regions. A concentration of ions and/or ion-vacancies may be altered in at least one of the regions to change a memory state of the memory cell and to simultaneously form a pn diode. Some embodiments include memory cells having programmable material with two compositionally different regions, and having ions and/or ion-vacancies diffusible into at least one of the regions. The memory cell has a memory state in which the first and second regions are of opposite conductivity type relative to one another. | 08-30-2012 |
20120223285 | RESISTIVE MEMORY CELL FABRICATION METHODS AND DEVICES - A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom electrode. The shapes of the variable resistance region and the top electrode are configured to evenly distribute a current with a generally hemispherical current density distribution around the first electrode. | 09-06-2012 |
20120223299 | METAL/OXIDE ONE TIME PROGAMMABLE MEMORY - Embodiments include memory cells having an oxide material in contact with a metal material. In one embodiment, a memory cell includes titanium nitride, titanium oxynitride in contact with the titanium nitride and copper in contact with the titanium oxynitride. A plurality of such memory cells and respective access devices can be included in a memory array. The memory cell and access device are electrically connected between an access line and a data/sense line. An array can include a plurality of memory cells vertically stacked with respective access devices. Embodiments also include methods of forming memory cells and arrays and stacking memory arrays over one another. | 09-06-2012 |
20120228573 | Memory Cell Constructions, and Methods for Fabricating Memory Cell Constructions - Some embodiments include methods for fabricating memory cell constructions. A memory cell may be formed to have a programmable material directly against a material having a different coefficient of expansion than the programmable material. A retaining shell may be formed adjacent the programmable material. The memory cell may be thermally processed to increase a temperature of the memory cell to at least about 300° C., causing thermally-induced stress within the memory cell. The retaining shell may provide a stress which substantially balances the thermally-induced stress. Some embodiments include memory cell constructions. The constructions may include programmable material directly against silicon nitride that has an internal stress of less than or equal to about 200 megapascals. The constructions may also include a retaining shell silicon nitride that has an internal stress of at least about 500 megapascals. | 09-13-2012 |
20120231604 | MEMORY DEVICES WITH ENHANCED ISOLATION OF MEMORY CELLS, SYSTEMS INCLUDING SAME AND METHODS OF FORMING SAME - Memory cells of a memory device including a variable resistance material have a cavity between the memory cells. Electronic systems include such memory devices. Methods of forming a memory device include providing a cavity between memory cells of the memory device. | 09-13-2012 |
20120248398 | VERTICAL TRANSISTOR PHASE CHANGE MEMORY - Vertical transistor phase change memory and methods of processing phase change memory are described herein. One or more methods include forming a dielectric on at least a portion of a vertical transistor, forming an electrode on the dielectric, and forming a vertical strip of phase change material on a portion of a side of the electrode and on a portion of a side of the dielectric extending along the electrode and the dielectric into contact with the vertical transistor. | 10-04-2012 |
20120248529 | METHODS OF FORMING VERTICAL FIELD-EFFECT TRANSISTOR WITH SELF-ALIGNED CONTACTS FOR MEMORY DEVICES WITH PLANAR PERIPHERY/ARRAY AND INTERMEDIATE STRUCTURES FORMED THEREBY - Methods of forming a memory device having an array portion including a plurality of array transistors and a periphery region including peripheral circuit transistor structures of the memory device, where an upper surface of the periphery region and an upper surface of the array portion are planar (or nearly planar) after formation of the peripheral circuit transistor structures and a plurality of memory cells (formed over the array transistors). The method includes forming the peripheral circuit transistor structures in the periphery region, forming the plurality of array transistors in the array portion and forming a plurality of memory cells over respective vertical transistors. Structures formed by the method have planar upper surfaces of the periphery and array regions. | 10-04-2012 |
20120248557 | CONFINED CELL STRUCTURES AND METHODS OF FORMING CONFINED CELL STRUCTURES - Techniques for reducing damage in memory cells are provided. Memory cell structures are typically formed using dry etch and/or planarization processes which damage certain regions of the memory cell structure. In one or more embodiments, certain regions of the cell structure may be sensitive to damage. For example, the free magnetic region in magnetic memory cell structures may be susceptible to demagnetization. Such regions may be substantially confined by barrier materials during the formation of the memory cell structure, such that the edges of such regions are protected from damaging processes. Furthermore, in some embodiments, a memory cell structure is formed and confined within a recess in dielectric material. | 10-04-2012 |
20120256151 | Memory Cells, Methods of Forming Memory Cells and Methods of Forming Memory Arrays - Some embodiments include memory cells which have multiple programmable material structures between a pair of electrodes. One of the programmable material structures has a first edge, and another of the programmable material structures has a second edge that contacts the first edge. Some embodiments include methods of forming an array of memory cells. First programmable material segments are formed over bottom electrodes. The first programmable material segments extend along a first axis. Lines of second programmable material are formed over the first programmable material segments, and are formed to extend along a second axis that intersects the first axis. The second programmable material lines have lower surfaces that contact upper surfaces of the first programmable material segments. Top electrode lines are formed over the second programmable material lines. | 10-11-2012 |
20120256153 | DIODE FOR VARIABLE-RESISTANCE MATERIAL MEMORIES, PROCESSES OF FORMING SAME, AND METHODS OF USING SAME - A variable-resistance material memory (VRMM) device includes a container conductor disposed over an epitaxial semiconductive prominence that is coupled to a VRMM. A VRMM device may also include a conductive plug in a recess that is coupled to a VRMM. A VRMM array may also include a conductive plug in a surrounding recess that is coupled to a VRMM. Apparatuses include the VRMM with one of the diode constructions. | 10-11-2012 |
20120261637 | OXIDE BASED MEMORY WITH A CONTROLLED OXYGEN VACANCY CONDUCTION PATH - Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming a substoichiometric oxide over the first conductive element, forming a second conductive element over the substoichiometric oxide, and oxidizing edges of the substoichiometric oxide by subjecting the substoichiometric oxide to an oxidizing environment to define a controlled oxygen vacancy conduction path near a center of the oxide. | 10-18-2012 |
20120262973 | Arrays Of Nonvolatile Memory Cells And Methods Of Forming Arrays Of Nonvolatile Memory Cells - An array of nonvolatile memory cells includes a plurality of vertically stacked tiers of nonvolatile memory cells. The tiers individually include a first plurality of horizontally oriented first electrode lines and a second plurality of horizontally oriented second electrode lines crossing relative to the first electrode lines. Individual of the memory cells include a crossing one of the first electrode lines and one of the second electrode lines and material there-between. Specifically, programmable material, a select device in series with the programmable material, and current conductive material in series between and with the programmable material and the select device are provided in series with such crossing ones of the first and second electrode lines. The material and devices may be oriented for predominant current flow in defined horizontal and vertical directions. Method and other implementations and aspects are disclosed. | 10-18-2012 |
20120275218 | SPIN TORQUE TRANSFER CELL STRUCTURE UTILIZING FIELD-INDUCED ANTIFERROMAGNETIC OR FERROMAGNETIC COUPLING - A magnetic memory cell including a soft magnetic layer and a coupling layer, and methods of operating the memory cell are provided. The memory cell includes a stack with a free ferromagnetic layer and a pinned ferromagnetic layer, and a soft magnetic layer and a coupling layer may also be formed as layers in the stack. The coupling layer may cause antiferromagnetic coupling to induce the free ferromagnetic layer to be magnetized in a direction antiparallel to the magnetization of the soft magnetic layer, or the coupling layer may cause ferromagnetic coupling to induce the free ferromagnetic layer to be magnetized in a direction parallel to the magnetization of the soft magnetic layer. The coupling layer, through a coupling effect, reduces the critical switching current of the memory cell. | 11-01-2012 |
20120281466 | PHASE CHANGE MEMORY ELEMENTS USING ENERGY CONVERSION LAYERS, MEMORY ARRAYS AND SYSTEMS INCLUDING SAME, AND METHODS OF MAKING AND USING SAME - A phase change memory element and method of forming the same. The memory element includes a phase change material layer electrically coupled to first and second conductive material layers. A energy conversion layer is formed in association with the phase change material layer, and electrically coupled to a third conductive material layer. An electrically isolating material layer is formed between the phase change material layer and the energy conversion layer. | 11-08-2012 |
20120286229 | Memory Cells - Some embodiments include a memory cell that contains programmable material sandwiched between first and second electrodes. The memory cell can further include a heating element which is directly against one of the electrodes and directly against the programmable material. The heating element can have a thickness in a range of from about 2 nanometers to about 30 nanometers, and can be more electrically resistive than the electrodes. Some embodiments include methods of forming memory cells that include heating elements directly between electrodes and programmable materials. | 11-15-2012 |
20120287704 | SPIN CURRENT GENERATOR FOR STT-MRAM OR OTHER SPINTRONICS APPLICATIONS - Spin current generators and systems and methods for employing spin current generators. A spin current generator may be configured to generate a spin current polarized in one direction, or a spin current selectively polarized in two directions. The spin current generator may by employed in spintronics applications, wherein a spin current is desired. | 11-15-2012 |
20120294077 | SPIN TORQUE TRANSFER MEMORY CELL STRUCTURES AND METHODS - Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures comprise an annular STT stack including a nonmagnetic material between a first ferromagnetic material and a second ferromagnetic material and a soft magnetic material surrounding at least a portion of the annular STT stack. | 11-22-2012 |
20120300540 | TRANSIENT HEAT ASSISTED STTRAM CELL FOR LOWER PROGRAMMING CURRENT - A memory cell including magnetic materials and heating materials, and methods of programming the memory cell are provided. The memory cell includes a free region, a pinned region, and a heating region configured to generate and transfer heat to the free region when a programming current is directed to the cell. The heat transferred from the heating region increases the temperature of the free region, which decreases the magnetization and the critical switching current density of the free region. In some embodiments, the heating region may also provide a current path to the free region, and the magnetization of the free region may be switched according to the spin polarity of the programming current, programming the memory cell to a high resistance state or a low resistance state. | 11-29-2012 |
20120305885 | VARIABLE RESISTANCE MEMORY DEVICE WITH AN INTERFACIAL ADHESION HEATING LAYER, SYSTEMS USING THE SAME AND METHODS OF FORMING THE SAME - A variable resistance memory element and method of forming the same. The memory element includes a first electrode, a resistivity interfacial layer having a first surface coupled to said first electrode; a resistance changing material, e.g. a phase change material, having a first surface coupled to a second surface of said resistivity interfacial layer, and a second electrode coupled to a second surface of said resistance changing material. | 12-06-2012 |
20120307555 | PHASE CHANGE MEMORY STRUCTURES AND METHODS - Methods, devices, and systems associated with phase change memory structures are described herein. One method of forming a phase change memory structure includes forming an insulator material on a first conductive element and on a dielectric material of a phase change memory cell, forming a heater self-aligned with the first conductive element, forming a phase change material on the heater and at least a portion of the insulator material formed on the dielectric material, and forming a second conductive element of the phase change memory cell on the phase change material. | 12-06-2012 |
20130010527 | RESISTIVE MEMORY - The present disclosure includes resistive memory devices and systems having resistive memory cells, as well as methods for operating the resistive memory cells. One memory device embodiment includes at least one resistive memory element, a programming circuit, and a sensing circuit. For example, the programming circuit can include a switch configured to select one of N programming currents for programming the at least one resistive memory element, where each of the N programming currents has a unique combination of current direction and magnitude, with N corresponding to the number of resistance states of the at least one memory element. In one or more embodiments, the sensing circuit can be arranged for sensing of the N resistance states. | 01-10-2013 |
20130011992 | CIRCUIT, BIASING SCHEME AND FABRICATION METHOD FOR DIODE ACCESSED CROSS-POINT RESISTIVE MEMORY ARRAY - Methods, systems, structures and arrays are disclosed, such as a resistive memory array which includes access devices, for example, back-to-back Zener diodes, that only allow current to pass through a coupled resistive memory cell when a voltage drop applied to the access device is greater than a critical voltage. The array may be biased to reduce standby currents and improve delay times between programming and read operations. | 01-10-2013 |
20130021836 | MEMORY ARCHITECTURE AND CELL DESIGN EMPLOYING TWO ACCESS TRANSISTORS - An improved memory array architecture and cell design is disclosed. In one embodiment, a memory array for an integrated circuit may comprise a plurality of memory cells. Each of the memory cells may comprise a material capable of holding a logic state and two access transistors coupled to the material. The two access transistors may be configured to access the logic state of the material, and may be independently selectable by two word lines of a plurality of word lines parallel to a first dimension. | 01-24-2013 |
20130064010 | MEMORY CELL HAVING NONMAGNETIC FILAMENT CONTACT AND METHODS OF OPERATING AND FABRICATING THE SAME - A magnetic cell structure including a nonmagnetic filament contact, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, an insulative layer between the free and pinned layers, and a nonmagnetic filament contact in the insulative layer which electrically connects the free and pinned layers. The nonmagnetic filament contact is formed from a nonmagnetic source layer, also between the free and pinned layers. The filament contact directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell. | 03-14-2013 |
20130064011 | STT-MRAM CELL STRUCTURE INCORPORATING PIEZOELECTRIC STRESS MATERIAL - A magnetic memory cell including a piezoelectric material, and methods of operating the memory cell are provided. The memory cell includes a stack, and the piezoelectric material may be formed as a layer in the stack or adjacent the layers of the cell stack. The piezoelectric material may be used to induce a transient stress during programming of the memory cell to reduce the critical switching current of the memory cell. | 03-14-2013 |
20130126997 | UNIDIRECTIONAL SPIN TORQUE TRANSFER MAGNETIC MEMORY CELL STRUCTURE - Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents. | 05-23-2013 |
20130130469 | VARIABLE-RESISTANCE MATERIAL MEMORIES, PROCESSES OF FORMING SAME, AND METHODS OF USING SAME - A variable-resistance material memory array includes a series of variable-resistance material memory cells. The series of variable-resistance material memory cells can be arranged in parallel with a corresponding series of control gates. A select gate can also be disposed in series with the variable-resistance material memory cells. Writing/reading/erasing to a given variable-resistance material memory cell can include turning off the corresponding control gate, while turning on all other control gates. Various devices can include such a variable-resistance material memory array. | 05-23-2013 |
20130134378 | VARIABLE-RESISTANCE MATERIAL MEMORIES AND METHODS - Variable-resistance memory material cells are contacted by vertical bottom spacer electrodes. Variable-resistance material memory spacer cells are contacted along the edge by electrodes. Processes include the formation of the bottom spacer electrodes as well as the variable-resistance material memory spacer cells. Devices include the variable-resistance memory cells. | 05-30-2013 |
20130149834 | Methods Of Forming Memory Cells, And Methods Of Patterning Chalcogenide-Containing Stacks - Some embodiments include methods of forming memory cells. Chalcogenide is formed over a plurality of bottom electrodes, and top electrode material is formed over the chalcogenide. Sacrificial material is formed over the top electrode material. A plurality of memory cell structures is formed by etching through the sacrificial material, top electrode material and chalcogenide. Each of the memory cell structures has a cap of the sacrificial material thereover. The etching forms polymeric residue over the sacrificial material caps, and damages chalcogenide along sidewalls of the structures. The sacrificial material is removed with an HF-containing solution, and such removes the polymeric residue off of the memory cell structures. After the sacrificial material is removed, the sidewalls of the structures are treated with one or both of H | 06-13-2013 |
20130149861 | CONTACT FOR MEMORY CELL - A contact for memory cells and integrated circuits having a conductive layer supported by the sidewall of a dielectric mesa, memory cells incorporating such a contact, and methods of forming such structures. | 06-13-2013 |
20130153849 | NON-VOLATILE MEMORY WITH RESISTIVE ACCESS COMPONENT - Some embodiments include apparatus and methods having a memory element configured to store information and an access component configured to allow conduction of current through the memory element when a first voltage difference in a first direction across the memory element and the access component exceeds a first voltage value and to prevent conduction of current through the memory element when a second voltage difference in a second direction across the memory element and the access component exceeds a second voltage value, wherein the access component includes a material excluding silicon. | 06-20-2013 |
20130157410 | Memory Cell Constructions, and Methods for Fabricating Memory Cell Constructions - Some embodiments include methods for fabricating memory cell constructions. A memory cell may be formed to have a programmable material directly against a material having a different coefficient of expansion than the programmable material. A retaining shell may be formed adjacent the programmable material. The memory cell may be thermally processed to increase a temperature of the memory cell to at least about 300° C., causing thermally-induced stress within the memory cell. The retaining shell may provide a stress which substantially balances the thermally-induced stress. Some embodiments include memory cell constructions. The constructions may include programmable material directly against silicon nitride that has an internal stress of less than or equal to about 200 megapascals. The constructions may also include a retaining shell silicon nitride that has an internal stress of at least about 500 megapascals. | 06-20-2013 |
20130170291 | VARIABLE RESISTANCE MEMORY WITH LATTICE ARRAY USING ENCLOSING TRANSISTORS - A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations. | 07-04-2013 |
20130215668 | MULTILEVEL PHASE CHANGE MEMORY OPERATION - Methods, devices, and systems associated with multilevel phase change memory cells are described herein. One or more embodiments of the present disclosure include operating a phase change memory device by placing a phase change memory cell in a reset state and applying a selected programming pulse to the phase change memory cell in order to program the cell to one of a number of intermediate states between the reset state and a set state associated with the cell. The selected programming pulse includes an uppermost magnitude applied for a particular duration, the particular duration depending on to which one of the number of intermediate states the memory cell is to be programmed. | 08-22-2013 |
20130240819 | Memory Devices and Formation Methods - A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite conductivity types. After activating the dopant, the substrate is bonded to the insulator material and at least some of the substrate is removed where bonded to the insulator material. After the removing, a memory cell is formed having a word line, an access diode, a state-changeable memory element containing chalcogenide phase change material, and a bit line all electrically connected in series, the access diode containing the junction as a p-n junction. A memory device includes an adhesion material over the insulator material and bonding the word line to the insulator material. | 09-19-2013 |
20130248810 | MEMORY ELEMENTS USING SELF-ALIGNED PHASE CHANGE MATERIAL LAYERS AND METHODS OF MANUFACTURING SAME - A memory element and method of forming the same. The memory element includes a substrate supporting a first electrode, a dielectric layer over the first electrode having a via exposing a portion of the first electrode, a phase change material layer formed over sidewalls of the via and contacting the exposed portion of the first electrode, insulating material formed over the phase change material layer and a second electrode formed over the insulating material and contacting the phase change material layer. | 09-26-2013 |
20130265822 | MEMORY CELL HAVING DIELECTRIC MEMORY ELEMENT - Some embodiments include apparatus and methods having a memory cell with a first electrode, a second electrode, and a dielectric located between the first and second electrodes. The dielectric may be configured to allow the memory cell to form a conductive path in the dielectric from a portion of a material of the first electrode to represent a first value of information stored in the memory cell. The dielectric may also be configured to allow the memory cell to break the conductive path to represent a second value of information stored in the memory cell. | 10-10-2013 |
20130272061 | SPIN CURRENT GENERATOR FOR STT-MRAM OR OTHER SPINTRONICS APPLICATIONS - Spin current generators and systems and methods for employing spin current generators. A spin current generator may be configured to generate a spin current polarized in one direction, or a spin current selectively polarized in two directions. The spin current generator may by employed in spintronics applications, wherein a spin current is desired. | 10-17-2013 |
20130279239 | Memory Cells, Methods of Forming Memory Cells, and Methods of Programming Memory Cells - Some embodiments include methods in which a memory cell is formed to have programmable material between first and second access lines, with the programmable material having two compositionally different regions. A concentration of ions and/or ion-vacancies may be altered in at least one of the regions to change a memory state of the memory cell and to simultaneously form a pn diode. Some embodiments include memory cells having programmable material with two compositionally different regions, and having ions and/or ion-vacancies diffusible into at least one of the regions. The memory cell has a memory state in which the first and second regions are of opposite conductivity type relative to one another. | 10-24-2013 |
20130286712 | BIPOLAR SWITCHING MEMORY CELL WITH BUILT-IN "ON" STATE RECTIFYING CURRENT-VOLTAGE CHARACTERISTICS - A memory array is disclosed having bipolar current-voltage (IV) resistive random access memory cells with built-in “on” state rectifying IV characteristics. In one embodiment, a bipolar switching resistive random access memory cell may have a metal/solid electrolyte/semiconductor stack that forms a Schottky diode when switched to the “on” state. In another embodiment, a bipolar switching resistive random access memory cell may have a metal/solid electrolyte/tunnel barrier/electrode stack that forms a metal-insulator-metal device when switched to the “on” state. Methods of operating the memory array are also disclosed. | 10-31-2013 |
20130286713 | PHASE CHANGE MEMORY ADAPTIVE PROGRAMMING - Some embodiments include methods and apparatus having a module configured to program a memory cell using a signal to cause the memory cell to have a programmed resistance value, to adjust a programming parameter value of the signal if the programmed resistance value is outside a target resistance value range, and to repeat at least one of the programming and the adjusting if the programmed resistance value is outside the target resistance value range, the signal including a different programming parameter value each time the programming is repeated. | 10-31-2013 |
20130286724 | METHOD, SYSTEM, AND DEVICE FOR HEATING A PHASE CHANGE MEMORY (PCM) CELL - Embodiments disclosed herein may relate to heating a phase change memory (PCM) cell. | 10-31-2013 |
20130286727 | SPIN TORQUE TRANSFER MEMORY CELL STRUCTURES AND METHODS - Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures comprise an annular STT stack including a nonmagnetic material between a first ferromagnetic material and a second ferromagnetic material and a soft magnetic material surrounding at least a portion of the annular STT stack. | 10-31-2013 |
20130292626 | RESISTIVE MEMORY HAVING CONFINED FILAMENT FORMATION - Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the oxide material formed in the opening. | 11-07-2013 |
20130292628 | OXIDE BASED MEMORY WITH A CONTROLLED OXYGEN VACANCY CONDUCTION PATH - Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming a substoichiometric oxide over the first conductive element, forming a second conductive element over the substoichiometric oxide, and oxidizing edges of the substoichiometric oxide by subjecting the substoichiometric oxide to an oxidizing environment to define a controlled oxygen vacancy conduction path near a center of the oxide. | 11-07-2013 |
20130295771 | METHODS AND SYSTEMS FOR POLISHING PHASE CHANGE MATERIALS - A slurry for polishing a phase change material, such as Ge—Sb—Te, or germanium-antimony-tellurium (GST), includes abrasive particles of sizes that minimize at least one of damage to (e.g., scratching of) a polished surface of phase change material, an amount of force to be applied during polishing, and a static etch rate of the phase change material, while optionally providing selectivity for the phase change material over adjacent dielectric materials. A polishing method includes applying a slurry with one or more of the above-noted properties to a phase change material, as well as bringing the polishing pad into frictional contact with the phase change material. Polishing systems are disclosed that include a plurality of sources of solids (e.g., abrasive particles) and provide for selectivity in the solids that are applied to a substrate or polishing pad. | 11-07-2013 |
20130313510 | MEMORY DEVICE HAVING SELF-ALIGNED CELL STRUCTURE - Some embodiments include apparatus and methods having a memory device with diodes coupled to memory elements. Each diode may be formed in a recess of the memory device. The recess may have a polygonal sidewall. The diode may include a first material of a first conductivity type (e.g., n-type) and a second material of a second conductive type (e.g., p-type) formed within the recess. | 11-28-2013 |
20130329479 | Arrays Of Nonvolatile Memory Cells And Methods Of Forming Arrays Of Nonvolatile Memory Cells - An array of nonvolatile memory cells includes a plurality of vertically stacked tiers of nonvolatile memory cells. The tiers individually include a first plurality of horizontally oriented first electrode lines and a second plurality of horizontally oriented second electrode lines crossing relative to the first electrode lines. Individual of the memory cells include a crossing one of the first electrode lines and one of the second electrode lines and material there-between. Specifically, programmable material, a select device in series with the programmable material, and current conductive material in series between and with the programmable material and the select device are provided in series with such crossing ones of the first and second electrode lines. The material and devices may be oriented for predominant current flow in defined horizontal and vertical directions. Method and other implementations and aspects are disclosed. | 12-12-2013 |
20140015143 | METHODS OF FORMING NANO-SCALE PORES, NANO-SCALE ELECTRICAL CONTACTS, AND MEMORY DEVICES INCLUDING NANO-SCALE ELECTRICAL CONTACTS, AND RELATED STRUCTURES AND DEVICES - Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm | 01-16-2014 |
20140024141 | STT-MRAM CELL STRUCTURES - A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, and a nonmagnetic bridge electrically connecting the free layer and the pinned layer. The shape and/or configuration of the nonmagnetic bridge directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer of the structure is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell. | 01-23-2014 |
20140051214 | Floating Body Field-Effect Transistors, and Methods of Forming Floating Body Field-Effect Transistors - In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor Si | 02-20-2014 |
20140057406 | Integrated Circuitry Comprising Nonvolatile Memory Cells And Methods Of Forming A Nonvolatile Memory Cell - An integrated circuit has a nonvolatile memory cell that includes a first electrode, a second electrode, and an ion conductive material there-between. At least one of the first and second electrodes has an electrochemically active surface received directly against the ion conductive material. The second electrode is elevationally outward of the first electrode. The first electrode extends laterally in a first direction and the ion conductive material extends in a second direction different from and intersecting the first direction. The first electrode is received directly against the ion conductive material only where the first and second directions intersect. Other embodiments, including method embodiments, are disclosed. | 02-27-2014 |
20140103288 | MEMORY ARRAYS AND ASSOCIATED METHODS OF MANUFACTURING - Memory arrays and associated methods of manufacturing are disclosed herein. In one embodiment, a memory array includes an access line extending along a first direction and a first contact line and a second contact line extending along a second direction different from the first direction. The first and second contact lines are generally parallel to each other. The memory array also includes a memory node that includes a first memory cell electrically connected between the access line and the first contact line to form a first circuit, and a second memory cell electrically connected between the access line and the second contact line to form a second circuit different from the first circuit. | 04-17-2014 |
20140138604 | METHODS FOR FORMING NARROW VERTICAL PILLARS AND INTEGRATED CIRCUIT DEVICES HAVING THE SAME - In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material. | 05-22-2014 |
20140146596 | PHASE CHANGE MEMORY ADAPTIVE PROGRAMMING - Some embodiments include methods and apparatus having a module configured to program a memory cell using a signal to cause the memory cell to have a programmed resistance value, to adjust a programming parameter value of the signal if the programmed resistance value is outside a target resistance value range, and to repeat at least one of the programming and the adjusting if the programmed resistance value is outside the target resistance value range, the signal including a different programming parameter value each time the programming is repeated. | 05-29-2014 |
20140154860 | Memory Cells, Methods of Forming Memory Cells, and Methods of Programming Memory Cells - Some embodiments include methods in which a memory cell is formed to have programmable material between first and second access lines, with the programmable material having two compositionally different regions. A concentration of ions and/or ion-vacancies may be altered in at least one of the regions to change a memory state of the memory cell and to simultaneously form a pn diode. Some embodiments include memory cells having programmable material with two compositionally different regions, and having ions and/or ion-vacancies diffusible into at least one of the regions. The memory cell has a memory state in which the first and second regions are of opposite conductivity type relative to one another. | 06-05-2014 |
20140158972 | Memory Cells and Methods of Forming Memory Cells - Some embodiments include a memory cell that contains programmable material sandwiched between first and second electrodes. The memory cell can further include a heating element which is directly against one of the electrodes and directly against the programmable material. The heating element can have a thickness in a range of from about 2 nanometers to about 30 nanometers, and can be more electrically resistive than the electrodes. Some embodiments include methods of forming memory cells that include heating elements directly between electrodes and programmable materials. | 06-12-2014 |
20140199821 | VARIABLE-RESISTANCE MATERIAL MEMORIES AND METHODS - Variable-resistance memory material cells are contacted by vertical bottom spacer electrodes. Variable-resistance material memory spacer cells are contacted along the edge by electrodes. Processes include the formation of the bottom spacer electrodes as well as the variable-resistance material memory spacer cells. Devices include the variable-resistance memory cells. | 07-17-2014 |
20140209851 | Memory Cell Constructions, and Methods for Fabricating Memory Cell Constructions - Some embodiments include methods for fabricating memory cell constructions. A memory cell may be formed to have a programmable material directly against a material having a different coefficient of expansion than the programmable material. A retaining shell may be formed adjacent the programmable material. The memory cell may be thermally processed to increase a temperature of the memory cell to at least about 300° C., causing thermally-induced stress within the memory cell. The retaining shell may provide a stress which substantially balances the thermally-induced stress. Some embodiments include memory cell constructions. The constructions may include programmable material directly against silicon nitride that has an internal stress of less than or equal to about 200 megapascals. The constructions may also include a retaining shell silicon nitride that has an internal stress of at least about 500 megapascals. | 07-31-2014 |
20140217350 | Arrays Of Memory Cells And Methods Of Forming An Array Of Memory Cells - An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. The pillars individually include a memory cell. Outer access lines are elevationally outward of the pillars and the buried access lines. The outer access lines are of higher electrical conductivity than the buried access lines. A plurality of conductive vias is spaced along and electrically couple pairs of individual of the buried and outer access lines. A plurality of the pillars is between immediately adjacent of the vias along the pairs. Electrically conductive metal material is directly against tops of the buried access lines and extends between the pillars along the individual buried access lines. Other embodiments, including method, are disclosed. | 08-07-2014 |
20140217352 | Memory Cells, Methods of Forming Memory Cells and Methods of Forming Memory Arrays - Some embodiments include memory cells which have multiple programmable material structures between a pair of electrodes. One of the programmable material structures has a first edge, and another of the programmable material structures has a second edge that contacts the first edge. Some embodiments include methods of forming an array of memory cells. First programmable material segments are formed over bottom electrodes. The first programmable material segments extend along a first axis. Lines of second programmable material are formed over the first programmable material segments, and are formed to extend along a second axis that intersects the first axis. The second programmable material lines have lower surfaces that contact upper surfaces of the first programmable material segments. Top electrode lines are formed over the second programmable material lines. | 08-07-2014 |
20140220763 | Memory Devices and Formation Methods - A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite conductivity types. After activating the dopant, the substrate is bonded to the insulator material and at least some of the substrate is removed where bonded to the insulator material. After the removing, a memory cell is formed having a word line, an access diode, a state-changeable memory element containing chalcogenide phase change material, and a bit line all electrically connected in series, the access diode containing the junction as a p-n junction. A memory device includes an adhesion material over the insulator material and bonding the word line to the insulator material. | 08-07-2014 |
20140246642 | ENCAPSULATED PHASE CHANGE CELL STRUCTURES AND METHODS - Methods and devices associated with phase change cell structures are described herein. In one or more embodiments, a method of forming a phase change cell structure includes forming a substrate protrusion that includes a bottom electrode, forming a phase change material on the substrate protrusion, forming a conductive material on the phase change material, and removing a portion of the conductive material and a portion of the phase change material to form an encapsulated stack structure. | 09-04-2014 |
20140246645 | Arrays Of Nonvolatile Memory Cells And Methods Of Forming Arrays Of Nonvolatile Memory Cells - An array of nonvolatile memory cells includes a plurality of vertically stacked tiers of nonvolatile memory cells. The tiers individually include a first plurality of horizontally oriented first electrode lines and a second plurality of horizontally oriented second electrode lines crossing relative to the first electrode lines. Individual of the memory cells include a crossing one of the first electrode lines and one of the second electrode lines and material there-between. Specifically, programmable material, a select device in series with the programmable material, and current conductive material in series between and with the programmable material and the select device are provided in series with such crossing ones of the first and second electrode lines. The material and devices may be oriented for predominant current flow in defined horizontal and vertical directions. Method and other implementations and aspects are disclosed. | 09-04-2014 |
20140247640 | MEMORY ARCHITECTURE AND CELL DESIGN EMPLOYING TWO ACCESS TRANSISTORS - Some embodiments include an improved memory array architecture and memory cell design. In one of such embodiments, a memory cell may comprise a memory element to store a logic state and two access transistors coupled to the memory element to access the logic state of the memory element. Other embodiments are described. | 09-04-2014 |
20140264675 | MEMORY CELL HAVING NONMAGNETIC FILAMENT CONTACT AND METHODS OF OPERATING AND FABRICATING THE SAME - A magnetic cell structure including a nonmagnetic filament contact, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, an insulative layer between the free and pinned layers, and a nonmagnetic filament contact in the insulative layer which electrically connects the free and pinned layers. The nonmagnetic filament contact is formed from a nonmagnetic source layer, also between the free and pinned layers. The filament contact directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell. | 09-18-2014 |
20140346425 | PHASE CHANGE MEMORY CELL WITH CONSTRICTION STRUCTURE - Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described. | 11-27-2014 |
20140353571 | VERTICAL TRANSISTOR PHASE CHANGE MEMORY - Vertical transistor phase change memory and methods of processing phase change memory are described herein. One or more methods include forming a dielectric on at least a portion of a vertical transistor, forming an electrode on the dielectric, and forming a vertical strip of phase change material on a portion of a side of the electrode and on a portion of a side of the dielectric extending along the electrode and the dielectric into contact with the vertical transistor. | 12-04-2014 |
20140363947 | RESISTIVE MEMORY CELL FABRICATION METHODS AND DEVICES - A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom electrode. The shapes of the variable resistance region and the top electrode are configured to evenly distribute a current with a generally hemispherical current density distribution around the first electrode. | 12-11-2014 |
20150021541 | RESISTIVE MEMORY HAVING CONFINED FILAMENT FORMATION - Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the oxide material formed in the opening. | 01-22-2015 |
20150041753 | NANO-SCALE ELECTRICAL CONTACTS, MEMORY DEVICES INCLUDING NANO-SCALE ELECTRICAL CONTACTS, AND RELATED STRUCTURES AND DEVICES - Electrical contacts may be formed by forming dielectric liners along sidewalk of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of as first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm | 02-12-2015 |
20150041754 | RESISTANCE VARIABLE MEMORY DEVICE WITH NANOPARTICLE ELECTRODE AND METHOD OF FABRICATION - A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of the nanoparticle. | 02-12-2015 |
20150050795 | DIODE FOR VARIABLE-RESISTANCE MATERIAL MEMORIES, PROCESSES OF FORMING SAME, AND METHODS OF USING SAME - A variable-resistance material memory (VRMM) device includes a container conductor disposed over an epitaxial semiconductive prominence that is coupled to a VRMM. A VRMM device may also include a conductive plug in a recess that is coupled to a VRMM. A VRMM array may also include a conductive plug in a surrounding recess that is coupled to a VRMM. Apparatuses include the VRMM with one of the diode constructions. | 02-19-2015 |
20150054067 | Integrated Circuitry Comprising Nonvolatile Memory Cells And Methods Of Forming A Nonvolatile Memory Cell - A method of forming a gate construction of a recessed access device includes forming a pair of sidewall spacers laterally over opposing sidewalls of a gate dielectric and elevationally over first conductive gate material. The gate dielectric, the first conductive gate material, and the sidewall spacers are received within a trench formed in semiconductive material. Second conductive gate material is deposited within the semiconductive material trench between the pair of sidewall spacers in electrical connection with the first conductive gate material. Other implementations are disclosed, including recessed access device gate constructions independent of method of manufacture. | 02-26-2015 |
20150060754 | MEMORY DEVICES HAVING ELECTRODES COMPRISING NANOWIRES, SYSTEMS INCLUDING SAME AND METHODS OF FORMING SAME - Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices. | 03-05-2015 |
20150078056 | Arrays Of Nonvolatile Memory Cells - Disclosed is an array of nonvolatile memory cells includes five memory cells per unit cell. Also disclosed is an array of vertically stacked tiers of nonvolatile memory cells that includes five memory cells occupying a continuous horizontal area of 4F | 03-19-2015 |
20150078073 | UNIDIRECTIONAL SPIN TORQUE TRANSFER MAGNETIC MEMORY CELL STRUCTURE - Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents. | 03-19-2015 |