Patent application number | Description | Published |
20080246078 | Charge trap flash memory device and memory card and system including the same - A charge trap flash memory device and method of making same are provided. The device includes: a tunnel insulating layer, a charge trap layer; a blocking insulating layer; and a gate electrode sequentially formed on a substrate. The charge trap layer includes: plural trap layers comprising a first material having a first band gap energy level; spaced apart nanodots, each nanodot being at least partially surrounded by at least one of the trap layers, wherein the nanodots comprise a second material having a second band gap energy level that is lower than the first band gap energy level; and an intermediate blocking layer comprising a third material having a third band gap energy level that is higher than the first band gap energy level, formed between at least two of the trap layers. This structure prevents loss of charges from the charge trap layer and improves charge storage capacity. | 10-09-2008 |
20090239367 | Nonvolatile memory device and method of fabricating the same - A method of fabricating a nonvolatile memory device includes forming a tunnel insulating layer on a semiconductor substrate, forming a charge storage layer on the tunnel insulating layer, forming a dielectric layer on the charge storage layer, the dielectric layer including a first aluminum oxide layer, a silicon oxide layer, and a second aluminum oxide layer sequentially stacked on the charge storage layer, and forming a gate electrode on the dielectric layer, the gate electrode directly contacting the second aluminum oxide layer of the dielectric layer. | 09-24-2009 |
20100210116 | METHODS OF FORMING VAPOR THIN FILMS AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES INCLUDING THE SAME - A method of forming a vapor thin film is provided, which includes loading a substrate into a chamber, adsorbing a source gas on the substrate by supplying the source gas into the chamber, and forming the thin film on the substrate by supplying a reaction gas into the chamber, wherein the forming of the thin film on the substrate is proceeded under an electric field formed in one direction on the substrate by applying a bias to the substrate. | 08-19-2010 |
20100240207 | METHODS OF MANUFACTURING CHARGE TRAP TYPE MEMORY DEVICES - Manufacturing of a charge trap type memory device can include forming a tunnel insulating layer on a substrate. A charge-trapping layer can be formed on the tunnel insulating layer. A blocking layer can be formed on the charge-trapping layer. Gate electrodes can be formed on the blocking layer and divided by a trench. A portion of the charge-trapping layer aligned with the trench may be converted into a charge-blocking pattern with a vertical side profile by an anisotropic oxidation process. | 09-23-2010 |
20110165750 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING STRUCTURES - In methods of manufacturing a semiconductor device, a plurality of gate structures spaced apart from each other and oxide layer patterns. A sputtering process using the oxide layer patterns as a sputtering target to connect the oxide layer patterns on the adjacent gate structures to each other is performed, so that a gap is formed between the gate structures. A volume of the gap is formed uniformly to have desired volume by controlling a thickness of the oxide layer patterns. | 07-07-2011 |
20110281379 | METHODS OF FORMING CONDUCTIVE LAYER PATTERNS USING GAS PHASE CLEANING PROCESS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - Methods of forming conductive patterns include forming a conductive layer including a metal element on a substrate. The conductive layer is partially etched to generate a residue including an oxide of the metal element and to form a plurality of separately formed conductive layer patterns. A cleaning gas is inflowed onto the substrate including the conductive layer pattern. The metal compound is evaporated to remove the metal element contained in the residue and to form an insulating interface layer on the conductive layer pattern and a surface portion of the substrate through a reaction of a portion of the cleaning gas and oxygen. The residue may be removed from the conductive layer pattern to suppress generation of a leakage current. | 11-17-2011 |
20110300686 | Methods of Fabricating Non-Volatile Memory Devices - Methods of forming non-volatile memory devices include forming a semiconductor layer having a first impurity region of first conductivity type extending adjacent a first side thereof and a second impurity region of second conductivity type extending adjacent a second side thereof, on a substrate. A first electrically conductive layer is also provided, which is electrically coupled to the first impurity region. The semiconductor layer is converted into a plurality of semiconductor diodes having respective first terminals electrically coupled to the first electrically conductive layer. The first electrically conductive layer operates as a word line or bit line of the non-volatile memory device. The converting may include patterning the first impurity region into a plurality of cathodes or anodes of the plurality of semiconductor diodes (e.g., P-i-N diodes). | 12-08-2011 |
20120001264 | ETCHANTS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES USING THE SAME - Provided according to embodiments of the present invention are methods of fabricating semiconductor devices using an etchant. In some embodiments, the etchant may be highly selective and may act to reduce interference between wordlines in the semiconductor device. In some embodiments of the invention, provided are methods of fabricating a semiconductor device that include forming a plurality of gate patterns on a substrate; forming first insulation layers between the gate patterns; wet-etching the first insulation layers to form first insulation layer residues; and forming air gaps between the plurality of gate patterns. Related etchant solutions and semiconductor devices are also provided. | 01-05-2012 |
20120064707 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A semiconductor device includes gate structures including a tunnel insulating layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially disposed on a substrate. The control gate includes an impurity doped polysilicon layer pattern and a metal layer pattern. The gate structures are spaced apart from each other on the substrate. A capping layer pattern is disposed on a sidewall portion of the metal layer pattern and includes a metal oxide. An insulating layer covers the gate structures and the capping layer pattern. The insulating layer is formed on the substrate and includes an air-gap therein. | 03-15-2012 |
20120267702 | VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A device includes a first GSL, a plurality of first word lines, a first SSL, a plurality of first insulation layer patterns, and a first channel. The first GSL, the first word lines, and the first SSL are spaced apart from each other on a substrate in a first direction perpendicular to a top surface of a substrate. The first insulation layer patterns are between the first GSL, the first word lines and the first SSL. The first channel on the top surface of the substrate extends in the first direction through the first GSL, the first word lines, the first SSL, and the first insulation layer patterns, and has a thickness thinner at a portion thereof adjacent to the first SSL than at portions thereof adjacent to the first insulation layer patterns. | 10-25-2012 |
20120276702 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a channel region, forming a buffer layer on the channel region, and heat-treating the channel region by using a gas containing halogen atoms. | 11-01-2012 |
20140054676 | VERTICAL TYPE SEMICONDUCTOR DEVICES INCLUDING OXIDATION TARGET LAYERS - A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps. | 02-27-2014 |
20140322832 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes: forming a preliminary stack structure, the preliminary stack structure defining a through hole; forming a protection layer and a dielectric layer in the through hole; forming a channel pattern, a gapfill pattern, and a contact pattern in the through hole; forming an offset oxide on the preliminary stack structure; measuring thickness data of the offset oxide; and scanning the offset oxide using a reactive gas cluster ion beam. The scanning the offset oxide includes setting a scan speed based on the measured thickness data of the offset oxide, and forming a gas cluster. | 10-30-2014 |
20140332875 | VERTICAL MEMORY DEVICES AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a vertical memory device is disclosed. In the method, a plurality of insulation layers and a plurality of first sacrificial layers are alternately stacked on a substrate. A plurality of holes is formed through the plurality of insulation layers and first sacrificial layers. A plasma treatment process is performed to oxidize the first sacrificial layers exposed by the holes. A plurality of second sacrificial layer patterns project from sidewalls of the holes. A blocking layer pattern, a charge storage layer pattern and a tunnel insulation layer pattern are formed on the sidewall of the holes that cover the second sacrificial layer patterns. A plurality of channels is formed to fill the holes. The first sacrificial layers and the second sacrificial layer patterns are removed to form a plurality of gaps exposing a sidewall of the blocking layer pattern. A plurality of gate electrodes is formed to fill the gaps. | 11-13-2014 |