Patent application number | Description | Published |
20080245774 | Laser-rotate arc hybrid welding system and thereof method - The present invention relates to a laser-rotating arc hybrid welding system and a welding method using the system. The laser-rotating arc hybrid welding system of the present invention includes an arc discharge unit ( | 10-09-2008 |
20090111238 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE CAPABLE OF INCREASING CURRENT DRIVABILITY OF PMOS TRANSISTOR - A semiconductor device capable of selectively applying different stresses for increasing current drivability of PMOS transistor is made by defining trenches in a semiconductor substrate having a PMOS region; forming selectively a buffer layer on sidewalls of the trenches; forming an insulation layer to fill the trenches; annealing the semiconductor substrate such that compressive stress is applied in a channel length direction of a PMOS transistor by oxidizing the buffer layer; removing portions of the insulation layer and thereby forming an isolation layer; and forming the PMOS transistor on the PMOS region of the semiconductor substrate. | 04-30-2009 |
20090124094 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE TO PREVENT DEFECTS DUE TO INSULATION LAYER VOLUME CHANGE - A semiconductor device is made by forming patterns on a semiconductor substrate. After forming the patterns, sequentially forming a spacer layer, an oxidation promotion layer and a buffer layer on the semiconductor substrate including the surfaces of the patterns previously formed. An insulation layer is then formed on the buffer layer to fill the patterns. The semiconductor substrate including the insulation layer is subsequently annealed such that the buffer layer is oxidized and the insulation layer is baked. | 05-14-2009 |
20090142925 | METHOD FOR FORMING TUNGSTEN FILM HAVING LOW RESISTIVITY AND GOOD SURFACE ROUGHNESS AND METHOD FOR FORMING WIRING OF SEMICONDUCTOR DEVICE USING THE SAME - A method for forming a tungsten film includes forming a tungsten nucleation layer having an amorphous-phase or a β-phase over a semiconductor substrate. A first tungsten layer having a crystalline α-phase is then formed over the tungsten nucleation layer to form a low resistivity tungsten film. A second tungsten layer is formed over the first tungsten layer by a physical vapor deposition process, and the second tungsten layer has a large grain size similar to that of the low resistivity tungsten film. The tungsten film has both good surface roughness and low resistivity, thus enhancing the production yield and reliability of a semiconductor device. | 06-04-2009 |
20090267180 | SEMICONDUCTOR DEVICE HAVING A REDUCED FUSE THICKNESS AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device that has a reduced fuse thickness without compromising the bondability of an associated pad and a method for manufacturing the same is described. The semiconductor device includes a pad and a fuse formed on a planar level. The pad and fuse are formed using a metal according to the metal used for the planar level on which the pad and fuse are formed. The pad is formed such that the center portion of the pad is positioned lower than that of the fuse. During the opening of the pad, the thickness of the fuse is reduced without reducing the thickness of the pad. A subsequent repair process can then be easily performed on the fuse having the reduced thickness without degrading the bondability of the pad. | 10-29-2009 |
20100167538 | METHOD FOR REMOVING NATIVE OXIDE REMAINING ON A SURFACE OF A SEMICONDUCTOR DEVICE DURING MANUFACTURING - A method for removing native oxide that remains on a surface of a semiconductor device is presented. The manufacturing method includes the steps of placing, supplying, moving, and annealing. The placing step includes placing a semiconductor substrate into a first process chamber. The supplying step includes supplying an etchant gas that reacts with the native oxide when the first process chamber is purged and sealed away from air. The moving step includes moving the semiconductor substrate with the byproduct formed on it into a second process chamber in which the moving step can be exposed to air. The annealing the semiconductor substrate in the second process chamber removes the byproduct. | 07-01-2010 |
20120007171 | SEMICONDUCTOR MEMORY DEVICE HAVING VERTICAL TRANSISTOR AND BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME - A semiconductor memory device includes an active region protruding upward from a substrate, wherein the active region is arranged next to a trench on the substrate, a first impurity region formed at an upper portion of the active region, a second impurity region formed at a lower portion of the active region, a gate dielectric layer formed along a side of the active region between the first impurity region and the second impurity region, a gate electrode layer formed on the gate dielectric layer, a buried bit line formed at a lower portion of the trench, and a polysilicon layer formed over the buried bit line, wherein the polysilicon layer electrically connects the buried bit line with the second impurity region. | 01-12-2012 |
20120009760 | METHOD FOR FABRICATING ETCHING BARRIER BY USING SHADOW EFFECT AND METHOD FOR FABRICATING ONE SIDE CONTACT OF VERTICAL TRANSISTOR USING THE SAME - A method for fabricating an etching barrier includes forming wall bodies with a trench in between the wall bodies in a semiconductor substrate. An etching barrier is formed by performing a deposition having a directionality in an oblique direction with respect to the surface of the semiconductor substrate, wherein one of two bottom edge portions of the trench is not covered by the deposition due to a shadow effect by upper portions of the wall bodies. | 01-12-2012 |
20120135573 | METHOD FOR MANUFACTURING VERTICAL TRANSISTOR HAVING ONE SIDE CONTACT - A method for manufacturing a vertical transistor having a one side contact includes: forming separate active regions using trenches, on a semiconductor substrate, the active regions having first and second side surfaces facing the trenches; forming a first liner on the first and second side surfaces; forming a second liner which exposes a lower portion of the first liner on the first side surface; forming a third liner covering the portion of the first layer exposed by the second liner; forming a sacrifice layer on the third liner to fill the trench; forming an etch barrier to selectively expose upper end portions of the first to third liners positioned adjacent to the first side surface; selectively removing the third liner not covered by the etch barrier to expose a portion of the first liner not covered by the second liner; selectively removing the exposed portion of the first liner to expose a lower portion of the first side surface; and forming a buried bit line contacted with the exposed portion of the first side surface. | 05-31-2012 |
20120205779 | SEMICONDUCTOR DEVICES INCLUDING CAPACITORS AND METAL CONTACTS, AND METHODS OF FABRICATING THE SAME - Methods of fabricating a semiconductor device are provided. The method includes forming a first mold layer on a in a cell region and a peripheral region, forming first storage nodes penetrating the first mold layer in the cell region and a first contact penetrating the first mold layer in the peripheral region, forming a second mold layer on the first mold layer, forming second storage nodes that penetrate the second mold layer to be connected to respective ones of the first storage nodes, removing the second mold layer in the cell and peripheral regions and the first mold layer in the cell region to leave the first mold layer in the peripheral region, and forming a second contact that penetrates a first interlayer insulation layer to be connected to the first contact. Related devices are also provided. | 08-16-2012 |
20150017779 | SEMICONDUCTOR DEVICE HAVING STACKED STORAGE NODES OF CAPACITORS IN CELL REGION SEPARATED FROM PERIPHERAL REGION - Methods of fabricating a semiconductor device are provided. The method includes forming a first mold layer on a in a cell region and a peripheral region, forming first storage nodes penetrating the first mold layer in the cell region and a first contact penetrating the first mold layer in the peripheral region, forming a second mold layer on the first mold layer, forming second storage nodes that penetrate the second mold layer to be connected to respective ones of the first storage nodes, removing the second mold layer in the cell and peripheral regions and the first mold layer in the cell region to leave the first mold layer in the peripheral region, and forming a second contact that penetrates a first interlayer insulation layer to be connected to the first contact. Related devices are also provided. | 01-15-2015 |