Patent application number | Description | Published |
20090013358 | Distributed video recording and playback - A method may include receiving a recording request for media information from a first media system. The method may also include selecting a source of the media information and selecting a storage destination for the media information. Recording and/or playback of the media information from the source to the storage destination may be scheduled. | 01-08-2009 |
20100169502 | Hybrid method for delivering streaming media within the home - A hybrid system and method for delivering “streaming” media within the home. According to the method, small portions of media items from a controlling device are received at a rendering device for pre-caching into a cache. Upon a user selecting a media item for playback, play of the media item is immediately started from the cache in real-time while the remaining portions of the selected media item are downloaded from the controlling device and appended to cache at a rate faster than real-time. | 07-01-2010 |
20110069835 | Method and apparatus for allowing software access to navigational data in a decrypted media stream while protecting stream payloads - A method, apparatus and system enabling software access to navigational data in a decrypted media stream while protecting stream payloads. In one embodiment, a filter may route an encrypted content stream and associated information to a secure partition having a trusted computing component for decryption. Upon decryption, the trusted computing component may store the decrypted payload of the content in a secure storage location accessible to the trusted computing component. Thereafter, the decrypted navigational header information of the content may be used to navigate to the decrypted content via a trusted component such as a trusted rendering unit in the secure partition. | 03-24-2011 |
20130182837 | METHOD AND APPARATUS FOR ALLOWING SOFTWARE ACCESS TO NAVIGATIONAL DATA IN A DECRYPTED MEDIA STREAM WHILE PROTECTING STREAM PAYLOADS - A method, apparatus and system enabling software access to navigational data in a decrypted media stream while protecting stream payloads. In one embodiment, a filter may route an encrypted content stream and associated information to a secure partition having a trusted computing component for decryption. Upon decryption, the trusted computing component may store the decrypted payload of the content in a secure storage location accessible to the trusted computing component. Thereafter, the decrypted navigational header information of the content may be used to navigate to the decrypted content via a trusted component such as a trusted rendering unit in the secure partition. | 07-18-2013 |
20140223180 | METHOD AND APPARATUS FOR ALLOWING SOFTWARE ACCESS TO NAVIGATIONAL DATA IN A DECRYPTED MEDIA STREAM WHILE PROTECTING STREAM PAYLOADS - A method, apparatus and system enabling software access to navigational data in a decrypted media stream while protecting stream payloads. In one embodiment, a filter may route an encrypted content stream and associated information to a secure partition having a trusted computing component for decryption. Upon decryption, the trusted computing component may store the decrypted payload of the content in a secure storage location accessible to the trusted computing component. Thereafter, the decrypted navigational header information of the content may be used to navigate to the decrypted content via a trusted component such as a trusted rendering unit in the secure partition. | 08-07-2014 |
20140380046 | COLLABORATIVE STREAMING SYSTEM FOR PROTECTED MEDIA - The present disclosure is directed to a collaborative streaming system for protected media. A presentation device may interact with a group of trusted devices over a network to stream multimedia content. The presentation device may obtain a presentation content encryption key for presenting the content. Each trusted device in a group of trusted devices may obtain a download content encryption key allowing for download without presentation. A leader may be selected for managing the operation of the trusted devices. The leader may determine trusted device condition and assign one or more of the trusted devices to download portions of the content based on the condition. The leader may then consolidate the portions of the content and provide them to the presentation device. If the presentation device is the leader, the presentation device may perform similar operations and collect the portions of the content directly from the group of trusted devices. | 12-25-2014 |
Patent application number | Description | Published |
20080233962 | TECHNIQUES FOR ALWAYS ON ALWAYS CONNECTED OPERATION OF MOBILE PLATFORMS USING NETWORK INTERFACE CARDS - An embodiment of the present invention provides an apparatus, comprising a network interface (NIC) card operable in communication with a mobile platform to monitor network traffic and perform filtering to enable decreased system resource use in said mobile platform when in an Always On Always Connected (AOAC) state. | 09-25-2008 |
20100235504 | METHOD AND APPARATUS FOR A POWER-EFFICIENT FRAMEWORK TO MAINTAIN DATA SYNCHRONIZATION OF A MOBILE PERSONAL COMPUTER TO SIMULATE A CONNECTED SCENARIO - An apparatus and method for a power-efficient framework to maintain data synchronization of a mobile personal computer (MPC) are described. In one embodiment, the method includes the detection of a data synchronization wakeup event while the MPC is operating according to a sleep state. Subsequent to wakeup event, at least one system resource is disabled to provide a minimum number of system resources required to re-establish a network connection. In one embodiment, user data from a network server is synchronized on the MPC without user intervention; the mobile platform system resumes operation according to the sleep state. In one embodiment, a wakeup alarm is programmed according to a user history profile regarding received e-mails. In a further embodiment, data synchronizing involves disabling a display, and throttling the system processor to operate at a reduced frequency. Other embodiments are described and claimed. | 09-16-2010 |
20120005511 | Method And Apparatus For A Power-Efficient Framework to Maintain Data Synchronization of a Mobile Personal Computer to Simulate A Connected Scenario - An apparatus and method for a power-efficient framework to maintain data synchronization of a mobile personal computer (MPC) are described. In one embodiment, the method includes the detection of a data synchronization wakeup event while the MPC is operating according to a sleep state. Subsequent to wakeup event, at least one system resource is disabled to provide a minimum number of system resources required to re-establish a network connection. In one embodiment, user data from a network server is synchronized on the MPC without user intervention; the mobile platform system resumes operation according to the sleep state. In one embodiment, a wakeup alarm is programmed according to a user history profile regarding received e-mails. In a further embodiment, data synchronizing involves disabling a display, and throttling the system processor to operate at a reduced frequency. Other embodiments are described and claimed. | 01-05-2012 |
20130013948 | Method and Apparatus For A Power-Efficient Framework to Maintain Data Synchronization of a Mobile Personal Computer to Simulate A Connected Scenario - An apparatus and method for a power-efficient framework to maintain data synchronization of a mobile personal computer (MPC) are described. In one embodiment, the method includes the detection of a data synchronization wakeup event while the MPC is operating according to a sleep state. Subsequent to wakeup event, at least one system resource is disabled to provide a minimum number of system resources required to re-establish a network connection. In one embodiment, user data from a network server is synchronized on the MPC without user intervention; the mobile platform system resumes operation according to the sleep state. In one embodiment, a wakeup alarm is programmed according to a user history profile regarding received e-mails. In a further embodiment, data synchronizing involves disabling a display, and throttling the system processor to operate at a reduced frequency. Other embodiments are described and claimed. | 01-10-2013 |
20140115318 | METHOD AND APPARATUS FOR A POWER-EFFICIENT FRAMEWORK TO MAINTAIN DATA SYNCHRONIZATION OF A MOBILE PERSONAL COMPUTER TO SIMULATE A CONNECTED SCENARIO - An apparatus and method for a power-efficient framework to maintain data synchronization of a mobile personal computer (MPC) are described. In one embodiment, the method includes the detection of a data synchronization wakeup event while the MPC is operating according to a sleep state. Subsequent to wakeup event, at least one system resource is disabled to provide a minimum number of system resources required to re-establish a network connection. In one embodiment, user data from a network server is synchronized on the MPC without user intervention; the mobile platform system resumes operation according to the sleep state. In one embodiment, a wakeup alarm is programmed according to a user history profile regarding received e-mails. In a further embodiment, data synchronizing involves disabling a display, and throttling the system processor to operate at a reduced frequency. Other embodiments are described and claimed. | 04-24-2014 |
Patent application number | Description | Published |
20110147855 | DUAL SILICIDE FLOW FOR CMOS - A method for forming a semiconductor device decouples NMOS and PMOS silicide processing and thereby allows independent optimization of at least one characteristic of both NMOS and PMOS devices, and eliminates constraints of using the same silicide process for both NMOS and PMOS, which limits the degree to which the process can be optimized for either technology. | 06-23-2011 |
20110156107 | Self-aligned contacts - A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations. | 06-30-2011 |
20120264285 | RECESSED WORKFUNCTION METAL IN CMOS TRANSISTOR GATES - A transistor gate comprises a substrate having a pair of spacers disposed on a surface, a high-k dielectric conformally deposited on the substrate between the spacers, a recessed workfunction metal conformally deposited on the high-k dielectric and along a portion of the spacer sidewalls, a second workfunction metal conformally deposited on the recessed workfunction metal, and an electrode metal deposited on the second workfunction metal. The transistor gate may be formed by conformally depositing the high-k dielectric into a trench between the spacers on the substrate, conformally depositing a workfunction metal atop the high-k dielectric, depositing a sacrificial mask atop the workfunction metal, etching a portion of the sacrificial mask to expose a portion of the workfunction metal, and etching the exposed portion of the workfunction metal to form the recessed workfunction metal. The second workfunction metal and the electrode metal may be deposited atop the recessed workfunction metal. | 10-18-2012 |
20130178033 | SELF-ALIGNED CONTACTS - A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations. | 07-11-2013 |
20130264617 | NON-PLANAR TRANSISTORS AND METHODS OF FABRICATION THEREOF - The present description relates to the formation source/drain structures within non-planar transistors, wherein fin spacers are removed from the non-planar transistors in order to form the source/drain structures from the non-planar transistor fins or to replace the non-planar transistor fins with appropriate materials to form the source/drain structures. | 10-10-2013 |
20140151817 | SELF-ALIGNED CONTACTS - A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations. | 06-05-2014 |
20140339646 | NON-PLANAR TRANSITOR FIN FABRICATION - The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the doping of fins within non-planar transistors, wherein a conformal blocking material layer, such as a dielectric material, may be used to achieve a substantially uniform doping throughout the non-planar transistor fins. | 11-20-2014 |
20150069473 | TRANSISTOR FABRICATION TECHNIQUE INCLUDING SACRIFICIAL PROTECTIVE LAYER FOR SOURCE/DRAIN AT CONTACT LOCATION - Techniques are disclosed for transistor fabrication including a sacrificial protective layer for source/drain (S/D) regions to minimize contact resistance. The sacrificial protective layer may be selectively deposited on S/D regions after such regions have been formed, but prior to the deposition of an insulator layer on the S/D regions. Subsequently, after contact trench etch is performed, an additional etch process may be performed to remove the sacrificial protective layer and expose a clean S/D surface. Thus, the sacrificial protective layer can protect the contact locations of the S/D regions from contamination (e.g., oxidation or nitridation) caused by insulator layer deposition. The sacrificial protective layer can also protect the S/D regions from undesired insulator material remaining on the S/D contact surface, particularly for non-planar transistor structures (e.g., finned or nanowire/nanoribbon transistor structures). | 03-12-2015 |
20150155385 | SOURCE/DRAIN CONTACTS FOR NON-PLANAR TRANSISTORS - The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure. | 06-04-2015 |
20150270216 | SELF-ALIGNED CONTACTS - A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations. | 09-24-2015 |