Patent application number | Description | Published |
20080246545 | DIGITAL PHASE AND FREQUENCY DETECTOR - Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles. | 10-09-2008 |
20090195275 | TECHNIQUE FOR EFFICIENTLY MANAGING BOTH SHORT-TERM AND LONG-TERM FREQUENCY ADJUSTMENTS OF AN ELECTRONIC CIRCUIT CLOCK SIGNAL - A control system for generating an electronic circuit clock signal that can optimize operating frequency margins by responding to short term effects by quickly varying the clock frequency and long term effects by finding an optimal frequency point. A sensor indicates frequency margins associated with safe use of the clock signal, and these frequency margins are input into a frequency compensator and used to determine whether the system is operating within acceptable margins, or alternatively to modify the operating clock frequency on a short-term basis in order to achieve acceptable operating margins. The requests for frequency adjustment by the frequency compensator are provided to a frequency filter, which combines such request with a maintained/accumulated history of previous short-term frequency requests that have previously been made in order to determine whether an update needs to be made to the target frequency to provide long-term frequency control. | 08-06-2009 |
20090195278 | METHOD AND CIRCUIT FOR CONTROLLING CLOCK FREQUENCY OF AN ELECTRONIC CIRCUIT WITH NOISE MITIGATION - A technique to mitigate noise spikes in an electronic circuit device such as an integrated circuit. The clock frequency of a clock signal used by the electronic circuit is controlled such that instantaneously large changes to the clock frequency are avoided by use of a frequency filter that is capable of generating frequency ramps having a linear slope which is used as a feedback signal in a digital phase-locked loop clock circuit in lieu of a discrete, stair-stepped feedback control signal. | 08-06-2009 |
20090199070 | DATA TRANSMISSION SYSTEM AND METHOD OF CORRECTING AN ERROR IN PARALLEL DATA PATHS OF A DATA TRANSMISSION SYSTEM - A data transmission system includes parallel data paths for transmitting data, and an encoder for encoding the data such that an error correction code is generated for data at a same bit position across the parallel data paths. | 08-06-2009 |
20100013531 | PHASE-LOCKED LOOP CIRCUITS AND METHODS IMPLEMENTING PULSEWIDTH MODULATION FOR FINE TUNING CONTROL OF DIGITALLY CONTROLLED OSCILLATORS - PLL (phase locked loop) circuits and methods are provided in which PWM (pulse width modulation) techniques are to achieve continuous fine tuning control of DCO (digitally controlled oscillator) circuits. In general, pulse width modulation techniques are applied to further modulate dithered control signals that are used to enhance the frequency tuning resolution of the DCO such that the dithered control signals are applied to the fractional tracking control port of the DCO for a selected fraction of a full clock signal based pulse width modulation applied. | 01-21-2010 |
20100013532 | PHASE-LOCKED LOOP CIRCUITS AND METHODS IMPLEMENTING MULTIPLEXER CIRCUIT FOR FINE TUNING CONTROL OF DIGITALLY CONTROLLED OSCILLATORS - Circuits and methods are provided in which fine tuning control of a DCO (digitally controlled oscillator) circuit in a digital PLL circuit is realized by dither controlling a multiplexer circuit under digital control to selectively output one of a plurality of analog control voltages with varied voltage levels that are input to a fractional frequency control port of the DCO to drive tuning elements of the DCO at fractional frequency resolution and achieve continuous fine tuning of the DCO under analog control. | 01-21-2010 |
20100017690 | METHOD AND APPARATUS FOR LOW LATENCY PROPORTIONAL PATH IN A DIGITALLY CONTROLLED SYSTEM - A digitally controlled circuit and method includes an error input coupled to a proportional path. The proportional path includes a selector which directly receives the error input as a select signal. The selector receives a proportional control weight from a location other than the proportional path wherein the proportional control weight is input to a digitally controlled oscillator (DCO). | 01-21-2010 |
20100146369 | Soft Error Protection in Individual Memory Devices - Techniques are disclosed for minimizing the effects of soft errors associated with memory devices that are individually accessible. By way of example, a method of organizing a column in a memory array of a memory device protected by an error correction code comprises the step of maximizing a distance of the error correction code by maximizing a physical distance between memory bits associated with a memory line within the column protected by the error correction code. Other soft error protection techniques may include use of a feed forward error correction code or use of a memory operation (e.g., read or write operation) suppress and retry approach. | 06-10-2010 |
20100188158 | OPTIMAL DITHERING OF A DIGITALLY CONTROLLED OSCILLATOR WITH CLOCK DITHERING FOR GAIN AND BANDWIDTH CONTROL - A digital phase locked loop (DPLL) and method include an adjustable delay line configured to receive a reference clock as an input and to output a dithered reference clock signal. A phase and frequency detector (PFD) is configured to compare the dithered reference clock signal with a feedback clock signal to determine phase and frequency differences between the dithered reference clock signal and the feedback clock signal. A digitally controlled oscillator (DCO) is configured to receive early or late determinations from the PFD to adjust an output in accordance therewith, wherein the dithered reference clock signal distributes jitter response to enhance overall operation of the DPLL. | 07-29-2010 |
20110063003 | PHASE AND FREQUENCY DETECTOR WITH OUTPUT PROPORTIONAL TO FREQUENCY DIFFERENCE - Phase and frequency detectors and techniques are disclosed. For example, apparatus comprises a first circuit for receiving first and second clock signals and for generating at least one signal indicative of a phase difference between the first and second clock signals. The apparatus also comprises a second circuit for receiving the at least one signal generated by the first circuit and, in response to the at least one received signal, generating at least one output signal, wherein a frequency associated with the at least one output signal is proportional to a frequency difference between the first and second clock signals. | 03-17-2011 |
20120084241 | PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN A NEUROMORPHIC NETWORK UTILIZING PHASE CHANGE SYNAPTIC DEVICES - Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path. | 04-05-2012 |
20120117413 | METHOD AND INFRASTRUCTURE FOR CYCLE-REPRODUCIBLE SIMULATION ON LARGE SCALE DIGITAL CIRCUITS ON A COORDINATED SET OF FIELD-PROGRAMMABLE GATE ARRAYS (FPGAs) - A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock control state machines are coupled to the balanced clock distribution network and obtain the reference clock signal therefrom. The plurality of local clock control state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided. | 05-10-2012 |
20120242383 | PHASE PROFILE GENERATOR - Phase profile generator systems and methods are disclosed. A system includes a signal generator, a target phase trajectory module, an error detector and a control loop filter. The signal generator is configured to generate an output signal. In addition, the target phase trajectory module is configured to track a target phase trajectory and determine a next adjustment of the output signal to conform the output signal to a portion of the target phase trajectory. Further, the error detector is configured to determine an error between the output signal and a current target phase trajectory value that precedes the portion of the target phase trajectory, where the determination of the error is independent of the next adjustment of the output signal. Moreover, the control loop filter is configured to control the signal generator in accordance with both the next adjustment and the error to generate a phase profile. | 09-27-2012 |
20120259804 | RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL NETWORKS - A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array. | 10-11-2012 |
20120262149 | LOOP PARAMETER SENSOR USING REPETITIVE PHASE ERRORS - A method and system are disclosed for measuring a specified parameter in a phase-locked loop frequency synthesizer (PLL). In one embodiment, the method comprises introducing multiple phase errors in the PLL, measuring a specified aspect of the introduced phase errors, and determining a value for the specified parameter using the measured aspects of the introduced phase errors. In one embodiment, the phase errors are introduced repetitively in the PLL, and these phase errors produce a modified phase difference between the reference signal and the feedback signal in the PPL. In one embodiment, crossover times, when this modified phase difference crosses over a preset value, are determined, and these crossover times are used to determine the value for the specified parameter. In an embodiment, the parameter is calculated as a mathematical function of the crossover times. The parameter may be, for example, the bandwidth of the PLL. | 10-18-2012 |
20120317062 | RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL NETWORKS - A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array. | 12-13-2012 |
20130057327 | REDUCING PHASE LOCKED LOOP PHASE LOCK TIME - There is provided a method for reducing lock time in a phase locked loop. The method includes detecting a saturation condition on a path within the phase locked loop. The method further includes temporarily applying saturation compensation along the path when the saturation condition is detected. | 03-07-2013 |
20130057348 | Transimpedance Amplifier - A circuit includes a transimpedance amplifier portion having a first input node and a second input node, and a feedback circuit portion comprising a first transistor having a drain terminal connected to the first input node, a source terminal, and a gate terminal, a second transistor having a drain terminal connected to the second input node, a source terminal, and a gate terminal, and a third transistor having a drain terminal connected to the source terminal of the first transistor and the source terminal of the second terminal. | 03-07-2013 |
20130063192 | PLL BANDWIDTH CORRECTION WITH OFFSET COMPENSATION - A method and system for compensating for offsets when measuring parameters of a phase-locked loop (PLL). In one embodiment, a proportional path in the PLL is temporarily shut off, a measurement is made of a real time-to-zero crossing in the PLL to measure a defined parameter of the PLL, the proportional path is switched on, and the defined loop parameter is adjusted based on this measurement. In one embodiment, the real time-to-zero crossing is measured after introducing a phase step into the PLL between a reference signal and an output signal of the PLL. In an embodiment, two phase steps, having opposite polarities, are successively introduced into the PLL, and the time-to-crossing measurements resulting from these two phase steps may be averaged, and this average is used to determine a loop parameter. | 03-14-2013 |
20130063218 | FULLY DECOUPLED LC-TANK BASED OSCILLATOR TOPOLOGY FOR LOW PHASE NOISE AND HIGH OSCILLATION AMPLITUDE APPLICATIONS - There is provided a tank based oscillator. The oscillator includes one or more active devices, one or more passive devices, and a tank circuit decoupled from the active devices using at least one of the one or more passive devices. A coupling ratio between the tank circuit and the one or more active devices is set such that a maximum value of an oscillation amplitude of the tank circuit is limited based upon a breakdown of only the one or more passive devices. | 03-14-2013 |
20130076449 | VARACTOR TUNING CONTROL USING REDUNDANT NUMBERING - Techniques for improved tuning control of varactor circuits are disclosed. For example, an apparatus comprises a plurality of varactors for tuning a frequency value. The plurality of varactors comprises approximately sqrt(2N) varactors, where N is a number of tunings steps and the plurality of varactors are respectively sized as 1x, 2x, 3x, 4x, . . . , approximately sqrt(2N)x, and where x is a unit of capacitance. A given one of the N tuning steps may be represented by more than one combination of varactors. This may be referred to as redundant numbering. | 03-28-2013 |
20140049323 | TRANSIMPEDANCE AMPLIFIER - A method of forming a circuit includes forming a transimpedance amplifier having a first input node and a second input node. The method also includes forming a feedback circuit having a first transistor having a drain terminal connected to the first input node, a source terminal, and a gate terminal, a second transistor having a drain terminal connected to the second input node, a source terminal, and a gate terminal, and a third transistor having a drain terminal connected to the source terminal of the first transistor and the source terminal of the second terminal. | 02-20-2014 |
20140070855 | HYBRID PHASE-LOCKED LOOP ARCHITECTURES - Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths. | 03-13-2014 |
20140070856 | HYBRID PHASE-LOCKED LOOP ARCHITECTURES - Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths. | 03-13-2014 |
20140176198 | CALIBRATION SCHEMES FOR CHARGE-RECYCLING STACKED VOLTAGE DOMAINS - A method and system are disclosed for calibrating a mid-voltage node in an integrated circuit including an input-output circuit having charge-recycling stacked voltage domains including at least first and second voltage domains. In one embodiment, the method comprises transmitting data through the input-output circuit, including transmitting a first portion of the data across the first voltage domain, and transmitting a second portion of the data across the second voltage domain. The method further comprises measuring a specified characteristic of the data transmitted through the input-output circuit; and based on the measured specified characteristic, adjusting a voltage of said mid-voltage node to a defined value. The voltage of the mid-voltage node may be adjusted to accomplish a number of objectives, for example, to achieve a desired trade-off between power and performance, or so that the two voltage domains have the same performance. | 06-26-2014 |
20140180984 | TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY ADDRESSING FOR IMPLEMENTING A UNIVERSAL SUBSTRATE OF ADAPTATION - Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation. One embodiment comprises a neurosynaptic device including a memory device that maintains neuron attributes for multiple neurons. The module further includes multiple bit maps that maintain incoming firing events for different periods of delay and a multi-way processor. The processor includes a memory array that maintains a plurality of synaptic weights. The processor integrates incoming firing events in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes and the synaptic weights maintained. | 06-26-2014 |
20140180987 | TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY ADDRESSING FOR IMPLEMENTING A NEURAL NETWORK - Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step. | 06-26-2014 |