Patent application number | Description | Published |
20080284006 | Semiconductor devices including interlayer conductive contacts and methods of forming the same - In a semiconductor device and a method of forming the same, the semiconductor device comprises: a first insulating layer on an underlying contact region of the semiconductor device, the first insulating layer having an upper surface; a first conductive pattern in a first opening through the first insulating layer, an upper portion of the first conductive pattern being of a first width, an upper surface of the first conductive pattern being recessed relative to the upper surface of the first insulating layer so that the upper surface of the first conductive pattern has a height relative to the underlying contact region that is less than a height of the upper surface of the first insulating layer relative to the underlying contact region; and a second conductive pattern contacting the upper surface of the first conductive pattern, a lower portion of the second conductive pattern being of a second width that is less than the first width. | 11-20-2008 |
20100227473 | Methods of Forming Metal Patterns in Openings in Semiconductor Devices - A method of forming a semiconductor device is disclosed. A dielectric layer having a opening therein is formed on a semiconductor substrate. An inner surface of the opening is treated by plasma. A barrier metal layer is formed on the plasma-treated inner surface of the opening. A seed layer is formed on the barrier metal layer. A metal bulk layer is formed on the seed layer. High quality semiconductor devices can be fabricated by using these methods, which may stably fill the opening formed in the dielectric layer. | 09-09-2010 |
20100230824 | Metal Interconnect of Semiconductor Device - Provided are a metal interconnect of a semiconductor device and a method of fabricating the metal interconnect. The metal interconnect includes a metal line having a first end and a second end disposed on an opposite side to the first end, a via electrically connected to the metal line, and a non-active segment extending from the first end and including a void. Tensile stress is decreased to prevent a void from occurring under the via. Accordingly, line breakage due to electromigration is substantially prevented, thus improving electrical characteristics of the device. | 09-16-2010 |
20110097895 | SEMICONDUCTOR DEVICES INCLUDING INTERLAYER CONDUCTIVE CONTACTS AND METHODS OF FORMING THE SAME - In a semiconductor device and a method of forming the same, the semiconductor device comprises: a first insulating layer on an underlying contact region of the semiconductor device, the first insulating layer having an upper surface; a first conductive pattern in a first opening through the first insulating layer, an upper portion of the first conductive pattern being of a first width, an upper surface of the first conductive pattern being recessed relative to the upper surface of the first insulating layer so that the upper surface of the first conductive pattern has a height relative to the underlying contact region that is less than a height of the upper surface of the first insulating layer relative to the underlying contact region; and a second conductive pattern contacting the upper surface of the first conductive pattern, a lower portion of the second conductive pattern being of a second width that is less than the first width. | 04-28-2011 |
20110195569 | Semiconductor Device and Method for Forming the Same - Methods of forming field effect transistors include forming a metal alloy gate electrode (e.g., aluminum alloy) containing about 0.5 to about 1.0 atomic percent silicon, on a substrate, and electroless plating an electrically conductive gate protection layer directly on at least a portion of an upper surface of the metal alloy gate electrode. A gate dielectric layer may be formed on the substrate. This gate dielectric layer may have a dielectric constant greater than a dielectric constant of silicon dioxide. The forming of the metal alloy gate electrode may include forming a metal alloy gate electrode directly on an upper surface of the gate dielectric layer. | 08-11-2011 |
20120164826 | Methods of Forming Metal Patterns in Openings in Semiconductor Devices - A method of forming a semiconductor device is disclosed. A dielectric layer having a opening therein is formed on a semiconductor substrate. An inner surface of the opening is treated by plasma. A barrier metal layer is formed on the plasma-treated inner surface of the opening. A seed layer is formed on the barrier metal layer. A metal bulk layer is formed on the seed layer. High quality semiconductor devices can be fabricated by using these methods, which may stably fill the opening formed in the dielectric layer. | 06-28-2012 |
20130147022 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device may include an interlayer insulating layer containing hydrogen and a first passivation layer configured to prevent or inhibit an out-gassing of the hydrogen. In the method, a second passivation layer configured to control a warpage characteristic of a wafer may be formed on the first passivation layer. | 06-13-2013 |
20140042633 | SEMICONDUCTOR DEVICES INCLUDING A NON-PLANAR CONDUCTIVE PATTERN, AND METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING A NON-PLANAR CONDUCTIVE PATTERN - Semiconductor devices are provided. The semiconductor devices may include a non-planar conductive pattern. The non-planar conductive pattern may be on an insulating layer and may contact a connection terminal at a plurality of different heights. Related methods of forming semiconductor devices are also provided. | 02-13-2014 |
20140080302 | METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including forming a first sacrificial layer on a substrate, the first sacrificial layer including a conductive material, forming a second sacrificial layer on the first sacrificial layer, the second sacrificial layer including an insulating material, patterning the second sacrificial layer and the first sacrificial layer to form an opening successively penetrating the second and first sacrificial layers, conformally forming a seed layer on the second and first sacrificial layers including the opening, and forming a conductive pattern filling the opening having the seed layer by a plating process. | 03-20-2014 |
20150031195 | Method of Fabricating a Semiconductor Device - A method of fabricating a semiconductor device may include conformally forming a gate insulating layer on a substrate having a recess, conformally forming a barrier layer containing fluorine-free tungsten nitride on the substrate with the gate insulating layer using an atomic layer deposition process, and forming a gate electrode on the barrier layer to fill at least a portion of the recess. | 01-29-2015 |