Patent application number | Description | Published |
20090087951 | Method of manufacturing wafer level package - A method of manufacturing a wafer level package is disclosed. The method may include stacking an insulation layer over a wafer substrate; processing a via hole in the insulation layer; forming a seed layer over the insulation layer; forming a plating resist, which is in a corresponding relationship with a redistribution pattern, over the seed layer; forming the redistribution pattern, which includes a terminal for external contact, by electroplating; and coupling a conductive ball to the terminal. As multiple redistribution layers can be formed using inexpensive PCB processes, the manufacturing costs can be reduced, and the stability and efficiency of the process can be increased. | 04-02-2009 |
20090166859 | Semiconductor device and method of manufacturing the same - Provided is a semiconductor device including a wafer having an electrode pad; an insulating layer that is formed on the wafer and has an exposure hole formed in one side thereof, the exposure layer exposing the electrode pad, and a support post formed in the other side, the support post having a buffer groove; a redistribution layer that is formed on the top surface of the insulating layer and has one end connected to the electrode pad and the other end extending to the support post; an encapsulation layer that is formed on the redistribution layer and the insulating layer and exposes the redistribution layer formed on the support post; and a solder bump that is provided on the exposed portion of the redistribution layer. | 07-02-2009 |
20090302468 | Printed circuit board comprising semiconductor chip and method of manufacturing the same - Disclosed is a printed circuit board including a semiconductor chip, which includes a semiconductor chip having a connection pad, which is exposed, on the upper surface thereof, a first solder ball formed on the connection pad and having a first melting point, a printed circuit board having an external connection terminal formed at the outermost circuit layer thereof, and a second solder ball formed on the external connection terminal, connected to the first solder ball, and having a second melting point higher than the first melting point. In the printed circuit board including a semiconductor chip, the distance between the printed circuit board and the semiconductor chip is increased, thus realizing high resistance to flexure due to the difference in thermal expansion coefficient between the printed circuit board and the semiconductor chip. | 12-10-2009 |
20110045668 | Method of manufacturing wafer level device package - There is provided a method of manufacturing a wafer level device package, the method including: forming a conductive pad on at least one area of a substrate; forming a first insulation layer on the substrate, the first insulation layer having an opening allowing the conductive pad to be exposed; forming a wiring layer connected to the conductive pad on the first insulation layer; forming a conductive diffusion barrier layer on the wiring layer to seal the wiring layer; forming a second insulation layer on the diffusion barrier layer, the second insulation layer having a contact hole allowing a part of diffusion barrier layer to be exposed; and forming a bump pad in the contact hole. This method allows for a reduction in processing time and costs by substituting a simple electroless plating process for a complicated photolithography process in the formation of the bump pad and the diffusion barrier layer. | 02-24-2011 |
20110108993 | Semiconductor package and manufacturing method thereof - There is provided a semiconductor package including: a circuit board having a receiving space formed therein; a semiconductor chip inserted into the receiving space of the circuit board; and an electrode pattern portion having a pattern shape on one surface of the semiconductor chip, and directly contacting a via portion of the circuit board so as to be electrically connected thereto. | 05-12-2011 |
20120295404 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A method of manufacturing a semiconductor package, the method including: forming an insulating layer on a board; forming an electrode pattern portion by redistribution plating in order to make a circuit connection on the insulating layer; manufacturing a semiconductor chip by forming a protecting portion on the electrode pattern portion such that a portion of the electrode pattern portion is exposed; and mounting the semiconductor chip on a receiving space of a circuit board and electrically connecting the semiconductor chip to the circuit board. | 11-22-2012 |
20130169382 | COMMON MODE FILTER AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a common mode filter and a method for manufacturing the same. The common mode filter includes a first insulator sheet; a first circuit layer having a first-layered first coil and a first-layered second coil alternately and separately arranged; a second insulator sheet laminated on the first circuit layer; and a second circuit layer having a second-layered first coil and a second-layered second coil alternately and separately arranged, the second-layered first coil being connected to the first-layered first coil and the second-layered second coil being connected to the first-layered second coil through the plurality of penetration holes. | 07-04-2013 |
Patent application number | Description | Published |
20090309216 | WAFER LEVEL PACKAGE AND MANUFACTURING METHOD THEREOF - A wafer level package and a manufacturing method thereof capable of reducing stress between an under bump metal and a bump. The wafer level package includes a substrate provided with a plurality of chip pads on a top surface; a first passivation layer to expose the chip pads; vias connected to the chip pads by passing through the first passivation layer; a metal wiring layer formed on the first passivation layer and connected to the vias; an under bump metal formed on the first passivation layer to be connected to the metal wiring layer and having a buffer pattern separated through a trench on a center; a second passivation layer formed on the first passivation layer to expose the under bump metal; a first bump formed on the buffer pattern; and a second bump filling the trench and formed on the first bump and the under bump metal. | 12-17-2009 |
20100117218 | Stacked wafer level package and method of manufacturing the same - The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost. | 05-13-2010 |
20100144152 | Method of manufacturing semiconductor package - The present invention relates to a method of manufacturing a semiconductor package capable of simplifying a process and remarkably reducing a production cost by including the steps of: preparing a different bonded panel including at least one metal layer; forming a pad unit electrically connected to the metal layer; mounting a semiconductor chip over the different bonded panel to be electrically connected to the pad unit; sealing the semiconductor chip; forming a rearrangement wiring layer by etching the metal layer; and forming an external connection unit electrically connected to the rearrangement wiring layer. | 06-10-2010 |
20100149770 | Semiconductor stack package - The present invention relates to a semiconductor stack package including: a printed circuit board; a first semiconductor chip mounted on the printed circuit board; a second semiconductor chip mounted on the printed circuit board in parallel with the first semiconductor chip; a first rearrangement wiring layer positioned on the first semiconductor chip; a second rearrangement wiring layer which constitutes one circuit together with the first rearrangement wiring layer and is positioned on the second semiconductor chip; and a third semiconductor chip which is electrically connected to the first and second rearrangement wiring layers and of which both ends are separately positioned on the first and second semiconductor chips. | 06-17-2010 |
Patent application number | Description | Published |
20130333202 | Method for Manufacturing High Frequency Inductor - Disclosed herein is a method for manufacturing a high frequency inductor, the method including; forming a primary coil for manufacturing the high frequency inductor on a wafer; coating a primary PSV on the wafer on which the primary coil is formed; forming a secondary coil for manufacturing the high frequency inductor, after the coating of the primary PSV; coating a secondary PSV, after the forming of the secondary coil; forming a barrier layer on an electrode portion to be exposed of the high frequency inductor, after the coating of the secondary PSV; filling and curing an insulating resin on the wafer, after the forming of the barrier layer; and polishing the cured resin up to the barrier layer to expose the electrode. | 12-19-2013 |
20140062644 | THIN FILM TYPE COMMON MODE FILTER - Disclosed herein is a common mode filter including an internal electrode manufactured in a coil electrode form and provided with a simultaneous coil pattern in which two coil electrodes are overlapped with each other in a single layer in a direction in which a coil is wound, wherein a height of a second insulating layer formed on the internal electrode is higher than an interval between the coils. Therefore, a portion at which a parasitic capacitance is generated may be basically blocked, and a self resonant frequency (SRF) may be increased while filtering performance as the common mode filter is maintained. | 03-06-2014 |
20140176280 | COMMON MODE FILTER AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a common mode filter, inlcuding: an external magnetic layer; an insulating layer formed on the external magnetic layer and having coil electrodes therein; a protecting layer formed on the insulating layer; an internal magnetic layer formed inside an opening part formed in one surface of the protecting layer; and external electrode terminals passing through the protecting layer and connected with end portions of the coil electrodes, so that there can be provided a common mode filter having excellent durability, moisture resistance, and heat resistance. | 06-26-2014 |
20140176284 | COMMON MODE FILTER AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are a method of manufacturing a common mode filter forming a coil electrode by directly patterning metal layers laminated on both surfaces of a core insulating layer while not using a build-up process, and the common mode filter manufactured according to the method. | 06-26-2014 |
20140184377 | INDUCTOR - Disclosed herein is an inductor including: a substrate; an insulating part provided on the substrate; and a conductive pattern part provided in the insulating part, wherein the insulating part includes first and second insulating parts that are provided at regions physically separated from each other, the first and second insulating parts being made of materials of which at least one of dielectric constant and heat resistance are different. In the inductor according to the present invention, high Q and L values may be implemented, and deformation by heat treatment may also be decreased, thereby making it possible to improve reliability. | 07-03-2014 |
20140285304 | INDUCTOR AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein is an inductor including: a core layer having a conductive pattern formed on a surface thereof and having a through-hole formed at a region in which the conductive pattern is not formed; and a magnetic layer covering the core layer, wherein the magnetic layer includes: a filled part filled in the through-hole and having high magnetic material filling density; and a cover part covering the surface of the core layer and having magnetic material filling density lower than that of the filled part. | 09-25-2014 |
20140285305 | INDUCTOR AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to an inductor. An inductor in accordance with an embodiment of the present invention includes: an insulating layer having a hole; a conductive pattern disposed on both surfaces of the insulating layer and having a structure in which portions disposed on the both surfaces are electrically connected to each other through the hole; and a magnetic layer disposed on the insulating layer to cover the conductive pattern, wherein the conductive pattern has a plating pattern formed by performing a plating process. | 09-25-2014 |
20140320251 | THIN FILM CHIP DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein is a thin film chip device, including: a substrate; a circuit layer disposed on the substrate and having coil patterns; and a functional layer formed on the circuit layer and having an embossed shape. | 10-30-2014 |