Patent application number | Description | Published |
20090176165 | Polymer composition, hardmask composition having antireflective properties, and associated methods - A polymer composition includes an aromatic ring-containing polymer represented by Formula 1: | 07-09-2009 |
20100167203 | Resist underlayer composition and method of manufacturing semiconductor integrated circuit device using the same - A resist underlayer composition and a method of manufacturing a semiconductor integrated circuit device, the composition including a solvent and an organosilane polymer, the organosilane polymer being a condensation polymerization product of at least one first compound represented by Chemical Formulae 1 and 2 and at least one second compound represented by Chemical Formulae 3 to 5. | 07-01-2010 |
20100279509 | Silicon-based hardmask composition and process of producing semiconductor integrated circuit device using the same - A silicon-based hardmask composition, including an organosilane polymer represented by Formula 1: | 11-04-2010 |
20110129981 | FILLER FOR FILLING A GAP AND METHOD FOR MANUFACTURING SEMICONDUCTOR CAPACITOR USING THE SAME - A filler for filling a gap includes a hydrogenated polysiloxazane having an oxygen content of about 0.2 to about 3 wt %. A chemical structure of the hydrogenated polysiloxazane includes first, second, and third moieties represented by the following respective Chemical Formulas 1-3: | 06-02-2011 |
20120267766 | RESIST UNDERLAYER COMPOSITION AND PROCESS OF PRODUCING INTEGRATED CIRCUIT DEVICES USING THE SAME - A resist underlayer composition includes a solvent and an organosilane condensation polymerization product, the organosilane condensation polymerization product including about 40 to about 80 mol % of a structural unit represented by the following Chemical Formula 1, | 10-25-2012 |
20120270143 | RESIST UNDERLAYER COMPOSITION AND METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES USING THE SAME - A resist underlayer composition, including a solvent, and an organosilane condensation polymerization product including about 10 to about 40 mol % of a structural unit represented by Chemical Formula 1: | 10-25-2012 |
20120270981 | RESIST UNDERLAYER COMPOSITION AND PROCESS OF PRODUCING INTEGRATED CIRCUIT DEVICES USING THE SAME - A resist underlayer composition includes a solvent, and an organosilane condensation polymerization product of: a compound represented by the following Chemical Formula 1, a compound represented by the following Chemical Formula 2, and a compound represented by the following Chemical Formula 3, | 10-25-2012 |
20120270998 | RESIN COMPOSITION FOR TRANSPARENT ENCAPSULATION MATERIAL AND ELECTRONIC DEVICE FORMED USING THE SAME - A resin composition for a transparent encapsulation material, the resin composition including a polysiloxane obtained by copolymerization of a first silicon compound represented by the following Chemical Formula 1 and a second silicon compound including a compound represented by the following Chemical Formula 2, | 10-25-2012 |
20120282776 | PHOTORESIST UNDERLAYER COMPOSITION AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE BY USING THE SAME - A photoresist underlayer composition includes a solvent, and a polysiloxane resin represented by Chemical Formula 1: | 11-08-2012 |
Patent application number | Description | Published |
20110062448 | Field effect semiconductor devices and methods of manufacturing field effect semiconductor devices - Field effect semiconductor devices and methods of manufacturing the same are provided, the field effect semiconductor devices include a second semiconductor layer on a first surface of a first semiconductor layer, a first and a second third semiconductor layer respectively on two sides of the second semiconductor layer, a source and a drain respectively on the first and second third semiconductor layer, and a gate electrode on a second surface of the first semiconductor layer. | 03-17-2011 |
20110068370 | Power electronic devices, methods of manufacturing the same, and integrated circuit modules including the same - Power electronic devices including 2-dimensional electron gas (2DEG) channels and methods of manufacturing the same. A power electronic device includes lower and upper material layers for forming a 2DEG channel, and a gate contacting an upper surface of the upper material layer. A region below the gate of the 2DEG channel is an off region where the density of a 2DEG is reduced or zero. The entire upper material layer may be continuous and may have a uniform thickness. A region of the upper material layer under the gate contains an impurity for reducing or eliminating a lattice constant difference between the lower and upper material layers. | 03-24-2011 |
20110212582 | Method Of Manufacturing High Electron Mobility Transistor - A method of manufacturing a High Electron Mobility Transistor (HEMT) may include forming first and second material layers having different lattice constants on a substrate, forming a source, a drain, and a gate on the second material layer, and changing the second material layer between the gate and the drain into a different material layer, or changing a thickness of the second material layer, or forming a p-type semiconductor layer on the second material layer. The change in the second material layer may occur in an entire region of the second material layer between the gate and the drain, or only in a partial region of the second material layer adjacent to the gate. The p-type semiconductor layer may be formed on an entire top surface of the second material layer between the gate and the drain, or only on a partial region of the top surface adjacent to the gate. | 09-01-2011 |
20110215378 | High electron mobility transistors exhibiting dual depletion and methods of manufacturing the same - High electron mobility transistors (HEMT) exhibiting dual depletion and methods of manufacturing the same. The HEMT includes a source electrode, a gate electrode and a drain electrode disposed on a plurality of semiconductor layers having different polarities. A dual depletion region exists between the source electrode and the drain electrode. The plurality of semiconductor layers includes an upper material layer, an intermediate material layer and a lower material layer, and a polarity of the intermediate material layer is different from polarities of the upper material layer and the lower material layer. | 09-08-2011 |
20110221482 | Semiconductor device - Provided is a semiconductor device that may include a switching device having a negative threshold voltage, and a driving unit between a power terminal and a ground terminal and providing a driving voltage for driving the switching device. The switching device may be connected to a virtual ground node having a virtual ground voltage that is greater than a ground voltage supplied from the ground terminal and may be turned on when a difference between the driving voltage and the virtual ground voltage is greater than the negative threshold voltage. | 09-15-2011 |
20110272743 | High Electron Mobility Transistors Including Lightly Doped Drain Regions And Methods Of Manufacturing The Same - High electron mobility transistors (HEMTs) including lightly doped drain (LDD) regions and methods of manufacturing the same. A HEMT includes a source, a drain, a gate, a channel supplying layer for forming at least a 2-dimensional electron gas (2DEG) channel, and a channel formation layer in which at least the 2DEG channel is formed. The channel supplying layer includes a plurality of semiconductor layers having different polarizabilities. A portion of the channel supplying layer is recessed. One of the plurality of semiconductor layers, which is positioned below an uppermost layer is an etching buffer layer, as well as a channel supplying layer. | 11-10-2011 |
20110273221 | Driving circuits, power devices and electronic devices including the same - A power device includes a switching device having a control terminal and an output terminal; and a driving circuit configured to provide a driving voltage to the control terminal such that a voltage between the control terminal and the output terminal remains less than or equal to a critical voltage. A rise time required for the driving voltage to reach a target level is determined according to current-voltage characteristics of the switching device. And, when the voltage between the control terminal and the output terminal exceeds the critical voltage, leakage current is generated between the control terminal and the output terminal. | 11-10-2011 |
20110303952 | High Electron Mobility Transistors And Methods Of Fabricating The Same - A High electron mobility transistor (HEMT) includes a source electrode, a gate electrode, a drain electrode, a channel forming layer in which a two-dimensional electron gas (2DEG) channel is induced, and a channel supplying layer for inducing the 2DEG channel in the channel forming layer. The source electrode and the drain electrode are located on the channel supplying layer. A channel increase layer is between the channel supplying layer and the source and drain electrodes. A thickness of the channel supplying layer is less than about 15 nm. | 12-15-2011 |
20120037958 | POWER ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME - According to an example embodiment, a power electronic device includes a first semiconductor layer, a second semiconductor layer on a first surface of the first semiconductor layer, and a source, a drain, and a gate on the second semiconductor layer. The source, drain and gate are separate from one another. The power electronic device further includes a 2-dimensional electron gas (2DEG) region at an interface between the first semiconductor layer and the second semiconductor layer, a first insulating layer on the gate and a second insulating layer adjacent to the first insulating layer. The first insulating layer has a first dielectric constant and the second insulating layer has a second dielectric constant less than the first dielectric constant. | 02-16-2012 |
20120086049 | E-Mode High Electron Mobility Transistor And Method Of Manufacturing The Same - According to an example embodiment, a high electron mobility transistor (HEMT) includes a substrate, a buffer layer on the substrate, a channel layer on the buffer layer, and a barrier structure on the channel layer. The buffer layer includes a 2-dimensional electron gas (2DEG). A polarization of the barrier structure varies in a region corresponding to a gate electrode. The HEMT further includes and the gate electrode, a source electrode, and a drain electrode on the barrier structure. | 04-12-2012 |
20120088341 | Methods Of Manufacturing High Electron Mobility Transistors - The methods may include forming a first material layer on a substrate, increasing electric resistance of the first material layer, and forming a source pattern and a drain pattern, which are spaced apart from each other, on the first material layer, a band gap of the source and drain patterns greater than a band gap of a first material layer. | 04-12-2012 |
20120112202 | E-Mode High Electron Mobility Transistors And Methods Of Manufacturing The Same - An Enhancement-mode (E-mode) high electron mobility transistor (HEMT) includes a channel layer with a 2-Dimensional Electron Gas (2DEG), a barrier layer inducing the 2DEG in the channel layer, source and drain electrodes on the barrier layer, a depletion layer on the barrier layer between the source and drain electrodes, and a gate electrode on the depletion layer. The barrier layer is recessed below the gate electrode and the depletion layer covers a surface of the recess and extends onto the barrier layer around the recess. | 05-10-2012 |
20130001587 | HIGH ELECTRON MOBILITY TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - High electron mobility transistors (HEMTs) including a cavity below a drain and methods of manufacturing HEMTS including removing a portion of a substrate below a drain. | 01-03-2013 |
20130032816 | HIGH ELECTRON MOBILITY TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - High electron mobility transistors (HEMTs) including a substrate and a HEMT stack on the substrate, the HEMT stack including a compound semiconductor layer that includes a 2-dimensional electron gas (2DEG), an upper compound semiconductor layer that has a polarization index higher than a polarization index of the compound semiconductor layer, and a source electrode, a drain electrode, and a gate that are disposed on the upper compound semiconductor layer. The substrate may be a nitride substrate that has a dielectric constant and a thermal conductivity higher than a dielectric constant and a thermal conductivity of a silicon substrate. The substrate may include an insulating layer that has a dielectric constant and a thermal conductivity higher than a dielectric constant and a thermal conductivity of the silicon substrate, a metal layer that is deposited on the insulating layer, and a plate that is attached to the metal layer. | 02-07-2013 |
20130175538 | SUBSTRATE STRUCTURE, SEMICONDUCTOR DEVICE FABRICATED FROM THE SAME, AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE - According to example embodiments, a substrate structure may include a GaN-based third material layer, a GaN-based second material layer, a GaN-based first material layer, and a buffer layer on a non-GaN-based substrate. The GaN-based first material layer may be doped with a first conductive type impurity. The GaN-based second material layer may be doped with a second conductive type impurity at a density that is less than a density of the first conductive type impurity in the first GaN-based material layer. The GaN-based third material layer may be doped with a first conductive type impurity at a density that is less than the density of the first conductive type impurity of the GaN-based first material layer. After a second substrate is attached onto the substrate structure, the non-GaN-based substrate may be removed and a GaN-based vertical type semiconductor device may be fabricated on the second substrate. | 07-11-2013 |
20130175539 | HIGH ELECTRON MOBILITY TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - According to example embodiments, a high electron mobility transistor (HEMT) includes a channel supply layer and a channel layer. The channel layer may include an effective channel region and a high resistivity region. The effective channel region may be between the high resistivity region and the channel supply layer. The high resistivity region may be a region into which impurities are ion-implanted. According to example embodiments, a method of forming a HEMT includes forming a device unit, including a channel layer and a channel supply layer, on a first substrate; adhering a second substrate to the device unit; removing the first substrate; and forming a high resistivity region by ion-implanting impurities into at least a portion of the channel layer. | 07-11-2013 |
20130234207 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - According to example embodiments, a high electron mobility transistor (HEMT) includes: stack including a buffer layer, a channel layer containing a two dimensional electron gas (2DEG) channel, and a channel supply layer sequentially stacked on each other, the stack defining a first hole and a second hole that are spaced apart from each other. A first electrode, a second electrode, and third electrode are spaced apart from each other along a first surface of the channel supply layer. A first pad is on the buffer layer and extends through the first hole of the stack to the first electrode. A second pad is on the buffer layer and extends through the second hole of the stack to the second electrode. A third pad is under the stack and electrically connected to the third electrode. | 09-12-2013 |
20130307026 | HIGH ELECTRON MOBILITY TRANSISTORS AND METHODS OF MANUFACTURING THE SAME - According to example embodiments, High electron mobility transistors (HEMTs) may include a discontinuation region in a channel region. The discontinuation region may include a plurality of 2DEG unit regions that are spaced apart from one another. The discontinuation region may be formed at an interface between two semiconductor layers or adjacent to the interface. The discontinuation region may be formed by an uneven structure or a plurality of recess regions or a plurality of ion implantation regions. The plurality of 2DEG unit regions may have a nanoscale structure. The plurality of 2DEG unit regions may be formed in a dot pattern, a stripe pattern, or a staggered pattern. | 11-21-2013 |
20140021511 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A high electron mobility transistor (HEMT) according to example embodiments includes a channel layer, a channel supply layer on the channel layer, a source electrode and a drain electrode on at least one of the channel layer and the channel supply layer, a gate electrode between the source electrode and the drain electrode, and a Schottky electrode forming a Schottky contact with the channel supply layer. An upper surface of the channel supply layer may define a Schottky electrode accommodation unit. At least part of the Schottky electrode may be in the Schottky electrode accommodation unit. The Schottky electrode is electrically connected to the source electrode. | 01-23-2014 |
20140027779 | HIGH ELECTRON MOBILITY TRANSISTOR - According to example embodiments, a high electron mobility transistor includes: a channel layer including a 2-dimensional electron gas (2DEG); a contact layer on the channel layer; a channel supply layer on the contact layer; a gate electrode on a portion of the channel layer; and source and drain electrodes on at least one of the channel layer, the contact layer, and the channel supply layer. The contact layer is configured to form an ohmic contact on the channel layer. The contact layer is n-type doped and contains a Group III-V compound semiconductor. The source electrode and the drain electrode are spaced apart from opposite sides of the gate electrode. | 01-30-2014 |
20140042449 | HIGH ELECTRON MOBILITY TRANSISTOR - According to example embodiments, a high electron mobility transistor (HEMT) includes a channel supply layer that induces a two-dimensional electron gas (2DEG) in a channel layer, a source electrode and a drain electrode that are at sides of the channel supply layer, a depletion-forming layer that is on the channel supply layer and contacts the source electrode, a gate insulating layer on the depletion-forming layer, and a gate electrode on the gate insulating layer. The depletion-forming layer forms a depletion region in the 2DEG. | 02-13-2014 |
20140097470 | HIGH-ELECTRON MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - According to example embodiments, a HEMT includes a channel supply layer on a channel layer, a p-type semiconductor structure on the channel supply layer, a gate electrode on the p-type semiconductor structure, and source and drain electrodes spaced apart from two sides of the gate electrode respectively. The channel supply layer may have a higher energy bandgap than the channel layer. The p-type semiconductor structure may have an energy bandgap that is different than the channel supply layer. The p-type semiconductor structure may include a hole injection layer (HIL) on the channel supply layer and be configured to inject holes into at least one of the channel layer and the channel supply in an on state. The p-type semiconductor structure may include a depletion forming layer on part of the HIL. The depletion forming layer may have a dopant concentration that is different than the dopant concentration of the HIL. | 04-10-2014 |
20140103969 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF DRIVING THE SAME - According to example embodiments, a HEMT includes a channel layer, a channel supply layer on the channel layer, a source electrode and a drain electrode spaced apart on the channel layer, a depletion-forming layer on the channel supply layer, and a plurality of gate electrodes on the depletion-forming layer between the source electrode and the drain electrode. The channel supply layer is configured to induce a two-dimensional electron gas (2DEG) in the channel layer. The depletion-forming layer is configured to form a depletion region in the 2DEG. The plurality of gate electrodes include a first gate electrode and a second gate electrode spaced apart from each other. | 04-17-2014 |
20140147973 | METHOD OF PACKAGING POWER DEVICES AT WAFER LEVEL - A method of packaging power devices at a wafer level is disclosed. The method includes preparing a wafer having a plurality of nitride power devices thereon, each of the plurality of nitride power devices having a plurality of electrodes thereon; forming a polymer layer on the plurality of nitride power devices; exposing each of the electrodes from the polymer layer; forming a solder bump on the exposed electrodes; forming a molding layer covering the solder bump on the polymer layer; and removing the wafer and exposing the solder bump. | 05-29-2014 |
20140266400 | METHOD OF REDUCING CURRENT COLLAPSE OF POWER DEVICE - According to example embodiments, a method of operating a power device includes applying a control voltage to a control electrode of the power device, where the control electrode is electrically separated from a source electrode, a drain electrode, and a gate electrode of the power device. The control voltage is separately applied to the control electrode. The method may include applying a negative control voltage to the control electrode prior to applying a gate voltage to the gate electrode. | 09-18-2014 |