Patent application number | Description | Published |
20080299716 | DISTRIBUTED HIGH VOLTAGE JFET - A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET. | 12-04-2008 |
20090096033 | ISOLATION TRENCH WITH ROUNDED CORNERS FOR BiCMOS PROCESS - A semiconductor device comprising a first transistor device on or in a semiconductor substrate and a second transistor device on or in the substrate. The device further comprises an insulating trench located between the first transistor device and the second transistor device. At least one upper corner of the insulating trench is a rounded corner in a lateral plane of the substrate. | 04-16-2009 |
20090159968 | BVDII Enhancement with a Cascode DMOS - Double diffused MOS (DMOS) transistors feature extended drain regions to provide depletion regions which drop high drain voltages to lower voltages at the gate edges. DMOS transistors exhibit lower drain breakdown potential in the on-state than in the off-state than in the off-state due to snapback by a parasitic bipolar transistor that exists in parallel with the DMOS transistor. The instant invention is a cascoded DMOS transistor in an integrated circuit incorporating an NMOS transistor on the DMOS source node to reverse bias the parasitic emitter-base junction during on-state operation, eliminating snapback. The NMOS transistor may be integrated with the DMOS transistor by connections in the interconnect system of the integrated circuit, or the NMOS transistor and DMOS transistor may be fabricated in a common p-type well and integrated in the IC substrate. Methods of fabricating an integrated circuit with the incentive cascoded DMOS transistor are also disclosed. | 06-25-2009 |
20100264486 | FIELD PLATE TRENCH MOSFET TRANSISTOR WITH GRADED DIELECTRIC LINER THICKNESS - An electronic device has a plurality of trenches formed in a semiconducting layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric is located between the field plate section and the vertical drift region. | 10-21-2010 |
20110073955 | ISOLATION TRENCH WITH ROUNDED CORNERS FOR BiCMOS PROCESS - A semiconductor device comprising a first transistor device ( | 03-31-2011 |
20110275210 | METHOD OF MAKING VERTICAL TRANSISTOR WITH GRADED FIELD PLATE DIELECTRIC - An electronic device has a plurality of trenches formed in a semiconductor layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric having increased thickness at greater depth is located between the field plate section and the vertical drift region. | 11-10-2011 |
20120098062 | HYBRID ACTIVE-FIELD GAP EXTENDED DRAIN MOS TRANSISTOR - An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions. | 04-26-2012 |
20130032863 | INTEGRATED GATE CONTROLLED HIGH VOLTAGE DIVIDER - An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider. | 02-07-2013 |
20130032922 | INTEGRATED HIGH VOLTAGE DIVIDER - An integrated circuit containing a voltage divider having an upper resistor of unsilicided gate material over field oxide around a central opening and a drift layer under the upper resistor, an input terminal coupled to an input node of the upper resistor adjacent to the central opening in the field oxide and coupled to the drift layer through the central opening, a sense terminal coupled to a sense node on the upper resistor opposite from the input node, a lower resistor with a sense node coupled to the sense terminal and a reference node, and a reference terminal coupled to the reference node. A process of forming the integrated circuit containing the voltage divider. | 02-07-2013 |
20140256108 | HYBRID ACTIVE-FIELD GAP EXTENDED DRAIN MOS TRANSISTOR - An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions. | 09-11-2014 |
20150041907 | IC WITH FLOATING BURIED LAYER RING FOR ISOLATION OF EMBEDDED ISLANDS - An integrated circuit (IC) includes a substrate having a p-type semiconductor surface. A first nwell includes an area surrounding a first plurality of semiconductor devices formed in the semiconductor surface having a first n-buried layer (NBL) thereunder. A vertical diode formed in the semiconductor surface surrounds the first nwell including a pwell on top of a floating NBL ring. A second nwell formed in the semiconductor surface includes an area surrounding the floating NBL ring and surrounds a second plurality of semiconductor devices having a second NBL thereunder. | 02-12-2015 |