Patent application number | Description | Published |
20080299716 | DISTRIBUTED HIGH VOLTAGE JFET - A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET. | 12-04-2008 |
20090096033 | ISOLATION TRENCH WITH ROUNDED CORNERS FOR BiCMOS PROCESS - A semiconductor device comprising a first transistor device on or in a semiconductor substrate and a second transistor device on or in the substrate. The device further comprises an insulating trench located between the first transistor device and the second transistor device. At least one upper corner of the insulating trench is a rounded corner in a lateral plane of the substrate. | 04-16-2009 |
20090159968 | BVDII Enhancement with a Cascode DMOS - Double diffused MOS (DMOS) transistors feature extended drain regions to provide depletion regions which drop high drain voltages to lower voltages at the gate edges. DMOS transistors exhibit lower drain breakdown potential in the on-state than in the off-state than in the off-state due to snapback by a parasitic bipolar transistor that exists in parallel with the DMOS transistor. The instant invention is a cascoded DMOS transistor in an integrated circuit incorporating an NMOS transistor on the DMOS source node to reverse bias the parasitic emitter-base junction during on-state operation, eliminating snapback. The NMOS transistor may be integrated with the DMOS transistor by connections in the interconnect system of the integrated circuit, or the NMOS transistor and DMOS transistor may be fabricated in a common p-type well and integrated in the IC substrate. Methods of fabricating an integrated circuit with the incentive cascoded DMOS transistor are also disclosed. | 06-25-2009 |
20100264486 | FIELD PLATE TRENCH MOSFET TRANSISTOR WITH GRADED DIELECTRIC LINER THICKNESS - An electronic device has a plurality of trenches formed in a semiconducting layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric is located between the field plate section and the vertical drift region. | 10-21-2010 |
20110073955 | ISOLATION TRENCH WITH ROUNDED CORNERS FOR BiCMOS PROCESS - A semiconductor device comprising a first transistor device ( | 03-31-2011 |
20110275210 | METHOD OF MAKING VERTICAL TRANSISTOR WITH GRADED FIELD PLATE DIELECTRIC - An electronic device has a plurality of trenches formed in a semiconductor layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric having increased thickness at greater depth is located between the field plate section and the vertical drift region. | 11-10-2011 |
20120098062 | HYBRID ACTIVE-FIELD GAP EXTENDED DRAIN MOS TRANSISTOR - An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions. | 04-26-2012 |
20130032863 | INTEGRATED GATE CONTROLLED HIGH VOLTAGE DIVIDER - An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider. | 02-07-2013 |
20130032922 | INTEGRATED HIGH VOLTAGE DIVIDER - An integrated circuit containing a voltage divider having an upper resistor of unsilicided gate material over field oxide around a central opening and a drift layer under the upper resistor, an input terminal coupled to an input node of the upper resistor adjacent to the central opening in the field oxide and coupled to the drift layer through the central opening, a sense terminal coupled to a sense node on the upper resistor opposite from the input node, a lower resistor with a sense node coupled to the sense terminal and a reference node, and a reference terminal coupled to the reference node. A process of forming the integrated circuit containing the voltage divider. | 02-07-2013 |
20140256108 | HYBRID ACTIVE-FIELD GAP EXTENDED DRAIN MOS TRANSISTOR - An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions. | 09-11-2014 |
20150041907 | IC WITH FLOATING BURIED LAYER RING FOR ISOLATION OF EMBEDDED ISLANDS - An integrated circuit (IC) includes a substrate having a p-type semiconductor surface. A first nwell includes an area surrounding a first plurality of semiconductor devices formed in the semiconductor surface having a first n-buried layer (NBL) thereunder. A vertical diode formed in the semiconductor surface surrounds the first nwell including a pwell on top of a floating NBL ring. A second nwell formed in the semiconductor surface includes an area surrounding the floating NBL ring and surrounds a second plurality of semiconductor devices having a second NBL thereunder. | 02-12-2015 |
Patent application number | Description | Published |
20080273508 | PACKETIZED AUDIO DATA OPERATIONS IN A WIRELESS LOCAL AREA NETWORK DEVICE - A wireless local area network (WLAN) transceiving integrated circuit includes a WLAN interface, an input buffer, an input buffer controller, and a processor. The WLAN transceiving integrated circuit may also include an output buffer, an output buffer controller, a transcoder, and/or an audio Coder-Decoder (CODEC). The WLAN transceiving integrated circuit is installed in a WLAN device that services voice communications. The input buffer receives packetized audio data from the WLAN interface. When the input buffer satisfies a buffer vacancy threshold, the processor and the input buffer controller cooperatively operate to fill at least a portion of the input buffer with packetized audio data. The processor copies packetized audio data from the input buffer and fills the input buffer with the copied packetized audio data to maintain an audio pattern in the input buffer. The input buffer controller fills the input buffer when the processor is available and after copying/filling is no longer effective. The processor operates to maintain the audio pattern when additional packetized audio data is received by the WLAN interface. These operations are also performed for the output buffer, which receives packetized audio data from the transcoder and writes the packetized audio data to the WLAN interface. | 11-06-2008 |
20090325490 | Baseband Controller in a Micronetwork - A baseband controller includes a microsequencer with special hardware resources circuitry and a configuration that supports real-time micronetwork functionality for an upper limit of slave devices. The microsequencer includes a correlator that may also be used as an accumulator, wherein the topology provides that the correlator can communicate with an arithmetic logic unit that correspondingly enables the correlator to act as an accumulator. The microsequencer also includes a plurality of clocks and timers for facilitating micronetwork timing functionality, and at registers for temporarily storing computational data, where each of the storage registers have different sizes for accommodating different-sized packets of computational data. | 12-31-2009 |
20100135271 | PACKETIZED AUDIO DATA OPERATIONS IN A WIRELESS LOCAL AREA NETWORK DEVICE - A wireless local area network (WLAN) transceiving integrated circuit includes a WLAN interface, an input buffer, an input buffer controller, and a processor. The WLAN transceiving integrated circuit may also include an output buffer, an output buffer controller, a transcoder, and/or an audio Coder-Decoder (CODEC). The WLAN transceiving integrated circuit is installed in a WLAN device that services voice communications. The input buffer receives packetized audio data from the WLAN interface. When the input buffer satisfies a buffer vacancy threshold, the processor and the input buffer controller cooperatively operate to fill at least a portion of the input buffer with packetized audio data. The processor copies packetized audio data from the input buffer and fills the input buffer with the copied packetized audio data to maintain an audio pattern in the input buffer. The input buffer controller fills the input buffer when the processor is available and after copying/filling is no longer effective. The processor operates to maintain the audio pattern when additional packetized audio data is received by the WLAN interface. These operations are also performed for the output buffer, which receives packetized audio data from the transcoder and writes the packetized audio data to the WLAN interface. | 06-03-2010 |
20110228754 | PACKETIZED AUDIO DATA OPERATIONS IN A WIRELESS LOCAL AREA NETWORK DEVICE - A wireless local area network (WLAN) transceiving integrated circuit includes a WLAN interface, an input buffer, an input buffer controller, and a processor. The WLAN transceiving integrated circuit may also include an output buffer, an output buffer controller, a transcoder, and/or an audio Coder-Decoder (CODEC). The WLAN transceiving integrated circuit is installed in a WLAN device that services voice communications. The input buffer receives packetized audio data from the WLAN interface. When the input buffer satisfies a buffer vacancy threshold, the processor and the input buffer controller cooperatively operate to fill at least a portion of the input buffer with packetized audio data. The processor copies packetized audio data from the input buffer and fills the input buffer with the copied packetized audio data to maintain an audio pattern in the input buffer. The input buffer controller fills the input buffer when the processor is available and after copying/filling is no longer effective. The processor operates to maintain the audio pattern when additional packetized audio data is received by the WLAN interface. These operations are also performed for the output buffer, which receives packetized audio data from the transcoder and writes the packetized audio data to the WLAN interface. | 09-22-2011 |
Patent application number | Description | Published |
20120023448 | Relational Service System and Method for Generating an Input Method - A relational service system for generating an input method is disclosed; the system uses an input unit to provide phonetic symbol and symbol input for a user, transmits an input string by the user to a temporary storing unit for display and selection, and then transmits the selected input string back to the input unit. When the input string is in the temporary storing unit, a analysis unit breaks the input string to obtain one or more words and analyzes the word to find a keyword, then a decision unit uses the keyword to search in a database to determine if there's an associated word or phrase related to the word, if so, then a prompting unit is enabled to use a relational information display unit to display related information in a tree structure, and finally a service unit uses an associated word or phrase selected by the user to initiate a remote service, such as ordering food, restaurant reservation, or booking movie tickets. | 01-26-2012 |
20120089907 | Single Word and Multi-word Term Integrating System and a Method thereof - A single word and multi-word term integrating system and a method thereof are disclosed, wherein a user uses an input unit to continuously input pinying codes for the system to find combinations of the pinying codes to provide word candidates for the user to choose, wherein the word candidates can be combined into a phrase or a sentence; when the inputted pinying codes are too long or incomplete, there might be a false prediction of a word or a sentence due to an incorrect combination of pinying codes; consequently, the system forcibly determines the pinying codes to be regarded as a single word and does not combine them with the follow-up pinying codes; then the system uses a full sentence prediction result display unit for the user to choose a correct word, thereby improving prediction accuracy. | 04-12-2012 |