Patent application number | Description | Published |
20080224186 | High Dynamic Range Imaging Cell With Electronic Shutter Extensions - A pixel sensor cell of improved dynamic range comprises a coupling transistor that couples a capacitor device to a photosensing region (e.g., photodiode) of the pixel cell, the photodiode being coupled to a transfer gate and one terminal of the coupling transistor. In operation, the additional capacitance is coupled to the pixel cell photodiode when the voltage on the photodiode is drawn down to the substrate potential. Thus, the added capacitance is only connected to the imager cell when the cell is nearing its charge capacity. Otherwise, the cell has a low capacitance and low leakage. In an additional embodiment, a terminal of the capacitor is coupled to a “pulsed” supply voltage signal that enables substantially full depletion of stored charge from the capacitor to the photosensing region during a read out operation of the pixel sensor cell. In various embodiments, the locations of the added capacitance and photodiode may be interchanged with respect to the coupling transistor. In addition, the added capacitor of the pixel sensor cell allows for a global shutter operation. | 09-18-2008 |
20080272399 | PIXEL SENSOR CELL FOR COLLECTING ELECTRONS AND HOLES - The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input. | 11-06-2008 |
20080272400 | PIXEL SENSOR CELL FOR COLLECTING ELECTRONS AND HOLES - The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input. | 11-06-2008 |
20080274578 | METHOD OF FORMING A PIXEL SENSOR CELL FOR COLLECTING ELECTRONS AND HOLES - The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input. | 11-06-2008 |
20080284021 | Method for FEOL and BEOL Wiring - A method for forming a conductive structure of sub-lithographic dimension suitable for FEOL and BEOL semiconductor fabrication applications. The method includes forming a topographic feature of silicon-containing material on a substrate; forming a dielectric cap on the topographic feature; applying a mask structure to expose a pattern on a sidewall of the topographic feature, the exposed pattern corresponding to a conductive structure to be formed; depositing a metal at the exposed portions of the sidewall and forming one or more metal silicide conductive structures at the exposed sidewall portions; removing the dielectric cap layer; and removing the silicon-containing topographic feature. The result is the formation of one or more metal silicide conductor structures formed for a single lithographically defined feature. In example embodiments, the formed metal silicide conductive structures have a high aspect ratio, e.g., ranging from 1:1 to 20:1 (height to width dimension). | 11-20-2008 |
20080296476 | PIXEL SENSOR CELL FOR COLLECTING ELECTIONS AND HOLES - The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input. | 12-04-2008 |
20090001427 | CHARGE CARRIER BARRIER FOR IMAGE SENSOR - A pixel sensor structure, method of manufacture and method of operating. Disclosed is a buffer pixel cell comprising a barrier region for preventing stray charge carriers from arriving at a dark current correction pixel cell. The buffer pixel cell is located in the vicinity of the dark current correction pixel cell and the buffer pixel cell resembles an active pixel cell. Thus, an environment surrounding the dark current correction pixel cell is similar to the environment surrounding an active pixel cell. | 01-01-2009 |
20090020819 | FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE - Disclosed herein are embodiments of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via. | 01-22-2009 |
20090065818 | STRUCTURE FOR IMAGERS HAVING ELECTRICALLY ACTIVE OPTICAL ELEMENTS - A design structure embodied in a machine readable medium for use in a design process, the design structure representing a CMOS image sensor device comprising an array of active pixel cells. Each active pixel cell includes a substrate; a photosensing device formed at or below a substrate surface for collecting charge carriers in response to incident light; and, one or more light transmissive conductive wire structures formed above the photosensing device, the one or more conductive wire structures being located in an optical path above the photosensing device. The formed light transmissive conductive wire structures provide both an electrical and optical functions. An optical function is provided by tailoring the thickness of the conductive wire layer to filter light according to a pixel color scheme. Alternately, the light transmissive conductive wire structures may be formed as a microlens structure providing a light focusing function. Electrical functions for the conductive wire layer include use as a capacitor plate, as a resistor or as an interconnect. | 03-12-2009 |
20090065834 | IMAGERS HAVING ELECTRICALLY ACTIVE OPTICAL ELEMENTS - A CMOS image sensor comprising an array of active pixel cells. Each active pixel cell includes a substrate; a photosensing device formed at or below a substrate surface for collecting charge carriers in response to incident light; and, one or more light transmissive conductive wire structures formed above the photosensing device, the one or more conductive wire structures being located in an optical path above the photosensing device. The formed light transmissive conductive wire structures provide both an electrical and optical functions. An optical function is provided by tailoring the thickness of the conductive wire layer to filter light according to a pixel color scheme. Alternately, the light transmissive conductive wire structures may be formed as a microlens structure providing a light focusing function. Electrical functions for the conductive wire layer include use as a capacitor plate, as a resistor or as an interconnect. | 03-12-2009 |
20090101978 | FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE - Disclosed herein are embodiments of a design structure of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via. | 04-23-2009 |
20090141155 | HIGH DYNAMIC RANGE IMAGING CELL WITH ELECTRONIC SHUTTER EXTENSIONS - A pixel sensor cell of improved dynamic range and a design structure including the pixel sensor cell embodied in a machine readable medium are provided. The pixel cell comprises a coupling transistor that couples a capacitor device to a photosensing region (e.g., photodiode) of the pixel cell, the photodiode being coupled to a transfer gate and one terminal of the coupling transistor. In operation, the additional capacitance is coupled to the pixel cell photodiode when the voltage on the photodiode is drawn down to the substrate potential. Thus, the added capacitance is only connected to the imager cell when the cell is nearing its charge capacity. Otherwise, the cell has a low capacitance and low leakage. In an additional embodiment, a terminal of the capacitor is coupled to a “pulsed” supply voltage signal that enables substantially full depletion of stored charge from the capacitor to the photosensing region during a read out operation of the pixel sensor cell. In various embodiments, the locations of the added capacitance and photodiode may be interchanged with respect to the coupling transistor. In addition, the added capacitor of the pixel sensor cell allows for a global shutter operation. | 06-04-2009 |
20090236644 | HIGH EFFICIENCY CMOS IMAGE SENSOR PIXEL EMPLOYING DYNAMIC VOLTAGE SUPPLY - A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The drain voltage of the reset gate transistor is held at a lower voltage than a circuit supply voltage to minimize the off-state leakage through the RG transistor, thus reducing the change in the voltage at the floating diffusion during the signal hold time. In addition, a design structure for such a circuit providing a dynamic voltage to the drain of a reset gate of a pixel circuit is also provided. | 09-24-2009 |
20090237103 | IMAGE SENSOR MONITOR STRUCTURE IN SCRIBE AREA - A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS image sensors employed in another array in the semiconductor chip and having a larger array size. Such a test structure is provided in a design phase by providing a design structure in which the orientations of the CMOS image sensors match between the two arrays. The test structure provides effective and accurate monitoring of manufacturing processes through in-line testing before a final test on the semiconductor chip. | 09-24-2009 |
20090268063 | Methods for Enhancing Quality of Pixel Sensor Image Frames for Global Shutter Imaging - The image quality of an image frame from a CMOS image sensor array operated in global shutter mode may be enhanced by dispersing or randomizing the noise introduced by leakage currents from floating drains among the rows of the image frame. Further, the image quality may be improved by accounting for time dependent changes in the output of dark pixels in dark pixel rows or dark pixel columns. In addition, voltage and time dependent changes in the output of dark pixels may also be measured to provide an accurate estimate of the noise introduced to the charge held in the floating drains. Such methods may be employed individually or in combination to improve the quality of the image. | 10-29-2009 |
20090286346 | Methods For Forming Anti-Reflection Structures For CMOS Image Sensors - Protuberances, having vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode, are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sublithographic features of a first polymeric block component within a matrix of a second polymeric block component. The pattern of the polymeric block component is transferred into a first optical layer to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection. | 11-19-2009 |
20090298220 | IMAGERS HAVING ELECTRICALLY ACTIVE OPTICAL ELEMENTS - A method of fabricating a CMOS image sensor comprising an array of active pixel cells. Each active pixel cell includes a substrate; a photosensing device formed at or below a substrate surface for collecting charge carriers in response to incident light; and, one or more light transmissive conductive wire structures formed above the photosensing device, the one or more conductive wire structures being located in an optical path above the photosensing device. The formed light transmissive conductive wire structures provide both an electrical and optical function. An optical function is provided by tailoring the thickness of the conductive wire layer to filter light according to a pixel color scheme. Alternately, the light transmissive conductive wire structures may be formed as a microlens structure providing a light focusing function. Electrical functions for the conductive wire layer include use as a capacitor plate, as a resistor or as an interconnect. | 12-03-2009 |
20100013972 | PIXEL SENSOR CELL WITH FRAME STORAGE CAPABILITY - A set of frame transfer transistors are provided between a hold gate transistor and a transfer gate transistor of a CMOS image sensor to enable storage of charge generate in the photosensitive diode after exposure. The readout of the charges from the set of frame transfer transistors may be performed after a plurality of exposures of the CMOS image sensor, between each of which charges are shifted toward the transfer gate transistor within the set of frame transfer transistors. Useful operation modes are enabled including a burst mode operation for rapid capture of successive images and high dynamic range operations in which multiple images are taken with different exposure times or a large capacitance is provided by ganging the diffusions of the set of frame transfer transistors. | 01-21-2010 |
20100013973 | PIXEL SENSOR CELL WITH FRAME STORAGE CAPABILITY - A set of frame transfer transistors are provided between a hold gate transistor and a transfer gate transistor of a CMOS image sensor to enable storage of charge generate in the photosensitive diode after exposure. The readout of the charges from the set of frame transfer transistors may be performed after a plurality of exposures of the CMOS image sensor, between each of which charges are shifted toward the transfer gate transistor within the set of frame transfer transistors. Useful operation modes are enabled including a burst mode operation for rapid capture of successive images and high dynamic range operations in which multiple images are taken with different exposure times or a large capacitance is provided by ganging the diffusions of the set of frame transfer transistors. | 01-21-2010 |
20100084690 | CMOS IMAGER PHOTODIODE WITH ENHANCED CAPACITANCE - A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface. In a further embodiment, an additional photosensitive element is provided that includes a laterally disposed charge collection region that contacts the non-laterally disposed charge collection region of the photosensitive element and underlies the doped layer formed at the substrate surface. | 04-08-2010 |
20100097511 | HIGH EFFICIENCY CMOS IMAGE SENSOR PIXEL EMPLOYING DYNAMIC VOLTAGE SUPPLY - A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The drain voltage of the reset gate transistor is held at a lower voltage than a circuit supply voltage to minimize the off-state leakage through the RG transistor, thus reducing the change in the voltage at the floating diffusion during the signal hold time. In addition, a design structure for such a circuit providing a dynamic voltage to the drain of a reset gate of a pixel circuit is also provided. | 04-22-2010 |
20100136733 | SILICIDE STRAPPING IN IMAGER TRANSFER GATE DEVICE - A CMOS active pixel sensor (APS) cell structure having dual workfunction transfer gate device and method of fabrication. The transfer gate device comprises a dielectric layer formed on a substrate and a dual workfunction gate conductor layer formed on the dielectric layer comprising a first conductivity type doped region and an abutting second conductivity type doped region. The transfer gate device defines a channel region where charge accumulated by a photosensing device is transferred to a diffusion region. A silicide structure is formed atop the dual workfunction gate conductor layer for electrically coupling the first and second conductivity type doped regions. In one embodiment, the silicide contact is smaller in area dimension than an area dimension of said dual workfunction gate conductor layer. Presence of the silicide strap prevents the diodic behavior from allowing one or the other side of the gate to float to an indeterminate voltage. | 06-03-2010 |
20100187614 | SELECTIVE NITRIDATION OF GATE OXIDES - A method of fabricating a semiconductor structure. The method includes forming a first feature of a first active device and a second feature of a second active device, introducing a first amount of nitrogen into the first feature of the first active device, and introducing a second amount of nitrogen into the second feature of the second active device, the second amount of nitrogen being different from the first amount of nitrogen. | 07-29-2010 |
20100245644 | VARIABLE DYNAMIC RANGE PIXEL SENSOR CELL, DESIGN STRUCTURE AND METHOD - A pixel sensor cell including a column circuit, a design structure for fabricating the pixel sensor cell including the column circuit and a method for operating the pixel sensor cell including the column circuit are predicated upon the measurement of multiple reference data point and signal data point pairs from a floating diffusion at a variable capacitance. The variable capacitance is provided by excluding or including a transfer gate transistor capacitance in addition to a floating diffusion capacitance. Such a variable capacitance provides variable dynamic ranges for the pixel sensor cell including the column circuit. | 09-30-2010 |
20100261351 | Spacer Linewidth Control - A method for forming a plurality of variable linewidth spacers adjoining a plurality of uniformly spaced topographic features uses a conformal resist layer upon a spacer material layer located over the plurality of uniformly spaced topographic features. The conformal resist layer is differentially exposed and developed to provide a differential thickness resist layer that is used as a sacrificial mask when forming the variable linewidth spacers. A method for forming uniform linewidth spacers adjoining narrowly spaced topographic features and widely spaced topographic features over the same substrate uses a masked isotropic etching of a variable thickness spacer material layer to provide a more uniform partially etched spacer material layer, followed by an unmasked anisotropic etching of the partially etched spacer material layer. A related method for forming the uniform linewidth spacers uses a two-step anisotropic etch method that includes at least one masking process step. | 10-14-2010 |
20100264473 | ANTI-REFLECTION STRUCTURES FOR CMOS IMAGE SENSORS - Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package. | 10-21-2010 |
20110049330 | IMAGE SENSOR, METHOD AND DESIGN STRUCTURE INCLUDING NON-PLANAR REFLECTOR - A solid state image sensor, a method for fabricating the solid state image sensor and a design structure for fabricating the solid state image sensor structure include a substrate that in turn includes a photosensitive region. Also included within solid state image sensor is a non-planar reflector layer located over a side of the photosensitive region and the substrate opposite an incoming radiation side of the photosensitive region and the substrate. The non-planar reflector layer is shaped and positioned to reflect uncaptured incident radiation back into the photosensitive region while avoiding optical cross-talk with an additional photosensitive region laterally separated within the substrate. | 03-03-2011 |
20110057282 | PIXEL SENSORS OF MULTIPLE PIXEL SIZE AND METHODS OF IMPLANT DOSE CONTROL - CMOS pixel sensors with multiple pixel sizes and methods of manufacturing the CMOS pixel sensors with implant dose control are provided. The method includes forming a plurality of pixel sensors in a same substrate and forming a masking pattern over at least one of the plurality of pixel sensors that has a pixel size larger than a non-masked pixel sensor of the plurality of pixel sensors. The method further includes providing a single dosage implant to the plurality of pixel sensors. The at least one of the plurality of pixel sensors with the masking pattern receives a lower dosage than the non-masked pixel sensor. | 03-10-2011 |
20110079827 | STRUCTURE AND METHOD TO CREATE A DAMASCENE LOCAL INTERCONNECT DURING METAL GATE DEPOSITION - A method and structure to create damascene local interconnect during metal gate deposition. A method includes: forming a gate dielectric on an upper surface of a substrate; forming a mandrel on the gate dielectric; forming an interlevel dielectric (ILD) layer on a same level as the mandrel; forming a trench in the ILD layer; removing the mandrel; and forming a metal layer on the gate dielectric and in the trench. | 04-07-2011 |
20110098838 | SYSTEM AND METHOD FOR CORRECTING SYSTEMATIC PARAMETRIC VARIATIONS ON INTEGRATED CIRCUIT CHIPS IN ORDER TO MINIMIZE CIRCUIT LIMITED YIELD LOSS - Disclosed are a system and a method of correcting systematic, design-based, parametric variations on integrated circuit chips to minimize circuit limited yield loss. Processing information and a map of a chip are stored. The processing information can indicate an impact, on a given device parameter, of changes in a value for a specification associated with a given process step. The map can indicate regional variations in the device parameter (e.g., threshold voltage). Based on the processing information and using the map as a guide, different values for the specification are determined, each to be applied in a different region of the integrated circuit chip during the process step in order to offset the mapped regional parametric variations. A process tool can then be selectively controlled to ensure that during chip manufacturing the process step is performed accordingly and, thereby to ensure that the regional parametric variations are minimized. | 04-28-2011 |
20110127529 | SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE - Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure. | 06-02-2011 |
20110131542 | SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS, DESIGN STRUCTURE AND METHOD - Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure. | 06-02-2011 |
20110134504 | Micro-Electro-Mechanical System Tiltable Lens - A tiltable micro-electro-mechanical (MEMS) system lens comprises a microscopic lens located on a front surface of a semiconductor-on-insulator (SOI) substrate and a semiconductor rim surrounding the periphery of the microscopic lens. Two horizontal semiconductor beams located at different heights are provided within a top semiconductor layer. The microscopic lens may be tilted by applying an electrical bias between the lens rim and one of the two semiconductor beams, thereby altering the path of an optical beam through the microscopic lens. An array of tiltable microscopic lenses may be employed to form a composite lens having a variable focal length may be formed. A design structure for such a tiltable MEMS lens is also provided. | 06-09-2011 |
20110193146 | Charge Carrier Barrier for Image Sensor - A pixel sensor structure, method of manufacture and method of operating. Disclosed is a buffer pixel cell comprising a barrier region for preventing stray charge carriers from arriving at a dark current correction pixel cell. The buffer pixel cell is located in the vicinity of the dark current correction pixel cell and the buffer pixel cell resembles an active pixel cell. Thus, an environment surrounding the dark current correction pixel cell is similar to the environment surrounding an active pixel cell. | 08-11-2011 |
20110208482 | Variable Focus Point Lens - A variable focal point lens includes a transparent tank, which comprises a transparent enclosure containing a transparent flexible membrane separating the inner volume of the transparent tank into an upper tank portion and a lower tank portion. The upper tank portion and the lower tank portion contain liquids having different indices of refraction. The transparent flexible membrane is electrostatically displaced to change the thicknesses of the first tank portion and the second tank portion in the path of the light, thereby shifting the focal point of the lens axially and/or laterally. The electrostatic displacement of the membrane may be effected by a fixed charge in the membrane and an array of enclosure-side conductive structures on the transparent enclosure, or an array of membrane-side conductive structures on the transparent membrane and an array of enclosure-side conductive structures. | 08-25-2011 |
20110250715 | METHODS FOR FORMING ANTI-REFLECTION STRUCTURES FOR CMOS IMAGE SENSORS - Protuberances, having vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode, are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sublithographic features of a first polymeric block component within a matrix of a second polymeric block component. The pattern of the polymeric block component is transferred into a first optical layer to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection. | 10-13-2011 |
20110278649 | NON-UNIFORM GATE DIELECTRIC CHARGE FOR PIXEL SENSOR CELLS AND METHODS OF MANUFACTURING - A non-uniform gate dielectric charge for pixel sensor cells, e.g., CMOS optical imagers, and methods of manufacturing are provided. The method includes forming a gate dielectric on a substrate. The substrate includes a source/drain region and a photo cell collector region. The method further includes forming a non-uniform fixed charge distribution in the gate dielectric. The method further includes forming a gate structure on the gate dielectric. | 11-17-2011 |
20110281409 | Semiconductor Structures Using Replacement Gate and Methods of Manufacture - An improved semiconductor device manufactured using, for example, replacement gate technologies. The method includes forming a dummy gate structure having a gate stack and spacers. The method further includes forming a dielectric material adjacent to the dummy gate structure. The method further includes removing the spacers to form gaps, and implanting a halo extension through the gaps and into an underlying diffusion region. | 11-17-2011 |
20120037967 | CMOS PIXEL SENSOR CELLS WITH POLY SPACER TRANSFER GATES AND METHODS OF MANUFACTURE - CMOS pixel sensor cells with spacer transfer gates and methods of manufacture are provided herein. The method includes forming a middle gate structure on a gate dielectric. The method further includes forming insulation sidewalls on the middle gate structure. The method further includes forming spacer transfer gates on the gate dielectric on opposing sides of the middle gate, adjacent to the insulation sidewalls which isolate the middle gate structure from the spacer transfer gates. The method further includes forming a photo-diode region in electrical contact with one of the spacer transfer gates and a floating diffusion in electrical contact with another of the spacer transfer gates. | 02-16-2012 |
20120038811 | METHODS FOR ENHANCING QUALITY OF PIXEL SENSOR IMAGE FRAMES FOR GLOBAL SHUTTER IMAGING - The image qualify of an image frame from a CMOS image sensor array operated in global shutter mode may be enhanced by dispersing or randomizing the noise introduced by leakage currents from floating drains among the rows of the image frame. Further, the image quality may be improved by accounting for time dependent changes in the output of dark pixels in dark pixel rows or dark pixel columns. In addition, voltage and time dependent changes in the output of dark pixels may also be measured to provide an accurate estimate of the noise introduced to the charge held in the floating drains. Such methods may be employed individually or in combination to improve the quality of the image. | 02-16-2012 |
20120074501 | USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES - Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET. | 03-29-2012 |
20120074502 | USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES - Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). One embodiment of this invention includes creating this differential stress by varying the deposition conditions for forming PFET and NFET contacts, for example, the temperature at which the fill materials are deposited, and the rate at which the fill materials are deposited. In another embodiment, the differential stress is created by filling the contacts with differing materials that will impart differential stress due to differing coefficient of thermal expansions. In another embodiment, the differential stress is created by including a silicide layer within the NFET contacts and/or the PFET contacts. | 03-29-2012 |
20120081588 | PIXEL SENSOR CELL WITH HOLD NODE FOR LEAKAGE CANCELLATION AND METHODS OF MANUFACTURE AND DESIGN STRUCTURE - A reference pixel sensor cell (e.g., global shutter) with hold node for leakage cancellation, methods of manufacture and design structure is provided. A pixel array includes one or more reference pixel sensor cells dispersed locally throughout active light sensing regions. The one or more reference pixel sensor cells provides a reference signal used to correct for photon generated leakage signals which vary by locality within the active light sensing regions. | 04-05-2012 |
20120122261 | CMOS IMAGER PHOTODIODE WITH ENHANCED CAPACITANCE - A method for manufacturing a pixel sensor cell that includes a photosensitive element having a non-laterally disposed charge collection region. The method includes forming a trench recess in a substrate of a first conductivity type material, and filling the trench recess with a material having second conductivity type material. The second conductivity type material is then diffused out of the filled trench material to the substrate region surrounding the trench to form the non-laterally disposed charge collection region. The filled trench material is removed to provide a trench recess, and the trench recess is filled with a material having a first conductivity type material. A surface implant layer is formed at either side of the trench having a first conductivity type material. A collection region of a trench-type photosensitive element is formed of the outdiffused second conductivity type material and is isolated from the substrate surface. | 05-17-2012 |
20120149200 | NITRIDE ETCH FOR IMPROVED SPACER UNIFORMITY - A method of forming dielectric spacers including providing a substrate comprising a first region having a first plurality of gate structures and a second region having a second plurality of gate structures and at least one oxide containing material or a carbon containing material. Forming a nitride containing layer over the first region having a thickness that is less than the thickness of the nitride containing layer that is present in the second region. Forming dielectric spacers from the nitride containing layer on the first plurality the second plurality of gate structures. The at least one oxide containing material or carbon containing material accelerates etching in the second region so that the thickness of the dielectric spacers in the first region is substantially equal to the thickness of the dielectric spacers in the second region of the substrate. | 06-14-2012 |
20120168835 | ANTI-REFLECTION STRUCTURES FOR CMOS IMAGE SENSORS - Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package. | 07-05-2012 |
20120181588 | PIXEL SENSOR CELLS WITH A SPLIT-DIELECTRIC TRANSFER GATE - Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. A transistor in the pixel sensor cell has a gate structure that includes a gate dielectric with a thick region and a thin region. A gate electrode of the gate structure is formed on the thick region of the gate dielectric and the thin region of the gate dielectric. The thick region of the gate dielectric and the thin region of the gate dielectric provide the transistor with an asymmetric threshold voltage. | 07-19-2012 |
20120211854 | PIXEL SENSOR CELL WITH A DUAL WORK FUNCTION GATE ELECTODE - Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. The pixel sensor cell has a gate structure that includes a gate dielectric and a gate electrode on the gate dielectric. The gate electrode includes a layer with first and second sections that have a juxtaposed relationship on the gate dielectric. The second section of the gate electrode is comprised of a conductor, such as doped polysilicon or a metal. The first section of the gate electrode is comprised of a metal having a higher work function than the conductor comprising the second section so that the gate structure has an asymmetric threshold voltage. | 08-23-2012 |
20120235216 | DAMASCENE METAL GATE AND SHIELD STRUCTURE, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - Semiconductor structures with damascene metal gates and pixel sensor cell shields, methods of manufacture and design structures are provided. The method includes forming a dielectric layer over a dummy gate structure. The method further includes forming one or more recesses in the dielectric layer. The method further includes removing the dummy gate structure in the dielectric layer to form a trench. The method further includes forming metal in the trench and the one more recesses in the dielectric layer to form a damascene metal gate structure in the trench and one or more metal components in the one or more recesses. | 09-20-2012 |
20120301990 | PIXEL SENSOR CELL WITH A DUAL WORK FUNCTION GATE ELECTODE - Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. The pixel sensor cell has a gate structure that includes a gate dielectric and a gate electrode on the gate dielectric. The gate electrode includes a layer with first and second sections that have a juxtaposed relationship on the gate dielectric. The second section of the gate electrode is comprised of a conductor, such as doped polysilicon or a metal. The first section of the gate electrode is comprised of a metal having a higher work function than the conductor comprising the second section so that the gate structure has an asymmetric threshold voltage. | 11-29-2012 |
20130001727 | IMAGE SENSOR, METHOD AND DESIGN STRUCTURE INCLUDING NON-PLANAR REFLECTOR - A solid state image sensor, a method for fabricating the solid state image sensor and a design structure for fabricating the solid state image sensor structure include a substrate that in turn includes a photosensitive region. Also included within solid state image sensor is a non-planar reflector layer located over a side of the photosensitive region and the substrate opposite an incoming radiation side of the photosensitive region and the substrate. The non-planar reflector layer is shaped and positioned to reflect uncaptured incident radiation back into the photosensitive region while avoiding optical cross-talk with an additional photosensitive region laterally separated within the substrate. | 01-03-2013 |
20130001732 | PIXEL SENSORS OF MULTIPLE PIXEL SIZE AND METHODS OF IMPLANT DOSE CONTROL - CMOS pixel sensors with multiple pixel sizes and methods of manufacturing the CMOS pixel sensors with implant dose control are provided. The method includes forming a plurality of pixel sensors in a same substrate and forming a masking pattern over at least one of the plurality of pixel sensors that has a pixel size larger than a non-masked pixel sensor of the plurality of pixel sensors. The method further includes providing a single dosage implant to the plurality of pixel sensors. The at least one of the plurality of pixel sensors with the masking pattern receives a lower dosage than the non-masked pixel sensor. | 01-03-2013 |
20130084476 | FUSE FOR THREE DIMENSIONAL SOLID-STATE BATTERY - A solid-state battery structure having a plurality of battery cells formed in a substrate, method of manufacturing the same and design structure thereof are provided. The battery structure includes a patterned cathode electrode layer formed upon the substrate and structured to form a plurality of sub-arrays of the battery cells. The battery structure further includes a plurality of fuse wires structured to interconnect at least two adjacent sub-arrays. At least one of the plurality of fuse wires is structured to be blown to disconnect an interconnection having a defective sub-array. Advantageously, the plurality of fuse wires is an integral part of the battery structure. | 04-04-2013 |
20130105941 | SEMICONDUCTOR DEVICE INCLUDING IN WAFER INDUCTORS, RELATED METHOD AND DESIGN STRUCTURE | 05-02-2013 |
20130119440 | BIOSENSORS INTEGRATED WITH A MICROFLUIDIC STRUCTURE - A biosensor with a microfluidic structure surrounded by an electrode and methods of forming the electrode around the microfluidic structure of the biosensor are provided. A method includes forming a gate or electrode in a first layer. The method further includes forming a trench in a second layer. The method further includes forming a first metal layer in the trench such that the first metal layer is in electrical contact with the gate or the electrode. The method further includes forming a sacrificial material in the trench. The method further includes forming a second metal layer over the sacrificial material and in contact with the first metal layer. The method further includes removing the sacrificial material such that a microfluidic channel is formed surrounded by the first and the second metal layers. | 05-16-2013 |
20130119442 | JUNCTION FIELD-EFFECT TRANSISTOR WITH RAISED SOURCE AND DRAIN REGIONS FORMED BY SELECTIVE EPITAXY - Junction field-effect transistors, methods for fabricating junction field-effect transistors, and design structures for a junction field-effect transistor. A source and a drain of the junction field-effect transistor are comprised of a semiconductor material grown by selective epitaxy and in direct contact with a top surface of a semiconductor layer. A gate is formed that is aligned with a channel laterally disposed in the semiconductor layer between the source and the drain. The source, the drain, and the semiconductor layer are each comprised of a second semiconductor material having an opposite conductivity type from a first semiconductor material comprising the gate. | 05-16-2013 |
20130119447 | NON-UNIFORM GATE DIELECTRIC CHARGE FOR PIXEL SENSOR CELLS AND METHODS OF MANUFACTURING - A non-uniform gate dielectric charge for pixel sensor cells, e.g., CMOS optical imagers, and methods of manufacturing are provided. The method includes forming a gate dielectric on a substrate. The substrate includes a source/drain region and a photo cell collector region. The method further includes forming a non-uniform fixed charge distribution in the gate dielectric. The method further includes forming a gate structure on the gate dielectric. | 05-16-2013 |
20130134483 | BIPOLAR TRANSISTOR WITH A RAISED COLLECTOR PEDASTAL FOR REDUCED CAPACITANCE AND A METHOD OF FORMING THE TRANSISTOR - Disclosed are a transistor and a method of forming the transistor with a raised collector pedestal in reduced dimension for reduced base-collector junction capacitance. The raised collector pedestal is on the top surface of a substrate, extends vertically through dielectric layer(s), is un-doped or low-doped, is aligned above a sub-collector region contained within the substrate and is narrower than that sub-collector region. An intrinsic base layer is above the raised collector pedestal and the dielectric layer(s). An extrinsic base layer is above the intrinsic base layer. Thus, the space between the extrinsic base layer and the sub-collector region is increased. This increased space is filled by dielectric material and the electrical connection between the intrinsic base layer and the sub-collector region is provided by the relatively narrow, un-doped or low-doped, raised collector pedestal. Consequently, base-collector junction capacitance is reduced and, consequently, the maximum oscillation frequency is increased. | 05-30-2013 |
20130161618 | SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE - Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure. | 06-27-2013 |
20130161777 | ANTI-REFLECTION STRUCTURES FOR CMOS IMAGE SENSORS - Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package. | 06-27-2013 |
20130170012 | MICROMIRRORS FOR COLOR ELECTRONIC PAPER AND DESIGN STRUCTURES FOR SAME - Direct view color displays and design structures of direct view color displays. The direct view displays include micromirrors having un-tilted and tilted states and multiple color filters or color reflectors. | 07-04-2013 |
20130175651 | DAMASCENE METAL GATE AND SHIELD STRUCTURE, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - Semiconductor structures with damascene metal gates and pixel sensor cell shields, methods of manufacture and design structures are provided. The method includes forming a dielectric layer over a dummy gate structure. The method further includes forming one or more recesses in the dielectric layer. The method further includes removing the dummy gate structure in the dielectric layer to form a trench. The method further includes forming metal in the trench and the one more recesses in the dielectric layer to form a damascene metal gate structure in the trench and one or more metal components in the one or more recesses. | 07-11-2013 |
20130186754 | BIOSENSOR CAPACITOR - A biosensor capacitor, including a dielectric layer; a first metal layer in the dielectric layer; a passivation layer over the dielectric layer and the first metal layer; an isolation layer over the passivation layer; a probe DNA electrode connected to the first metal layer; a counter electrode connected to the first metal layer wherein the counter electrode forms an enclosure around the probe DNA electrode; and a bond pad connected to the first metal layer. | 07-25-2013 |
20130200434 | USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES - Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET. | 08-08-2013 |
20130200910 | 3-DIMENSIONAL INTEGRATED CIRCUIT TESTING USING MEMS SWITCHES WITH TUNGSTEN CONE CONTACTS - A test system for testing a multilayer 3-dimensional integrated circuit (IC), where two separate layers of IC circuits are temporarily connected in order to achieve functionality, includes a chip under test with a first portion of the 3-dimensional IC, and a test probe chip with a second portion of the 3-dimensional IC and micro-electrical-mechanical system (MEMS) switches that selectively complete functional circuits between the first portion of the 3-dimensional IC in a first IC layer to circuits within the second portion of the 3-dimensional IC in a second IC layer. The MEMS switches include tungsten (W) cone contacts, which make the selective electrical contacts between circuits of the chip under test and the test probe chip and which are formed using a template of graded borophosphosilicate glass (BPSG). | 08-08-2013 |
20130210227 | USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES - Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET. | 08-15-2013 |
20130224896 | MICRO-ELECTRO-MECHANICAL SYSTEM TILTABLE LENS - A tiltable micro-electro-mechanical (MEMS) system lens comprises a microscopic lens located on a front surface of a semiconductor-on-insulator (SOI) substrate and a semiconductor rim surrounding the periphery of the microscopic lens. Two horizontal semiconductor beams located at different heights are provided within a top semiconductor layer. The microscopic lens may be tilted by applying an electrical bias between the lens rim and one of the two semiconductor beams, thereby altering the path of an optical beam through the microscopic lens. An array of tiltable microscopic lenses may be employed to form a composite lens having a variable focal length may be formed. A design structure for such a tiltable MEMS lens is also provided. | 08-29-2013 |
20130228835 | SEMICONDUCTOR STRUCTURES USING REPLACEMENT GATE AND METHODS OF MANUFACTURE - An improved semiconductor device manufactured using, for example, replacement gate technologies. The method includes forming a dummy gate structure having a gate stack and spacers. The method further includes forming a dielectric material adjacent to the dummy gate structure. The method further includes removing the spacers to form gaps, and implanting a halo extension through the gaps and into an underlying diffusion region. | 09-05-2013 |
20130265068 | BUILT-IN SELF-TEST METHOD AND STRUCTURE - A method of testing a semiconductor wafer and a related structure. In various embodiments, a method includes: placing a probe on a first chip on the semiconductor wafer; testing a scribe line automatic built-in self-test (ABIST) for the first chip to search for a fault; progressively testing a subsequent scribe line ABIST for a subsequent chip on the semiconductor wafer in response to determining the ABIST for the first chip does not indicate the fault; moving the probe point to the subsequent chip and retesting the subsequent scribe line ABIST in response to determining the ABIST for the subsequent chip indicates a fault; and testing a further subsequent scribe line ABIST for a further subsequent chip on the semiconductor wafer in response to determining the retesting of the subsequent scribiline ABIST does not indicate a fault in the subsequent scribe line ABIST. | 10-10-2013 |
20130299939 | CHIP IDENTIFICATION PATTERN AND METHOD OF FORMING - Various embodiments disclosed include methods of performing a double exposure process on a level of an integrated circuit (IC) chip to form an IC chip having an embedded electrically measurable identifier. In some cases, the method includes: exposing a level of an integrated circuit (IC) chip using a first mask orientation; subsequently exposing the level of the IC chip using a second mask orientation distinct from the first mask orientation; and developing the level of the IC chip to form an electrically measurable identifier on the IC chip. | 11-14-2013 |
20140004687 | SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE | 01-02-2014 |
20140021516 | BIOSENSORS INTEGRATED WITH A MICROFLUIDIC STRUCTURE - A biosensor with a microfluidic structure surrounded by an electrode and methods of forming the electrode around the microfluidic structure of the biosensor are provided. A method includes forming a gate or electrode in a first layer. The method further includes forming a trench in a second layer. The method further includes forming a first metal layer in the trench such that the first metal layer is in electrical contact with the gate or the electrode. The method further includes forming a sacrificial material in the trench. The method further includes forming a second metal layer over the sacrificial material and in contact with the first metal layer. The method further includes removing the sacrificial material such that a microfluidic channel is formed surrounded by the first and the second metal layers. | 01-23-2014 |
20140097434 | BACK-END-OF-LINE METAL-OXIDE-SEMICONDUCTOR VARACTORS - Device structures, design structures, and fabrication methods for a varactor. The device structure includes a first electrode formed on a dielectric layer, and a semiconductor body formed on the first electrode. The semiconductor body is comprised of a silicon-containing semiconductor material in an amorphous state or a polycrystalline state. The device structure further includes an electrode insulator formed on the semiconductor body and a second electrode formed on the electrode insulator. | 04-10-2014 |
20140145747 | LIGHT ACTIVATED TEST CONNECTIONS - A test circuit including a light activated test connection in a semiconductor device is provided. The light activated test connection is electrically conductive during a test of the semiconductor device and is electrically non-conductive after the test. | 05-29-2014 |
20140183753 | FABRICATING POLYSILICON MOS DEVICES AND PASSIVE ESD DEVICES - A semiconductor fabrication is described, wherein a MOS device and a MEMS device is fabricated simultaneously in the BEOL process. A silicon layer is deposited and etched to form a silicon film for a MOS device and a lower silicon sacrificial film for a MEMS device. A conductive layer is deposited atop the silicon layer and etched to form a metal gate and a first upper electrode. A dielectric layer is deposited atop the conductive layer and vias are formed in the dielectric layer. Another conductive layer is deposited atop the dielectric layer and etched to form a second upper electrode and three metal electrodes for the MOS device. Another silicon layer is deposited atop the other conductive layer and etched to form an upper silicon sacrificial film for the MEMS device. The upper and lower silicon sacrificial films are then removed via venting holes. | 07-03-2014 |
20140321801 | VERTICAL BEND WAVEGUIDE COUPLER FOR PHOTONICS APPLICATIONS - An optical waveguide structure may include a dielectric layer having a top surface, an optical waveguide structure, and an optical coupler embedded within the dielectric layer. The optical coupler may have both a substantially vertical portion that couples to the top surface of the dielectric layer and a substantially horizontal portion that couples to the optical waveguide structure. The substantially vertical portion and the substantially horizontal portion are separated by a curved portion. | 10-30-2014 |
20140321802 | VERTICALLY CURVED WAVEGUIDE - An optical waveguide structure may include an optical waveguide structure located within a semiconductor structure and an optical coupler. The optical coupler may include a metallic structure located within an electrical interconnection region of the semiconductor structure, whereby the metallic structure extends downward in a substantially curved shape from a top surface of the electrical interconnection region and couples to the optical waveguide structure. The optical coupler may further include an optical signal guiding region bounded within the metallic structure, whereby the optical coupler receives an optical signal from the top surface and couples the optical signal to the optical waveguide structure such that the optical signal propagation is substantially vertical at the top surface and substantially horizontal at the optical waveguide structure. | 10-30-2014 |
20140339607 | FABRICATING POLYSILICON MOS DEVICES AND PASSIVE ESD DEVICES - A semiconductor fabrication is described, wherein a MOS device and a MEMS device is fabricated simultaneously in the BEOL process. A silicon layer is deposited and etched to form a silicon film for a MOS device and a lower silicon sacrificial film for a MEMS device. A conductive layer is deposited atop the silicon layer and etched to form a metal gate and a first upper electrode. A dielectric layer is deposited atop the conductive layer and vias are formed in the dielectric layer. Another conductive layer is deposited atop the dielectric layer and etched to form a second upper electrode and three metal electrodes for the MOS device. Another silicon layer is deposited atop the other conductive layer and etched to form an upper silicon sacrificial film for the MEMS device. The upper and lower silicon sacrificial films are then removed via venting holes. | 11-20-2014 |
20140340548 | PIXEL SENSOR CELL WITH HOLD NODE FOR LEAKAGE CANCELLATION AND METHODS OF MANUFACTURE AND DESIGN STRUCTURE - A reference pixel sensor cell (e.g., global shutter) with hold node for leakage cancellation, methods of manufacture and design structure is provided. A pixel array includes one or more reference pixel sensor cells dispersed locally throughout active light sensing regions. The one or more reference pixel sensor cells provides a reference signal used to correct for photon generated leakage signals which vary by locality within the active light sensing regions. | 11-20-2014 |
20140346596 | HIGH VOLTAGE LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR - High-voltage LDMOS devices with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming an array of poly islands and a control gate structure by patterning a poly layer formed over a deep well region and a body of a substrate. The method further includes forming a metal shield in contact with the control gate structure and over the array of poly islands. | 11-27-2014 |
20140353759 | Self-Aligned Gate Electrode Diffusion Barriers - A self-aligned diffusion barrier may be formed by forming a first masking layer, having a vertical sidewall on a semiconductor layer, above a first portion of the semiconductor layer. A first spacer layer, including a spacer region on the vertical sidewall, may be formed above the semiconductor layer. A second portion of the semiconductor layer not covered by the first masking layer or the spacer region may then be doped. A second masking layer may then be formed over the first spacer layer and planarized to expose at least a portion of the spacer region. The spacer region may then be etched to form a notch exposing a third portion of the semiconductor layer. The third portion may then be doped with a barrier dopant. The first masking layer may be removed and a second spacer layer filling the notch may be formed. The first portion may then be doped. | 12-04-2014 |
20150014769 | HIGH VOLTAGE LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR - A high-voltage LDMOS device with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming a continuous gate structure over a deep well region and a body of a substrate. The method further includes forming oppositely doped, alternating segments in the continuous gate structure. The method further includes forming a contact in electrical connection with a tip of the continuous gate structure and a drain region formed in the substrate. The method further includes forming metal regions in direct electrical contact with segments of at least one species of the oppositely doped, alternating segments. | 01-15-2015 |
20150014771 | DUAL L-SHAPED DRIFT REGIONS IN AN LDMOS DEVICE AND METHOD OF MAKING THE SAME - A semiconductor device comprising dual L-shaped drift regions in a lateral diffused metal oxide semiconductor (LDMOS) and a method of making the same. The LDMOS in the semiconductor device comprises a trench isolation region or a deep trench encapsulated by a liner, a first L-shaped drift region, and a second L-shaped drift region. The LDMOS comprising the dual L-shape drift regions is integrated with silicon-germanium (SiGe) technology. The LDMOS comprising the dual L-shape drift regions furnishes a much higher voltage drop in a lateral direction within a much shorter distance from a drain region than the traditional LDMOS does. | 01-15-2015 |
20150028449 | NANOPARTICLES FOR MAKING SUPERCAPACITOR AND DIODE STRUCTURES - Structures and methods of making a supercapacitor may include a first electrode comprising a first conductive plate and a 3-dimensional (3D) aggregate of sintered nanoparticles electrically connected one to another and to the first conductive plate. The supercapacitor may also include a dielectric formed on surfaces of the 3D aggregate of sintered nanoparticles. The supercapacitor may further include a second electrode comprising a solid second conductor that fills interstices between surfaces of the dielectric and electrically connects to a second conductive plate of a solid second conductor, disposed above an outermost portion of the dielectric. | 01-29-2015 |
20150035076 | Self-Aligned Gate Electrode Diffusion Barriers - A structure that provides a diffusion barrier between two doped regions. The structure includes a diffusion barrier including a semiconductor layer comprising a first doped region and a second doped region; and a diffusion barrier separating the first doped region and the second doped region, wherein the diffusion barrier comprises a doped portion and a notch above the doped portion. | 02-05-2015 |
20150085408 | EOS PROTECTION CIRCUIT WITH FET-BASED TRIGGER DIODES - An integrated circuit is disclosed, including a circuit with a first type of FET having a first breakdown voltage (VBD), resulting from a first set of design and manufacturing process parameters and having VBD tracking characteristics resulting from a second set of design and manufacturing process parameters. The IC may include a trigger device circuit a having a trigger FET that may generate, in response to the supply voltage exceeding a specified maximum, a signal on a trigger device output, causing a clamping device to couple the supply voltage node to the ground, to reduce the supply voltage. The trigger FET may be of a second type having a second VBD less than the first VBD, resulting from modifications to the first set of design and manufacturing process parameters, and VBD tracking characteristics resulting from the second set of design and manufacturing process parameters. | 03-26-2015 |