| Patent application number | Description | Published |
|---|
| 20140027933 | DEVICE AND METHOD FOR ALIGNMENT OF VERTICALLY STACKED WAFERS AND DIE - A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively. | 01-30-2014 |
| 20140134808 | RECESSED GATE FIELD EFFECT TRANSISTOR - A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode. | 05-15-2014 |
| 20150053930 | ATOMIC LAYER DEPOSITION OF SELECTED MOLECULAR CLUSTERS - Energy bands of a thin film containing molecular clusters are tuned by controlling the size and the charge of the clusters during thin film deposition. Using atomic layer deposition, an ionic cluster film is formed in the gate region of a nanometer-scale transistor to adjust the threshold voltage, and a neutral cluster film is formed in the source and drain regions to adjust contact resistance. A work function semiconductor material such as a silver bromide or a lanthanum oxide is deposited so as to include clusters of different sizes such as dimers, trimers, and tetramers, formed from isolated monomers. A type of Atomic Layer Deposition system is used to deposit on semiconductor wafers molecular clusters to form thin film junctions having selected energy gaps. A beam of ions contains different ionic clusters which are then selected for deposition by passing the beam through a filter in which different apertures select clusters based on size and orientation. | 02-26-2015 |
| 20150087205 | ADAPTIVE UNIFORM POLISHING SYSTEM - An adaptive uniform polishing system is equipped with feedback control to apply localized adjustments during a polishing operation. The adaptive uniform polishing system disclosed has particular application to the semiconductor industry. Such an adaptive uniform polishing system includes a rotatable head that holds a semiconductor wafer, and a processing unit structured to be placed in contact with an exposed surface of the wafer. The processing unit includes a rotatable macro-pad and a plurality of rotatable micro-pads that can polish different portions of the exposed surface at different rotation speeds and pressures. Thus, uniformity across the exposed surface can be enhanced by applying customized treatments to different areas. Customized treatments can include the use of different pad materials and geometries. Parameters of the adaptive uniform polishing system are programmable, based on in-situ data or data from other operations in a fabrication process, using advanced process control. | 03-26-2015 |
| 20150096591 | POST-CMP HYBRID WAFER CLEANING TECHNIQUE - A brush-cleaning apparatus is disclosed for use in cleaning a semiconductor wafer after polishing. Embodiments of the brush-cleaning apparatus implemented with a multi-branch chemical dispensing unit are applied beneficially to clean semiconductor wafers, post-polish, using a hybrid cleaning method. An exemplary hybrid cleaning method employs a two-chemical sequence in which first and second chemical treatment modules are separate from one another, and are followed by a pH-neutralizing-rinse that occurs in a treatment module separate from the first and second chemical treatment modules. Implementation of such hybrid methods is facilitated by the multi-branch chemical dispensing unit, which provides separate chemical lines to different chemical treatment modules, and dispenses chemical to at least four different areas of each wafer during single-wafer processing in an upright orientation. The multi-branch chemical dispensing unit provides a flexible, modular building block for constructing various equipment configurations that use multiple chemical treatments and/or pH neutralization steps. | 04-09-2015 |
| 20150097289 | HYBRID PHOTONIC AND ELECTRONIC INTEGRATED CIRCUITS - A sequence of processing steps presented herein is used to embed an optical signal path within an array of nanowires, using only one lithography step. Using the techniques disclosed, it is not necessary to mask electrical features while forming optical features, and vice versa. Instead, optical and electrical signal paths can be created substantially simultaneously in the same masking cycle. This is made possible by a disparity in the widths of the respective features, the optical signal paths being significantly wider than the electrical ones. Using a damascene process, the structures of disparate widths are plated with metal that over-fills narrow trenches and under-fills a wide trench. An optical cladding material can then be deposited into the trench so as to surround an optical core for light transmission. | 04-09-2015 |
| 20150102496 | NOVEL METHOD TO MAKE HIGH ASPECT RATIO VIAS FOR HIGH PERFORMANCE DEVICES INTERCONNECTION APPLICATION - Metal interconnections are formed in an integrated circuit by forming a wide trench in a dielectric layer. A dielectric fin of a second dielectric material is formed in the trench. Conductive plugs and metal lines are formed on both sides of the fin. | 04-16-2015 |
| 20150115401 | TECHNIQUE FOR FABRICATION OF MICROELECTRONIC CAPACITORS AND RESISTORS - A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method of fabricating such a structure cleverly takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers. The resistors and capacitors thus formed as a set of integrated circuit elements are suitable for use as microelectronic fuses and antifuses, respectively, to protect underlying microelectronic circuits. | 04-30-2015 |
