Patent application number | Description | Published |
20120299155 | METHOD FOR FORMING FULLY RELAXED SILICON GERMANIUM ON SILICON - Semiconductor devices are formed with a thin layer of fully strain relaxed epitaxial silicon germanium on a substrate. Embodiments include forming a silicon germanium (SiGe) epitaxial layer on a semiconductor substrate, implanting a dopant into the SiGe epitaxial layer, and annealing the implanted SiGe epitaxial layer. | 11-29-2012 |
20120329230 | FABRICATION OF SILICON OXIDE AND OXYNITRIDE HAVING SUB-NANOMETER THICKNESS - A method of fabricating a silicon-containing oxide layer that includes providing a chemical oxide layer on a surface of a semiconductor substrate, removing the chemical oxide layer in an oxygen-free environment at a temperature of 1000° C. or greater to provide a bare surface of the semiconductor substrate, and introducing an oxygen-containing gas at a flow rate to the bare surface of the semiconductor substrate for a first time period at the temperature of 1000° C. The temperature is then reduced to room temperature during a second time period while maintaining the flow rate of the oxygen containing gas to provide a silicon-containing oxide layer having a thickness ranging from 0.5 Å to 10 Å. | 12-27-2012 |
20130005103 | METHODS FOR FABRICATING A FINFET INTEGRATED CIRCUIT ON A BULK SILICON SUBSTRATE - Methods are provided for fabricating a FINFET integrated circuit that includes epitaxially growing a first silicon germanium layer and a second silicon layer overlying a silicon substrate. The second silicon layer is etched to form a silicon fin using the first silicon germanium layer as an etch stop. The first silicon germanium layer underlying the fin is removed to form a void underlying the fin and the void is filled with an insulating material. A gate structure is then formed overlying the fin. | 01-03-2013 |
20130049142 | TRANSISTOR WITH REDUCED PARASITIC CAPACITANCE - Scaled transistors with reduced parasitic capacitance are formed by replacing a high-k dielectric sidewall spacer with a SiO | 02-28-2013 |
20130082332 | METHOD FOR FORMING N-TYPE AND P-TYPE METAL-OXIDE-SEMICONDUCTOR GATES SEPARATELY - Semiconductor devices with replacement gate electrodes are formed with different materials in the work function layers. Embodiments include forming first and second removable gates on a substrate, forming first and second pairs of spacers on opposite sides of the first and second removable gates, respectively, forming a hardmask layer over the second removable gate, removing the first removable gate, forming a first cavity between the first pair of spacers, forming a first work function material in the first cavity, removing the hardmask layer and the second removable gate, forming a second cavity between the second pair of spacers, and forming a second work function material, different from the first work function material, in the second cavity. | 04-04-2013 |
20130181260 | METHOD FOR FORMING N-SHAPED BOTTOM STRESS LINER - Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner. | 07-18-2013 |
20130277765 | SEMICONDUCTOR DEVICE INCLUDING GRADED GATE STACK, RELATED METHOD AND DESIGN STRUCTURE - A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region. | 10-24-2013 |
20130330843 | METHOD OF MANUFACTURING SCALED EQUIVALENT OXIDE THICKNESS GATE STACKS IN SEMICONDUCTOR DEVICES AND RELATED DESIGN STRUCTURE - A method of forming a semiconductor device is disclosed. The method includes: forming a dielectric region on a substrate; annealing the dielectric region in an environment including ammonia (NH | 12-12-2013 |
20140001570 | COMPOSITE HIGH-K GATE DIELECTRIC STACK FOR REDUCING GATE LEAKAGE | 01-02-2014 |
20140070334 | SEMICONDUCTOR DEVICE INCLUDING GRADED GATE STACK, RELATED METHOD AND DESIGN STRUCTURE - A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region. | 03-13-2014 |
20140120708 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING REPLACEMENT METAL GATE PROCESS INCORPORATING A CONDUCTIVE DUMMY GATE LAYER - A method of manufacturing a semiconductor device including a replacement metal gate process incorporating a conductive dummy gate layer (e.g., silicon germanium (SiGe), titanium nitride, etc.) and a related are disclosed. The method includes forming an oxide layer on a substrate; removing a gate portion of the oxide layer from the substrate in a first region of the semiconductor device; forming a conductive dummy gate layer on the semiconductor device in the first region; and forming a gate on the semiconductor device, the gate including a gate conductor disposed in the first region and directly connected to the substrate. | 05-01-2014 |
20140159052 | METHOD AND STRUCTURE FOR TRANSISTOR WITH REDUCED DRAIN-INDUCED BARRIER LOWERING AND ON RESISTANCE - Embodiments of the invention provide an improved method and structure for a transistor with reduced DIBL and R | 06-12-2014 |
20140187028 | Concurrently Forming nFET and pFET Gate Dielectric Layers - Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region. | 07-03-2014 |