| Patent application number | Description | Published |
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| 20090326211 | Process for concentrating and processing fluid samples - A method of treating a liquid sample having microbiological target species therein to concentrate the species and collect lysate is disclosed. The liquid sample comprises non-target microbiological particles, inorganic particles, and microbiological target species. The liquid is passed through a prefilter medium to allow the target species to pass through as filtrate and retain non-target microbiological products and inorganic particles thereon. The filtrate is contacted with a main filtration medium adapted to retain the target species thereon as retentate. The retentate is lysed to form a lysate containing target material that was enveloped within the microbiological target species. The microbiological species may comprise cell containing or viral material. Target materials comprise intracellular nucleic acids, or in the case of viral sampling, nucleic acids encased within the protein sheath or coating of the virus. | 12-31-2009 |
| 20110032683 | POWER MODULE AND CIRCUIT BOARD ASSEMBLY THEREOF - A power module includes a first bobbin, a primary winding coil, a circuit board assembly and a first magnetic core assembly. The primary winding coil is wound around the first bobbin. The circuit board assembly includes a printed circuit board, a second winding structure, at least one current-sensing element, a rectifier circuit and an electrical connector. The second winding structure has an output terminal. The current-sensing element includes a first conductor. The first conductor is a conductive sheet. A first end of the first conductor is in contact with the output terminal of the second winding structure. A second end of the first conductor is connected to the rectifier circuit. The primary winding coil is aligned with the second winding structure of the circuit board assembly and arranged within the first magnetic core assembly. The primary winding coil and the electrical connector are electrically connected with a system board. | 02-10-2011 |
| 20110038182 | POWER CONVERTER HAVING SYNCHRONOUS RECTIFIER AND CONTROL METHOD OF SYNCHRONOUS RECTIFIER - Disclosed is a power converter including a switching circuit; a transformer having a primary winding connected to the switching circuit and a secondary winding; a main control circuit connected to the switching circuit for outputting a main control signal to manipulate the switching circuit; at least one synchronous rectifier connected to the secondary winding; at least one current transformer connected to the synchronous rectifier for outputting a detecting signal according to a current flowing through the synchronous rectifier; and at least one synchronous rectification control circuit connected to a control terminal of the synchronous rectifier, the current transformer, and a control terminal of the switching circuit for receiving the detecting signal and the main control signal for manipulating the synchronous rectifier. In case that the main control circuit manipulates the switching circuit to turn on, the synchronous rectification control circuit manipulates the synchronous rectifier to turn on, and thereby allowing the synchronous rectification control circuit to manipulate the synchronous rectifier to turn off according to the detecting signal. | 02-17-2011 |
| 20110129843 | METHOD FOR EVALUATING THE VIRULENCE OF PATHOGENIC BIPHASIC BACTERIA - A method for evaluating relative bacterial virulence of a biphasic bacteria in environmental systems includes measuring the concentration of DNA in the bacteria, measuring the concentration of RNA in the bacteria, determining a ratio of the concentration of RNA to the concentration of DNA and correlating the concentration ratio with a level of relative pathogenicity, wherein the bacteria is preferentially | 06-02-2011 |
| 20110199842 | DRAM CELL UTILIZING FLOATING BODY EFFECT AND MANUFACTURING METHOD THEREOF - The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a first N type semiconductor region provided on a buried oxide layer, a P type semiconductor region provided on the first N type semiconductor region, a gate region provided on the P type semiconductor region, and an electrical isolation region surrounding the P type semiconductor region and the N type semiconductor region. A diode is taken as a storage node. Via a tunneling effect between bands, holes gather in the floating body, which is defined as a first storage state; via forward bias of PN junction, holes are emitted out from the floating body or electrons are injected into the floating body, which is defined as a second storage state. The present invention provides a highly efficient DRAM cell utilizing floating body effect with high density, which has low power consumption, has simple manufacturing process, and is compatible to the conventional CMOS and conventional logic circuit manufacturing process. | 08-18-2011 |
| 20110221002 | MOS-TYPE ESD PROTECTION DEVICE IN SOI AND MANUFACTURING METHOD THEREOF - The present invention discloses a MOS ESD protection device for SOI technology and a manufacturing method for the device. The MOS ESD protection device comprises: an epitaxial silicon layer grown on top of an SOI substrate; a first side-wall spacer disposed on both sides of the epitaxial silicon layer so as to isolate the ESD protection device from the intrinsic active structures; a source region and a drain region disposed respectively on two sides of the epitaxial silicon layer; a poly silicon gate and a gate dielectric formed on top of the epitaxial silicon layer; and a second side-wall spacer disposed on both sides of the poly silicon gate of . ESD leakage current passes down to the SOI substrate for protection. Because ESD protection device and intrinsic MOS transistor are located in the same plane, this fabrication process can be inserted in the current MOS process flow. | 09-15-2011 |
| 20110233727 | VERTICAL SOI BIPOLAR JUNCTION TRANSISTOR AND MANUFACTURING METHOD THEREOF - The present invention discloses a vertical SOI bipolar junction transistor and a manufacturing method thereof. The bipolar junction transistor includes an SOI substrate from down to up including a body region, a buried oxide layer and a top silicon film; an active region located in the top silicon film formed by STI process; a collector region located in the active region deep close to the buried oxide layer formed by ion implantation; a base region located in the active region deep close to the top silicon film formed by ion implantation; an emitter and a base electrode both located over the base region; a side-wall spacer located around the emitter and the base electrode. The present invention utilizing a simple double poly silicon technology not only can improve the performance of the transistor, but also can reduce the area of the active region in order to increase the integration density. Furthermore, the present invention utilizes side-wall spacer process to improve the compatibility of SOI BJT and SOI CMOS, which simplifies the SOI BiCMOS process and thus reduce the cost. | 09-29-2011 |
| 20110248354 | HYBRID MATERIAL INVERSION MODE GAA CMOSFET - A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, the devices have hybrid material, GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, prevent polysilicon gate depletion and short channel effects. | 10-13-2011 |
| 20110254013 | HYBRID ORIENTATION ACCUMULATION MODE GAA CMOSFET - A hybrid orientation accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Si(110) and n-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device results in high carrier mobility. Meanwhile polysilicon gate depletion and short channel effects are prevented, and threshold voltage is increased. | 10-20-2011 |
| 20110254099 | Hybrid material accumulation mode GAA CMOSFET - A Ge and Si hybrid material accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of p-type Ge and n-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an accumulation mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device. | 10-20-2011 |
| 20110254100 | HYBRID MATERIAL ACCUMULATION MODE GAA CMOSFET - A Ge and Si hybrid material accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Ge and n-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device has high carrier mobility, high device drive current, and maintains the electrical integrity of the device. Meanwhile, polysilicon gate depletion and short channel effects are prevented. | 10-20-2011 |
| 20110254101 | HYBRID MATERIAL INVERSION MODE GAA CMOSFET - A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device. | 10-20-2011 |
| 20110254102 | HYBRID ORIENTATION INVERSION MODE GAA CMOSFET - A hybrid orientation inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Si (110) and p-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an inversion mode, the devices have different orientation channels, the GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, and prevent polysilicon gate depletion and short channel effects. | 10-20-2011 |
| 20110291191 | MOS Structure with Suppressed SOI Floating Body Effect and Manufacturing Method thereof - The present invention discloses a MOS structure with suppressed floating body effect including a substrate, a buried insulation layer provided on the substrate, and an active area provided on the buried insulation layer comprising a body region, a first conductive type source region and a first conductive type drain region provided on both sides of the body region respectively and a gate region provide on top of the body region, wherein the active area further comprises a highly doped second conductive type region between the first conductive type source region and the buried insulation layer. For manufacturing this structure, implant ions into a first conductive type source region via a mask having an opening thereon forming a highly doped second conductive type region under the first conductive type source region and above the buried insulation layer. The present invention will not increase chip area and is compatible with conventional CMOS process. | 12-01-2011 |
| 20110292723 | DRAM CELL UTILIZING FLOATING BODY EFFECT AND MANUFACTURING METHOD THEREOF - The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a P type semiconductor region provided on a buried oxide layer, an N type semiconductor region provided on the P type semiconductor region, a gate region provided on the N type semiconductor region, and an electrical isolation region surrounding the P type semiconductor region and the N type semiconductor region. A diode of floating body effect is taken as a storage node. Via a tunneling effect between bands, electrons gather in the floating body, which is defined as a first storage state; via forward bias of PN junction, electrons are emitted out from the floating body or holes are injected into the floating body, which is defined as a second storage state. The present invention provides a highly efficient DRAM cell utilizing floating body effect with high density, which has low power consumption, has simple manufacturing process, and is compatible to the conventional CMOS and conventional logic circuit manufacturing process. | 12-01-2011 |
| 20120009741 | SOI MOS DEVICE HAVING A SOURCE/BODY OHMIC CONTACT AND MANUFACTURING METHOD THEREOF - The present invention discloses a manufacturing method of SOI MOS device having a source/body ohmic contact. The manufacturing method comprises steps of: firstly creating a gate region, then performing high dose source and drain light doping to form the lightly doped N-type source region and lightly doped N-type drain region; forming an insulation spacer surrounding the gate region; performing large tilt heavily-doped P ion implantation in an inclined direction via a mask with an opening at the position of the N type Si source region and implanting P ions into the space between the N type Si source region and the N type drain region to form a heavily-doped P-type region; finally forming a metal layer on the N type Si source region, then allowing the reaction between the metal layer and the remained Si material underneath to form silicide by heat treatment. In the device prepared by the method of the present invention, an ohmic contact is formed between the silicide and the heavily-doped P-type region nearby in order to release the holes accumulated in body region of the SOI MOS device and eliminate floating body effects thereof. Besides, the device of the present invention also has following advantages, such as limited chip area, simplified fabricating process and great compatibility with traditional CMOS technology. | 01-12-2012 |
| 20120012931 | SOI MOS DEVICE HAVING BTS STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention discloses a SOI MOS device having BTS structure and manufacturing method thereof. The source region of the SOI MOS device comprises: two heavily doped N-type regions, a heavily doped P-type region formed between the two heavily doped N-type regions, a silicide formed above the heavily doped N-type regions and the heavily doped P-type region, and a shallow N-type region which is contact to the silicide; an ohmic contact is formed between the heavily doped P-type region and the silicide thereon to release the holes accumulated in body region of the SOI MOS device and eliminate floating body effects thereof without increasing the chip area and also overcome the disadvantages such as decreased effective channel width of the devices in the BTS structure of the prior art. The manufacturing method comprises steps of: forming a heavily doped P-type region via ion implantation, forming a metal layer above the source region and forming a silicide via the heat treatment between the metal layer and the Si underneath. The device in the present invention could be fabricated via simplified fabricating process with great compatibility with traditional CMOS technology. | 01-19-2012 |
| 20120018809 | MOS DEVICE FOR ELIMINATING FLOATING BODY EFFECTS AND SELF-HEATING EFFECTS - A MOS device having low floating charge and low self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided. | 01-26-2012 |
| 20120021571 | Method of Reducing Floating Body Effect of SOI MOS Device Via a Large Tilt Ion Implantation - The present invention discloses a method of reducing floating body effect of SOI MOS device via a large tilt ion implantation including a step of: (a) implanting ions in an inclined direction into an NMOS with a buried insulation layer forming a highly doped P region under a source region of the NMOS and above the buried insulation layer, wherein the angle between a longitudinal line of the NMOS and the inclined direction is ranging from 15 to 45 degrees. Through this method, the highly doped P region under the source region and a highly doped N region form a tunnel junction so as to reduce the floating body effect. Furthermore, the chip area will not be increased, manufacturing process is simple and the method is compatible with conventional CMOS process. | 01-26-2012 |
| 20120025267 | MOS DEVICE FOR ELIMINATING FLOATING BODY EFFECTS AND SELF-HEATING EFFECTS - A SOI MOS device for eliminating floating body effects and self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating body effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided. | 02-02-2012 |
| 20120093036 | METHOD, SYSTEM AND NETWORK DEVICE FOR IMPLEMENTING LOCAL IP ACCESS - A method for implementing local Internet Protocol (IP) access includes: obtaining User Equipment (UE)'s first information that is used for implementing local IP access; and implementing local IP access of the UE according to the first information. A system for implementing local IP access is disclosed by the present invention. The system can communicate with UE and includes: a NodeB, configured to obtain UE's first information that is used for implementing local IP access, and implement local IP access of the UE according to the first information; and a core network node, configured to assist the NodeB in obtaining the UE's first information that is used for implementing local IP access. Besides, relevant network devices are also disclosed. | 04-19-2012 |
| 20120112283 | ESD PROTECTION DEVICES FOR SOI INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF - The present invention discloses an ESD protection structure in a SOI CMOS circuitry. The ESD protection structure includes a variety of longitudinal (vertical) PN junction structures having significantly enlarged junction areas for current flow. The resulting devices achieve increased heavy current release capability. Processes of fabricating varieties of the ESD protection longitudinal PN junction are also disclosed. Compatibility of the disclosed fabrication processes with current SOI technology reduces implementation cost and improves the integration robustness. | 05-10-2012 |
| 20120115287 | MANUFACTURING METHOD OF SOI MOS DEVICE ELIMINATING FLOATING BODY EFFECTS - The present invention discloses a manufacturing method of SOI MOS device eliminating floating body effects. The active area of the SOI MOS structure according to the present invention includes a body region, a N-type source region, a N-type drain region, a heavily doped P-type region, wherein the N-type source region comprises a silicide and a buried insulation region and the heavily doped P-type region is located between the silicide and the buried insulation region. The heavily doped P-type region contacts to the silicide, the body region, the buried insulation layer and the shallow trench isolation (STI) structure respectively. The manufacturing method of the device comprises steps of forming a heavily doped P-type region via ion implantation method, forming a metal layer on a part of the surface of the source region, then obtaining a silicide by the heat treatment of the metal layer and the Si material below. The present invention utilizes the silicide and the heavily doped P-type region to form an ohmic contact in order to release the holes accumulated in the body region of SOI MOS device and eliminate SOI MOS floating body effects. Besides, the manufacturing process is simple and can be easily implement. Further, the manufacturing process according to the present invention will not increase chip area and is compatible with conventional CMOS process. | 05-10-2012 |
| 20120170746 | Method, Network Element, and Mobile Station for Negotiating Encryption Algorithms - A method, network element, and mobile station (MS) are disclosed. The method includes: obtaining information that a plug-in card of the MS does not support a first encryption algorithm; deleting the first encryption algorithm from an encryption algorithm list permitted by a core network element according to the information that the plug-in card of the MS does not support the first encryption algorithm; sending the encryption algorithm list excluding the first encryption algorithm to an access network element, so that the access network element selects an encryption algorithm according to the encryption algorithm list excluding the first encryption algorithm and the MS capability information sent from the MS and sends the selected encryption algorithm to the MS. By using the method, network element, and MS, errors due to the fact that the plug-in card of the MS does not support an encryption algorithm may be avoided during the encryption process. | 07-05-2012 |
| 20120182929 | METHOD, APPARATUS, AND SYSTEM FOR DATA TRANSMISSION - Embodiments of the present invention disclose a method, an apparatus, and a system for data transmission. The method for data transmission includes: determining that data to be transmitted is control plane signaling related to a user equipment that camps on a relay node; and transmitting the data through a first user data bearer established between the relay node and a donor base station, where the first user data bearer provides integrity protection for the data. According to the embodiments of the present invention, when the control plane signaling related to the user equipment that camps on the relay node is transmitted between the relay node and the donor base station, integrity protection is provided for the control plane signaling, and therefore attacks such as the denial of a service attack are prevented. | 07-19-2012 |
| 20120205743 | PD SOI DEVICE WITH A BODY CONTACT STRUCTURE - The present invention discloses a PD SOI device with a body contact structure. The active region of the PD SOI device includes: a body region; a gate region, which is inverted-L shaped, formed on the body region; a N-type source region and a N-type drain region, formed respectively at the two opposite sides of the anterior part the body region; a body contact region, formed at one side of the posterior part of the body region, which is side-by-side with the N-type source region; and a first silicide layer, formed on the body contact region and the N-type source region, which is contact to both of the body contact region and the N-type source region. The body contact region of the device is formed on the border of the source region and the leading-out terminal of the gate electrode. It can suppress floating body effect of the PD SOI device meanwhile not increasing the chip area, thereby overcoming the shortcoming in the prior art that the chip area is enlarged when the traditional body contact structure is employed. Furthermore, the fabrication process provided herein is simple and compatible to the CMOS technology. | 08-16-2012 |
| 20120212314 | POWER MODULE AND CIRCUIT BOARD ASSEMBLY THEREOF - A power module mounted on a system board comprises a printed circuit board having an extension part, at least one primary winding coil disposed on a first side of the extension part. The at least one primary winding coil is disposed at a primary side of the power module. The power module further comprises a PCB winding formed on the extension part at a secondary side of the power module, a first magnetic core assembly, and a connector. The first magnetic core assembly comprises a first magnetic part and a second magnetic part. The at least one primary winding coil and the extension part are enclosed between the first magnetic part and the second magnetic part. | 08-23-2012 |
| 20130011831 | Compositions And Methods For The Rapid Detection Of Legionella pneumophila - The present application describes compositions and methods useful for the rapid detection of | 01-10-2013 |
| 20130054209 | Modeling Method of SPICE Model Series of SOI FET - The present invention provides a modeling method of a SPICE model series of a Silicon On Insulator (SOI) Field Effect Transistor (FET), where auxiliary devices are designed and fabricated, electrical property data is measured, intermediate data is obtained, model parameters are extracted based on the intermediate data, a SPICE model of an SOI FET of a floating structure is established, model parameters are extracted by using the intermediate data and data of the auxiliary devices, a macro model is complied, and a SPICE model of an SOI FET of a body leading-out structure is established. The modeling method provided in the present invention takes an influence of a parasitic transistor of a leading-out part in a body leading-out structure into consideration, and model series established by using the method can more accurately reflect actual operating conditions and electrical properties of the SOI FET of a body leading-out structure and the SOI FET of a floating structure, thereby improving fitting effects of the models. | 02-28-2013 |
| 20130054210 | Method for Determining BSIMSOI4 DC Model Parameters - The present invention provides a method for determining BSIMSOI4 Direct Current (DC) model parameters, where a plurality of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices of a body leading-out structure and of different sizes, and a plurality of MOSFET devices of a floating structure and of different sizes are provided; Id-Vg-Vp, Id/Ip-Vd-Vg, Ig-Vg-Vd, Ig-Vp, Ip-Vg-vd, Is/Id-Vp, and Id/Ip-Vp-Vd properties of all the MOSFET devices of a body leading-out structure, and Id-Vg-Vp, Id-Vd-Vg, and Ig-Vg-Vd properties of all the MOSFET devices of a floating structure are measured; electrical property curves without a self-heating effect of each MOSFET device of a body leading-out structure and each MOSFET device of a floating structure are obtained; and then DC parameters of a BSIMSOI4 model are successively extracted according to specific steps. In the present invention, proper test curves are successively selected according to model equations, and various kinds of parameters are successively determined, thereby accurately and effectively extracting the DC parameters of the BSIMSOI4 model. | 02-28-2013 |
| 20130054219 | Equivalent Electrical Model of SOI FET of Body Leading-Out Structure, and Modeling Method Thereof - The present invention provides an equivalent electrical model of a Silicon On Insulator (SOI) Field Effect Transistor (FET) of a body leading-out structure, and a modeling method thereof. The equivalent electrical model is formed by an internal FET and an external FET connected in parallel, where the SOI FET of a body leading-out structure is divided into a body leading-out part and a main body part, the internal FET represents a parasitic transistor of the body leading-out part, and the external FET represents a normal transistor of the main body part. The equivalent electrical model provided in the present invention completely includes the influence of parts of a physical structure of the SOIMOSFET device of a body leading-out structure, that is, the body leading-out part and the main body part, on the electrical properties, thereby improving a fitting effect of the model on the electrical properties of the device. | 02-28-2013 |
| 20130152033 | TCAD Emulation Calibration Method of SOI Field Effect Transistor - The present invention provides a Technology Computer Aided Design (TCAD) emulation calibration method of a Silicon On Insulator (SOI) field effect transistor, where process emulation Metal Oxide Semiconductor (MOS) device structures with different channel lengths Lgate are obtained by establishing a TCAD process emulation program; based on the process emulation MOS device structures, the process emulation MOS device structures are calibrated according to a Transmission Electron Microscope (TEM) test result, a secondary ion mass spectrometer (SIMS) test result, a Capacitor Voltage (CV) test result, a WAT test result, and a square resistance test result of an actual device, so as to complete TCAD emulation calibration of key electrical parameters of an SOI field effect transistor. Through the calibration method consistent with the present invention, in the same SOI process, TCAD emulation results of key parameters Vt and Idsat of MOSFETs of different sizes all meet a high-precision requirement that an error is less than 10%; moreover, accurate and effective pretest can be implement in the case of multiple splits, thereby providing effective guidance for research, development and optimization of a new process flow. | 06-13-2013 |
| 20130236016 | METHOD, APPARATUS, AND SYSTEM FOR DATA PROTECTION ON INTERFACE IN COMMUNICATIONS SYSTEM - A method and an apparatus for protecting data carried on an Un interface between a eNB and a relay node are disclosed. Three types of radio bearers (RBs) are defined over the Un interface: signaling radio bearers (SRBs) for carrying control plane signaling data, signaling-data radio bearers (s-DRBs) for carrying control plane signaling date; and data-data radio bearers (d-DRBs) for carrying user plane data. An integrity protection algorithm and an encryption algorithm are negotiated for control plane signaling data on an SRB, control plane signaling data carried on an s-DRB, and user plane data carried on a d-DRB. With the respective integrity protection algorithm and encryption algorithm, the data over the Un interface can be protected respectively. Therefore, the security protection on the Un interface is more comprehensive, and the security protection requirements of data borne over different RBs can be met. | 09-12-2013 |
| 20130258907 | METHOD, DEVICE, AND SYSTEM FOR MANAGING QUALITY OF SERVICE - Embodiments of the present invention pertain to the communications field and disclose a method, device, and system for managing quality of service. The method includes: receiving a service request; determining, according to configuration information, devices participating in negotiation on quality of service; and determining, according to a negotiation result of the devices participating in negotiation on quality of service, quality of service corresponding to the service request. The device includes: a receiving module, a first determining module and a second determining module. In the embodiments of the present invention, devices participating in negotiation on quality of service are determined according to configuration information, and the corresponding quality of service is determined according to the negotiation result of the devices participating in negotiation on quality of service, thereby not being limited to the subscription result of the HLR, and implementing flexible management for quality of service. | 10-03-2013 |
| 20140053249 | METHOD, APPARATUS, AND SYSTEM FOR PREVENTING ABUSE OF AUTHENTICATION VECTOR - A method for preventing abuse of an Authentication Vector (AV) and a system and apparatus for implementing the method are provided. Access network information of a non-3rd Generation Partnership Project (3GPP) access network where a user resides is bound to an AV of the user, so that when the user accesses an Evolved Packet System (EPS) through the non-3GPP access network, even if an entity in the non-3GPP access network is breached, or an Evolved Packet Data Gateway (ePDG) connected to an untrusted non-3GPP access network is breached, the stolen AV cannot be applied to other non-3GPP access networks by an attacker. | 02-20-2014 |
| 20140068709 | METHOD AND APPARATUS FOR NEGOTIATING SECURITY DURING HANDOVER BETWEEN DIFFERENT RADIO ACCESS TECHNOLOGIES - Solution for security negotiation during handover of a user equipment (UE) between different radio access technologies are provided. In the solution, the UE receives NAS security information and AS security information which are selected by the target system and then performs security negotiation with the target system according to the received NAS security information and AS security information. As such, the UE may obtain the key parameter information of the NAS and AS selected by a LTE system and perform security negotiation with the LTE system when the UE hands over from a different system, such as a UTRAN, to the LTE system. | 03-06-2014 |
| 20140080449 | HANDOVER METHOD, BASE STATION, USER EQUIPMENT, AND MOBILITY MANAGEMENT ENTITY - Embodiments of the present invention provide a handover method, base station, user equipment, and mobility management entity. The handover method includes: obtaining an algorithm used by a user equipment in a universal mobile telecommunication system and four least significant bits of a downlink non-access stratum count; and sending a handover command to the user equipment, where the handover command carries the algorithm used by the user equipment in the universal mobile telecommunication system and the four least significant bits of the downlink non-access stratum count, so that the user equipment calculates a cipher key and an integrity key according to the four least significant bits of the downlink non-access stratum count. | 03-20-2014 |
| 20140133086 | ELECTRONIC DEVICE - An electronic device includes a motherboard, a plurality of heating modules arranged on the motherboard, a first electronic module arranged on a front side of the motherboard along a longitudinal direction, a second electronic module stacked above the first electronic module, a wind scooper and a fan module being located on a rear side of the motherboard along the transverse direction and facing the heating modules and the second electronic module. The wind scooper covers the heating modules, and has a partition board to form a lower-layer airflow passage and an upper-layer airflow passage. The wind scooper guides a first airflow from the fan module to flow through the heating modules along the lower-layer airflow passage, and guides a second airflow from the fan module to flow to the second electronic module through the upper-layer airflow passage, without flowing through the heating modules. | 05-15-2014 |
| 20140133087 | ELECTRONIC DEVICE - An electronic device includes a motherboard, a power module, a hard disk module, a fan module, a heating module and a power-supply wind scooper. The power module is arranged on a front side of the motherboard along a longitudinal direction, and has a power-supply opening. The hard disk module is stacked on the module. The fan module is located on a rear side of the motherboard along a transverse direction, and further provides airflows towards the power-supply opening of the power module. The heating module is arranged on the motherboard, and further located between the fan module and the power module. The power-supply wind scooper shields a part of the power-supply opening, so as to respectively guide parts of the airflow into the power module and the heating module. | 05-15-2014 |
| 20140133090 | ELECTRONIC DEVICE - An electronic device includes a motherboard, at least one heat dissipation module, a fan module and a wind scooper. The heat dissipation module is arranged on the motherboard and provided with a first positioning component. The fan module is arranged on one side of the motherboard and faces the heat dissipation module. The wind scooper has a second positioning component corresponding to the first positioning component. The wind scooper is fixed on the heat dissipation module through the cooperation between the first positioning component and the second positioning component. The wind scooper is connected between the fan module and the heat dissipation modules, so that the airflow provided by the fan module can flow through the heat dissipation module. | 05-15-2014 |
| 20140233735 | ENCRYPTION METHOD, DECRYPTION METHOD, AND RELATED APPARATUS - Embodiments of the present application provide an encryption method, a decryption method, and a related apparatus. The encryption method includes: generating a keystream, where the keystream is used to encrypt a part of data to be encrypted in an initial layer-3 message, and the part of data to be encrypted includes small data; generating, by performing an exclusive OR operation on the keystream and the initial layer-3 message, an initial layer-3 message in which the part of data is encrypted; and sending the initial layer-3 message in which the part of data is encrypted, where the initial layer-3 message includes an added encryption indication, and the encryption indication is used to indicate that the part of data to be encrypted in the initial layer-3 message is encrypted. | 08-21-2014 |
| 20140233736 | METHOD AND RELATED DEVICE FOR GENERATING GROUP KEY - Embodiments of the present invention provide a method and a related device for generating a group key. The method includes: obtaining a group ID of a group where a machine type communication MTC device is located; obtaining a group communication root key corresponding to the group ID; generating a group key corresponding to the group ID according to the group communication root key; and sending the group key encrypted by using an access stratum key of the MTC device to the MTC device, so that the MTC device obtains the group key through decryption according to the access stratum key of the MTC device. According to the foregoing technical solutions, a base station may allocate, to an MTC device, a group key corresponding to a group where the MTC device is located. | 08-21-2014 |
| 20140237559 | METHOD AND RELATED DEVICE FOR GENERATING GROUP KEY - A method and a related device for generating a group key are provided. A group ID of a group to which an MTC device belongs and a group communication root key related to a security key are received from an MME, where the security key is corresponding to the group ID; a group key corresponding to the group ID is generated according to the group communication root key; and a generating parameter used to generate the group key is sent to the MTC device, so that the MTC device generates the group key according to the group key generating parameter and a security key saved in the MTC device. Therefore, a base station only needs to maintain a same group key for a same group, thereby reducing the operation complexity of the base station. | 08-21-2014 |
| 20140310523 | METHOD, APPARATUS AND SYSTEM FOR SECURE COMMUNICATION OF LOW-COST TERMINAL - Embodiments of the present invention provide a method for secure communication of a low-cost terminal, which solves a communication security problem in the low-cost terminal and on a network side. The method includes: selecting, by an access point, a ciphering algorithm and an integrity algorithm according to a security capability of the low-cost terminal after successful authentication and key negotiation between the low cost terminal and a mobility management entity, and acquiring a cipher key and an integrity key according to the ciphering algorithm and the integrity algorithm; sending, by the access point, a security mode command including the ciphering algorithm and the integrity algorithm to the low-cost terminal so that the low-cost terminal calculates the cipher key and the integrity key; and receiving, by the access point, a security mode complete response message sent by the low-cost terminal. Embodiments of the present invention apply to radio communication. | 10-16-2014 |
| 20140317688 | METHOD AND DEVICE FOR GENERATING ACCESS STRATUM KEY IN COMMUNICATIONS SYSTEM - In the communications system, a user equipment UE accesses a core network via a first network-side device by using a first air interface and connects to the first network-side device via a second network-side device by using a second air interface to access the core network. The method includes: acquiring, by the network-side device, an input parameter; calculating, by the network-side device, an access stratum root key KeNB* according to the input parameter and an access stratum root key KeNB on the first air interface, or using, by the network-side device, the KeNB as the KeNB*; and generating, by the second network-side device, an access stratum key on the second air interface according to the KeNB*, or sending, by the first network-side device, the KeNB* to the second network-side device. | 10-23-2014 |
| 20140341987 | COLOUR CHANGING COMPOSITION IN O/W EMULSION FORM - A changing colour composition for caring for and/or making up keratin materials on the form of an O/W emulsion comprising, in a physiologically acceptable medium, at least a) microcapsules containing releasable colorant(s), said microcapsules comprising: —a core comprising one organic material, —at least one layered coating surrounding said core, the layered coating comprising at least one polymer, at least one colorant, and advantageously at least one lipid-based material, b) at least 5% by weight, more preferably at least 8% by weight and advantageously at least 10% by weight relative to the weight of the composition of an aqueous phase comprising water and at least one compound chosen from polyols, glycols C2-C8 monoalcohols and mixtures thereof, c) non entrapped Ti0 | 11-20-2014 |
| 20140355762 | METHOD, APPARATUS, AND SYSTEM FOR ESTABLISHING SECURITY CONTEXT - Embodiments of the present invention discloses a method, an apparatus, and a system for establishing a security context and relates to the communications field, so as to comprehensively protect UE data. The method includes: acquiring an encryption algorithm of an access node; acquiring a root key and deriving, according to the root key and the encryption algorithm, an encryption key of the access node; sending the encryption key and the encryption algorithm to the access node, so that the access node starts downlink encryption and uplink decryption; sending the encryption algorithm of the access node to the UE so as to negotiate the encryption algorithm with the UE; and instructing the access node to start downlink encryption and uplink decryption and instructing, during algorithm negotiation, the UE to start downlink decryption and uplink encryption. The present invention mainly applies to SCC security protection. | 12-04-2014 |
| 20140356403 | COLOUR CHANGING COMPOSITION IN GEL FORM - A changing colour composition in the form of a gel for caring for and/or making up keratin materials is disclosed. The composition comprises in a physiologically acceptable medium, a) from 0.1 to 10% by weight preferably from 0.5 to 10% more preferably from 1 to 5% by weight relative to the weight of the composition of microcapsules containing releasable colorant(s), said microcapsules comprising:—a core comprising one organic material,—at least one layered coating surrounding said core, the layered coating comprising at least one polymer at least one colorant, and advantageously at least one lipid-based material, b) at least 3% by weight, preferably at least 5% by weight, more preferably at least 8% by weight and advantageously at least 10% by weight relative to the weight of the composition of an aqueous phase comprising water and at least one compound chosen from polyols, glycols and C2-C8 monoalcohols, and mixtures thereof, and c) at least one hydrophilic gelifying agent. | 12-04-2014 |
| 20140357262 | METHOD AND APPARATUS FOR SECURE PROCESSING OF SHORT MESSAGE - The present invention discloses a method and apparatus for secure processing of a short message, and relates to the field of wireless communications technologies. The method includes: receiving, by a second device, identifier information sent by a first device; sending a rejection indication or a query result to the first device if the second device determines, according to the identifier information, that a receiver is a machine type communication MTC device or determines that the identifier information is not in an authorization list; or sending an acknowledgement indication or a query result to the first device if the second device determines, according to the identifier information, that a receiver is another device other than an MTC device or determines that the identifier information is in an authorization list. Embodiments of the present invention are mainly applied to a secure processing procedure of a short message. | 12-04-2014 |
| 20150038186 | MTC Device Communication Method, Device, and System - Embodiments of the present invention provide an MTC device communication method, device, and system. A second network element receives, a query message sent by a first network element after the first network element identifies that a type of a received short message is a preset-type short message. The query message comprises an identifier of a receiver of the short message and an identifier of a sender of the short message. The second network element checks whether the sender is authorized to send the preset-type short message to the receiver. The second network element sends a message to the first network element indicating whether or not to send the short message to the receiver. | 02-05-2015 |
| 20150043537 | SECURITY PROCESSING METHOD AND SYSTEM IN NETWORK HANDOVER PROCESS - Embodiments of the present invention disclose a security processing method and system in a network handover process. The method includes: generating, by a network switching node, a target key after receiving a handover request; sending, by the network switching node, security information including the target key to a target network node, and receiving a handover response message sent by the target network node; and sending, by the network switching node, a handover command to a mobile terminal, so that the mobile terminal accesses a target network. By adopting the present invention, security processing in handover of a mobile terminal from a 3G network to an HSPA network or an LTE network may be completed in a case that the network switching node currently used in the network is not changed. | 02-12-2015 |
| 20150085828 | METHOD FOR OBTAINING SERVING GATEWAY, MOBILITY MANAGEMENT NODE, DATA GATEWAY, AND SYSTEM - The present invention provides a method for obtaining a serving gateway, a mobility management node, a data gateway, and a system. A method for obtaining a serving gateway according to an embodiment of the present invention includes: when a UE is switched from an old-side mobility management node to a new-side mobility management node, sending, by the new-side mobility management node, a domain name resolution request to a domain name system DNS server according to access information of the UE; receiving a hostname of a device returned, according to the domain name resolution request, by the DNS server; obtaining a hostname of a new-side available S-GW; and selecting the new-side available S-GW closest to the device on geographic topology as a new-side S-GW. User service data transmission time delay can be reduced through the method. | 03-26-2015 |
