Patent application number | Description | Published |
20090146238 | CMOS-BASED PLANAR TYPE SILICON AVALANCHE PHOTO DIODE USING SILICON EPITAXIAL LAYER AND METHOD OF MANUFACTURING THE SAME - A complementary metal-oxide semiconductor (CMOS)-based planar type avalanche photo diode (APD) using a silicon epitaxial layer and a method of manufacturing the APD, the photo diode including: a substrate; a well layer of a first conductivity type formed in the substrate; an avalanche embedded junction formed in the well layer of the first conductivity type by low energy ion implantation; the silicon epitaxial layer formed in the avalanche embedded junction; a doping area of a second conductivity type opposite to the first conductive type, formed from a portion of a surface of the well layer of the first conductivity type in the avalanche embedded junction and forming a p-n junction; positive and negative electrodes formed on the doping area of the second conductivity type and the well layer of the first conductivity type separated from the doping area of the second conductivity type, respectively; and an oxide layer formed on an overall surface excluding a window where the positive and negative electrodes are formed. | 06-11-2009 |
20090321641 | BIPOLAR JUNCTION TRANSISTOR-BASED UNCOOLED INFRARED SENSOR AND MANUFACTURING METHOD THEREOF - A BJT (bipolar junction transistor)-based uncooled IR sensor and a manufacturing method thereof are provided. The BJT-based uncooled IR sensor includes: a substrate; at least one BJT which is formed to be floated apart from the substrate; and a heat absorption layer which is formed on an upper surface of the at least one BJT, wherein the BJT changes an output value according heat absorbed through the heat absorption layer. Accordingly, it is possible to provide a BJT-based uncooled IR sensor capable of being implemented through a CMOS compatible process and obtaining more excellent temperature change detection characteristics. | 12-31-2009 |
20110084322 | CMOS IMAGE SENSOR AND MANUFACTURING METHOD THEREOF - Disclosed is a CMOS image sensor and a manufacturing method thereof. According to an aspect of the present invention, each pixel of CMOS image sensor includes a photo detector that includes an electon Collection layer doped with a concentration of 5×10 | 04-14-2011 |
20110084603 | INORGANIC ELECTROLUMINESCENT DEVICE AND MANUFACTURING METHOD THEREOF - An inorganic electroluminescent device includes: patterned metal electrodes periodically disposed at pre-set intervals; and a phosphor layer positioned on the patterned metal electrodes, wherein as a first voltage and a second voltage are alternately applied to the patterned metal electrodes according to the order of their disposition, light emitted from the phosphor layer is discharged to the spaces between the patterned metal electrodes. | 04-14-2011 |
20110147787 | ORGANIC LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - An organic light emitting diode (OLED) and a method for manufacturing the same are provided. In the OLED, patterned metal electrodes are positioned on one or more of upper and lower portions of a light emission layer to allow light generated from the light emission layer to emit to an area between the patterned metal electrodes. | 06-23-2011 |
20110147938 | CONDUCTIVE VIA HOLE AND METHOD FOR FORMING CONDUCTIVE VIA HOLE - Provided is a technology for forming a conductive via hole to implement a three dimensional stacked structure of an integrated circuit. A method for forming a conductive via hole according to an embodiment of the present invention comprises: filling inside of a via hole structure that is formed in one or more of an upper portion and a lower portion of a substrate with silver by using a reduction and precipitation of silver in order to connect a plurality of stacked substrates by a conductor; filling a portion that is not filled with silver inside of the via hole structure by flowing silver thereinto; and sublimating residual material of silver oxide series, which is generated during the flowing, on an upper layer inside of the via hole structure filled with silver. | 06-23-2011 |
20130279268 | EEPROM CELL WITH STORAGE CAPACITOR - In an EEPROM cell, as a storage capacitor is added between a control plate and a tunneling plate, after the storage capacitor is charged for a time that is relatively smaller than a time necessary for writing or erasing data of the EEPROM cell, the EEPROM cell that can perform operation of writing or erasing data of the EEPROM cell using a charge voltage that is stored at the storage capacitor is provided. Therefore, operation of writing or erasing data of the EEPROM cell within a short time using the EEPROM cell can be performed, and thus entire productivity of the EEPROM can be improved. | 10-24-2013 |
20130286740 | EEPROM CELL WITH TRANSFER GATE - An EEPROM cell including a transfer gate that can suppress a data disturbance phenomenon of the EEPROM cell is provided. The EEPROM cell includes: an inverter; a control plate; a tunneling plate; a data output metal oxide semiconductor field effect transistor (MOSFET) that is connected to the inverter; a floating plate that is connected to the inverter; a tunneling capacitor area that is formed between the floating plate and the tunneling plate; and a transfer gate that is connected to the tunneling plate. As the transfer gate is added between a bit line and the tunneling plate of the EEPROM cell, in a standby (or unselected) operation of the EEPROM cell, the tunneling plate is floated. | 10-31-2013 |
20140159875 | TERMINAL AND OPERATION CONTROL METHOD THEREOF - A terminal and an operation control method thereof are disclosed. A terminal performs an authentication procedure upon receiving a tag device's information from the tag device. If the tag device is identified as a registered tag device in the authentication procedure, initial data corresponding to a function to control the terminal even in a power-saving mode or a lock mode is received from the tag device, and the function corresponding to the initial data is performed. | 06-12-2014 |
20140192597 | CIRCUIT FOR CONTROLLING EEPROM CELL - An EEPROM cell control circuit is provided which includes a signal input circuit configured to receive control signals for controlling an EEPROM cell from an external device; a bit line control circuit configured to provide a positive voltage and a negative voltage to two bit lines connected with the EEPROM cell in response to the control signals; and a word line control circuit configured to control a sense gate line in response to the control signals at a sense operation and to apply a positive voltage and a negative voltage to a word line. | 07-10-2014 |
20140192600 | EEPROM CELL AND EEPROM DEVICE - An EEPROM cell is provided which includes a control gate; a tunneling plate; a floating plate configured to form a capacitor area with the control plate and the tunneling plate; an inverter configured to sense a voltage level of the floating plate; a first transfer gate connected with the tunneling plate and configured to transfer an operating voltage selectively applied from first and second bit lines to the tunneling plate; a protection circuit connected with the inverter and configured to float the inverter at non-read or write/erase operations of an adjacent EEPROM cell; and a second transfer gate configured to transfer an output voltage of the inverter. This configuration is enable to use all the same gate oxide (i.e. 26 Å) and ultra low operation voltages (i.e. ±2V) in EEPROM cell. | 07-10-2014 |
Patent application number | Description | Published |
20110296131 | NONVOLATILE MEMORY SYSTEM AND THE OPERATION METHOD THEREOF - A memory controller includes a microprocessor, a queue configured to store a plurality of first commands provided by the microprocessor, a queue management block configured to interpret and control said plurality of first commands, and a command generator configured to provide a plurality of second commands under control of the queue management block. The queue management block may simultaneously perform the plurality of second commands so as to simultaneously access a plurality of non-volatile memory units. | 12-01-2011 |
20120221771 | DATA STORAGE SYSTEM AND DATA MAPPING METHOD OF THE SAME - A data mapping method is performed by a memory controller in a data storage system configured to control a nonvolatile memory device having a plurality of channels, where each channel includes a plurality of nonvolatile memories. The data mapping method includes selecting channels of the plurality of channels to be active channels to which data input from a host are written in response to a request from the host, including nonvolatile memories corresponding to each of the active channels in a candidate zone list as active zones, and sequentially writing the data input from the host to the active zones included in the candidate zone list. | 08-30-2012 |
20130159815 | ADAPTIVE COPY-BACK METHOD AND STORAGE DEVICE USING SAME - During a garbage collection process for a non-volatile memory device of a storage device, an adaptive copy-back method selectively performs either an external or an internal copy-back operation in view of certain performance conditions for a storage device. The external copy-back operation is performed when a number of error-corrected bits per unit size of read data exceeds a given threshold value, and the internal copy-back operation is performed when the number of error-corrected bits does not exceed the threshold value. | 06-20-2013 |
20130166825 | Method Of Controlling Non-Volatile Memory, Non-Volatile Memory Controller Therefor, And Memory System Including The Same - A method of controlling a non-volatile memory device having multiple planes including receiving write requests from a host, the write requests each including a logical address, a write command, and a data set; storing the data sets at an address of a buffer; storing the buffer address in a mapping table that maps addresses of the buffer to the multiple planes; sequentially transmitting the data sets stored at respective buffer addresses to page buffers, respectively, of the planes corresponding to the buffer addresses according to the mapping table; and programming in parallel at least two data sets stored in respective page buffers to memory cells of the non-volatile memory device. | 06-27-2013 |
20130185483 | DATA STORAGE SYSTEM, MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, AND METHOD OF OPERATING THE SAME - A nonvolatile memory device includes: first through m-th word lines arranged sequentially and first through m-th pages connected respectively to the first through m-th word lines; a redundant array of inexpensive disks (RAID) controller generating first RAID parity data from first through (m−1)-th data; and an access controller connected to the RAID controller and capable of accessing the nonvolatile memory device, wherein the access controller programs the first through (m−1)-th data to the first through (m−1)-th pages and programs the first RAID parity data to the m-th page. | 07-18-2013 |
20130227213 | MEMORY CONTROLLER AND OPERATION METHOD THEREOF - A memory controller and an operation method thereof are provided. The operation method includes storing a plurality of random sequences, selecting at least one random sequence among the plurality of random sequences according to a data pattern of a data block, and performing conversion by at least one of randomizing the data block using the selected at least one random sequence and derandomizing the randomized data block using the selected at least one random sequence. | 08-29-2013 |
Patent application number | Description | Published |
20120162763 | IMAGE DISPLAY DEVICE - A image display device includes a display panel including a display area and a non-display area, wherein the display area includes left-eye horizontal pixel lines displaying a left-eye image and right-eye horizontal pixel lines displaying a right-eye image; a polarizing film disposed over the display panel, wherein the polarizing film linearly polarizes the left-eye image and the right-eye image; a patterned retarder disposed over the polarizing film and including left-eye retarders and right-eye retarders, wherein the left-eye retarders correspond to the left-eye horizontal pixel lines and change the linearly polarized left-eye image into left-circularly polarized image, and the right-eye retarders correspond to the right-eye horizontal pixel lines and change the linearly polarized image into right-circularly polarized image; and a lenticular lens film disposed over the polarizing film and including lenticular lenses, wherein the lenticular lenses correspond to the left-eye retarders and the right-eye retarders, respectively. | 06-28-2012 |
20120287504 | IMAGE DISPLAY DEVICE - An image display device includes a display panel including left-eye horizontal pixel lines displaying a left-eye image and right-eye horizontal pixel lines displaying a right-eye image; a polarizing film disposed over the display panel and linearly polarizing the left-eye image and the right-eye image; a patterned retarder disposed over the polarizing film and including left-eye retarders and right-eye retarders; and a lenticular lens film disposed over the polarizing film and including lenticular lenses, wherein the lenticular lenses correspond to the left-eye retarders and the right-eye retarders, respectively, wherein the lenticular lenses are spaced part from each other. | 11-15-2012 |
20130342771 | PATTERNED RETARDER TYPE STEREOSCOPIC IMAGE DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A stereoscopic image display device includes a first substrate defining an active area and a non-active area surrounding the active area, the first substrate having a gate line formed at the active area and the non-active area, a gate pad formed at the non-active area, a dummy line defining a dummy pixel by crossing the gate line, and a light leakage blocking layer that is connected to the dummy line and disposed to overlap the gate line and the gate pad; a second substrate opposing the first substrate, the second substrate having a black stripe on a side of the second substrate opposite from the first substrate along portions corresponding to edges of the active area, and a patterned retardation film over the black stripe; and a liquid crystal layer disposed between the first and second substrates. | 12-26-2013 |