Patent application number | Description | Published |
20080211405 | PLASMA DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A plasma display panel and a manufacturing method thereof are disclosed. The panel includes a substrate having a plurality of discharge cells, and barrier ribs defining the discharge cells, the barrier ribs contain carbon in an amount of 0.1 to 10% by weight. | 09-04-2008 |
20090068277 | PHARMACEUTICAL COMPOSITION COMPRISING LIPASE INHIBITOR AND LIPOPHILIC OIL ABSORBENT AND ORAL FORMULATION PREPARED THEREFROM - This invention provides a pharmaceutical composition comprising a lipase inhibitor; a lipophilic oil absorbent selected from the group consisting of hydrogenated castor oil, hydrogenated vegetable oil, glyceryl behenate, glyceryl palmitostearate and a mixture thereof; and a pharmaceutically acceptable additive, an oral formulation of a lipase inhibitor prepared there from and a method for preparing said formulation. The formulation of the present invention can minimize side effects such as oily spotting, fatty/oily stool, abdominal distension and flatus, and thus it can be advantageously used for preventing or treating obesity and hyperlipaemia. | 03-12-2009 |
20090137684 | SUSTAINED-RELEASE PREPARATIONS AND METHOD FOR PRODUCING THE SAME - The present invention relates to sustained-release preparations prepared by double granulation and methods for producing the same. The sustained-release preparations according to the present invention enables maintenance of effective blood concentration of drug for many hours via sustained release of the drug over 12 hours or more, and further its production is easy owing to convenience of process. | 05-28-2009 |
20090145654 | ELECTROMAGNETIC SHIELDING SHEET, PLASMA DISPLAY APPARATUS USING THE SAME, AND RELATED TECHNOLOGY - There are provided an electromagnetic shielding sheet and a plasma display apparatus. The electromagnetic shielding sheet includes a base sheet; a first layer on a first surface of the base sheet, the first layer including first and second patterns crossing each other; and a second layer on a second surface of the base sheet, the second layer including a third pattern. The first and second patterns include a conductive material, the third pattern includes a light absorbing material, and at least one of the first and second patterns is grounded. Accordingly, conductive patterns for shielding electromagnetic waves and blocking external light are formed on a first surface of a base sheet, and patterns for blocking external light are formed on a second surface of the base sheet, so that the functions of shielding electromagnetic waves and blocking external light can be simultaneously performed using one sheet, and therefore, the ambient contrast ratio of a display image can be enhanced without increasing manufacturing costs. Further, patterns for shielding electromagnetic waves are directly formed a glass member of a filter or an upper substrate of the panel, so that processes of forming an electromagnetic shielding sheet can be easily performed. | 06-11-2009 |
20100210068 | Method of forming phase change memory device - Provided is a method of forming a phase change memory device, the method including washing and rinsing a phase change device structure. A phase change material layer may be formed on a semiconductor substrate. The phase change material layer may be etched so as to form a phase change device structure. The semiconductor substrate on which the phase change device structure is formed may be washed using a washing solution including a reducing agent containing fluorine (F), a pH controller, a dissolution agent and water. In addition, the semiconductor substrate on which the washing is performed may be rinsed. | 08-19-2010 |
20100304530 | METHOD OF FORMING A SEMICONDUCTOR DEVICE PACKAGE - Provided is a method of forming a semiconductor package. In the method, a first package including a first chip on a first substrate is formed, a second package including a second chip on a second substrate is formed, a moulding cap provided with a via hole and a recess structure configured to receive the first chip is formed, and the second package is provided on the first package with the moulding cap being therebetween such that the recess receives the first chip. The via hole and the recess structure are simultaneously foamed. | 12-02-2010 |
20100317759 | ADHESIVE SHEET AND METHOD FOR MANUFACTURING SAME - Disclosed is a method for manufacturing an adhesive sheet, including the steps of: (i) forming polymer syrup using monomer for adhesive polymer resin; (ii) injecting gas into the polymer syrup to form bubbles; (iii) forming an adhesive mixture by adding a conductive filler to the polymer syrup having the bubbles and mixing the conductive filler with the polymer syrup; (iv) manufacturing the mixture in a form of a sheet; and (v) irradiating light onto at least two surfaces of the sheet to photopolymerize the adhesive mixture. Gas is injected into polymer syrup before the conductive filler is added to the polymer syrup to form bubbles, thereby obtaining an adhesive sheet capable of shielding and/or absorbing an electromagnetic radiation with dimensional stability and adhesive force superior to that of comparative adhesive sheets. | 12-16-2010 |
20110018121 | Semiconductor packages and methods of fabricating the same - A semiconductor package may include a substrate having first and second surfaces, the second surface including a recessed portion, a first semiconductor chip mounted on the first surface, a first ball land outside the recessed portion, a connection pad inside the recessed portion, a second chip in the recessed portion, the second semiconductor chip including a through via electrically connected to the connection pad, and a second ball land electrically connected to the through via. A semiconductor package may include a substrate having first and second surfaces, the second surface including a recessed portion, a first semiconductor chip mounted on the first surface, a first ball land outside the recessed portion, a connection pad inside the recessed portion, a second semiconductor chip in the recessed portion, the second chip including a through via electrically connected to the connection pad, and a second ball land electrically connected to the through via. | 01-27-2011 |
20110078568 | MOBILE TERMINAL AND METHOD FOR CONTROLLING THE SAME - A mobile terminal and a method for controlling the same are disclosed, where symbols used often when inputting characters and pointer position moving are input simultaneously by using a touch gesture of a user, such that character input may be accelerated. | 03-31-2011 |
20110106707 | RECHARGE AMOUNT TRANSFER SYSTEM AND METHOD FOR ELECTRONIC PAYMENT MEANS USING PORTABLE PHONE - The present invention relates to a recharge amount transfer system for an electronic payment means using a portable phone. The present invention comprises: a first user terminal that indexes a recharge balance stored in a first electronic settlement payment means according to recharge amount transfer request information input by a first user, transmits a generated recharge amount transfer request SMS if the amount to be transferred is less than the recharge balance, receives a first recharge amount transfer completion SMS, and updates the recharge balance stored in the first electronic settlement payment means; a recharge server that indexes the first user information already stored according to the recharge amount transfer request SMS, generates and transmits a recharge amount transfer confirmation request SMS accordingly, receives a recharge amount transfer confirmation SMS, updates the first and second user information already stored in a recharge storage DB, and transmits the generated first and second recharge amount transfer completion SMS; and a second user terminal unit that receives the recharge amount transfer confirmation request SMS, generates and transmits a recharge amount transfer confirmation SMS according to the recharge amount transfer confirmation information input by a second user, receives the second recharge amount transfer completion SMS, and updates the recharge balance stored in a second electronic settlement payment means. | 05-05-2011 |
20110109000 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - Provided are a semiconductor package and a method of forming the same. The semiconductor package includes a stress reliever disposed on a part (more specifically, a weak part) of a semiconductor chip. The stress reliever relieves thermal and/or physical stresses caused by a molding layer. As a result, the semiconductor chip does not suffer from the thermal and/or physical stresses. | 05-12-2011 |
20110170582 | APPARATUS AND METHOD FOR DOWNCONVERTING RF MULTI-SIGNALS SIMULTANEOUSLY BY BANDPASS SAMPLING - The present invention relates to a method of down-converting RF multi-signals by bandpass sampling, which includes: setting up obtainable combinations of 2 spectrum signals extracted from 2N negative and positive spectrum signals existing for N RF signals; calculating available sampling ranges for the 2 spectrum signals in each obtainable combination; and determining an effective sampling range by the intersection of the available sampling ranges. | 07-14-2011 |
20110183681 | METHOD AND APPARATUS FOR THE MOBILITY MANAGEMENT OF A MOBILE TERMINAL BASED ON CELL-CLUSTER IN MOBILE COMMUNICATIONS NETWORKS - The present invention relates to a method and apparatus which is capable of managing movement of a mobile terminal in the unit of cell cluster in a mobile communication system. The method includes the steps of: forming cell clusters each including at least one cell including a base station communicating with the mobile terminal; determining a position of the mobile terminal; and if it is determined that the mobile terminal moves from one cell cluster to another cell cluster, changing location information of the mobile terminal. According to the present invention, it is possible to overcome a drawback of a conventional mobile communication system which is difficult to manage movement of a mobile terminal due to indistinctness or overlapping of cell or wireless communication areas, and thus achieve efficient and economical mobile terminal mobility management. | 07-28-2011 |
20110193228 | MOLDED UNDERFILL FLIP CHIP PACKAGE PREVENTING WARPAGE AND VOID - A molded underfill flip chip package may include a printed circuit board, a semiconductor chip mounted on the printed circuit board, and a sealant. The printed circuit board has at least one resin passage hole passing through the printed circuit board and at least one resin channel on a bottom surface of the printed circuit board, the at least one resin channel extending from the at least one resin passage hole passing through the printed circuit board. The sealant seals a top surface of the printed circuit board, the semiconductor chip, the at least one resin passage hole, and the at least one resin channel. | 08-11-2011 |
20110215444 | PACKAGE SUBSTRATES, SEMICONDUCTOR PACKAGES HAVING THE SAME, AND METHODS OF FABRICATING THE SEMICONDUCTOR PACKAGES - A package substrate, a semiconductor package having the same, and a method for fabricating the semiconductor package. The semiconductor package includes a semiconductor chip, a package substrate, and a molding layer. The package substrate provides a region mounted with the semiconductor chip. The molding layer is configured to mold the semiconductor chip. The package substrate includes a first opening portion that provides an open region connected electrically to the semiconductor chip and extends beyond sides of the semiconductor chip to be electrically connected to the semiconductor chip. | 09-08-2011 |
20110215451 | Stacked Semiconductor Packages - Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device. | 09-08-2011 |
20110233755 | Semiconductor Housing Package, Semiconductor Package Structure Including The Semiconductor Housing Package, And Processor-Based System Including The Semiconductor Package Structure - A semiconductor housing package may be provided. The semiconductor housing package may include a mold layer, a housing chip, a redistribution structure, and a housing node. The mold layer may surround and partially expose the housing chip. The redistribution structure may be electrically connected to the housing chip and may be disposed on the mold layer. The housing node may be in contact with the redistribution structures. The semiconductor housing package may be disposed on a semiconductor base package and may constitute a semiconductor package structure along with the semiconductor base package. The semiconductor package structure may be disposed on a processor-based system. | 09-29-2011 |
20110237027 | Method Of Forming Package-On-Package And Device Related Thereto - Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs. | 09-29-2011 |
20110291294 | Multi-Chip Package - A multi-chip package may include a first semiconductor package, a second semiconductor package and an interposer chip. The second semiconductor package may be arranged over the first semiconductor package. The interposer chip may be interposed between the first semiconductor package and the second semiconductor package. The interposer chip may have a receiving groove configured to receive the first semiconductor package. Thus, electrical connection reliability between the first semiconductor package and the second semiconductor package may be improved under a condition that the connecting terminals may have small sizes. | 12-01-2011 |
20120023166 | AUGMENTED REALITY APPARATUS AND METHOD - A terminal, server, system, and method for providing private tag information by the terminal accessible to the server through a wired/wireless communication network are provided. The method includes recognizing an object, detecting private tag information related to the recognized object, the private tag information including a sharing range, and outputting the detected private tag information. | 01-26-2012 |
20120091579 | Semiconductor Packages And Methods Of Fabricating The Same - A semiconductor package includes a wiring board including an upper connection pad provided on a first surface and a lower connection pad provided on a second surface opposite to the first surface, a semiconductor chip having a bonding pad area in which a bonding pad is provided and an adhesive area except the bonding pad area, and being mounted on the first surface of the wiring board in a flip-chip manner such that the bonding pad is electrically connected to the upper connection pad, a first molding layer provided between the adhesive area of the semiconductor chip and the first surface of the wiring board, and a second molding layer provided between the bonding pad area of the semiconductor chip and the first area of the wiring board while covering the first surface of the wiring board and the semiconductor chip. The first molding layer has a lower modulus than the second molding layer. | 04-19-2012 |
20130001800 | METHOD OF FORMING PACKAGE-ON-PACKAGE AND DEVICE RELATED THERETO - Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs. | 01-03-2013 |
20130147063 | METHODS OF FABRICATING FAN-OUT WAFER LEVEL PACKAGES AND PACKAGES FORMED BY THE METHODS - A fan-out wafer level package may include at least two semiconductor chips; an insulating layer covering portions of a first semiconductor chip; a mold layer covering portions of a second semiconductor chip; a redistribution line pattern in the insulating layer; and/or an external terminal on the insulating layer. The first semiconductor chip may be stacked relative to the second semiconductor chip. The redistribution line pattern may be electrically connected to the at least two semiconductor chips. The external terminal may be electrically connected to the redistribution line pattern. A fan-out wafer level package may include at least three semiconductor chips; an insulating layer covering portions of first semiconductor chips; a mold layer covering portions of a second semiconductor chip; a redistribution line pattern in the insulating layer; and/or an external terminal on the insulating layer. The first semiconductor chips may be stacked relative to the second semiconductor chip. | 06-13-2013 |
20130191146 | APPARATUS FOR EVALUATING RADIATION THERAPY PLAN AND METHOD THEREFOR - The present invention relates to an apparatus and to a method for comparing and evaluating therapy plan received from heterogeneous radiation therapy apparatuses. An apparatus according to an embodiment of the present invention includes a receiving means, a processing means, and a display means. The receiving means receives the patient's first radiation therapy plan data, which is generated by a first radiation therapy apparatus, and also receives the patient's second radiation therapy plan data, which is generated by a second radiation therapy apparatus. The processing means processes the first and second radiation therapy plan data to generate mixed data overlaid onto the medical image of the patient. According to a configuration of the present invention, trial and error during radiation treatment may be minimized. | 07-25-2013 |
20130274537 | APPARATUS AND METHOD FOR EVALUATING A RADIATION THERAPY PLAN - The present invention relates to an apparatus and method for evaluating the safety of RTP data. According to an embodiment of the present invention, the computer-implemented method for evaluating safety of RTP data comprises the steps of: receiving first RTP data about a first concerned area of a patient; receiving a second concerned area of the patient from a user; and calculating an amount of radiation for the second concerned area by using the first RTP data and a medical image of the patient. The evaluating method of the present invention may further comprise a step of evaluating the safety of the first RTP data by using information on the amount of radiation for the second concerned area. | 10-17-2013 |
20130288431 | PACKAGE SUBSTRATES, SEMICONDUCTOR PACKAGES HAVING THE SAME, AND METHODS OF FABRICATING THE SEMICONDUCTOR PACKAGES - A package substrate, a semiconductor package having the same, and a method for fabricating the semiconductor package. The semiconductor package includes a semiconductor chip, a package substrate, and a molding layer. The package substrate provides a region mounted with the semiconductor chip. The molding layer is configured to mold the semiconductor chip. The package substrate includes a first opening portion that provides an open region connected electrically to the semiconductor chip and extends beyond sides of the semiconductor chip to be electrically connected to the semiconductor chip. | 10-31-2013 |
20130295725 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - The inventive concept provides semiconductor packages and methods of forming the same. The semiconductor package includes a buffer layer covering at least one sidewall of the semiconductor chip. The buffer layer is covered by a molding layer. Thus, reliability of the semiconductor package may be improved. | 11-07-2013 |
20130330881 | DOUBLE-SIDED ADHESIVE TAPE, SEMICONDUCTOR PACKAGES, AND METHODS OF FABRICATING THE SAME - Provided are a double-sided adhesive tape, semiconductor packages, and methods of fabricating the packages. A method of fabricating semiconductor packages includes providing a double-sided adhesive tape on a top surface of a carrier, the double-sided adhesive tape including a first adhesive layer and a second adhesive layer stacked on the first adhesive layer, the first adhesive layer of the double-sided adhesive tape being in contact with the top surface of the carrier, adhering active surfaces of a plurality of semiconductor chips onto the second adhesive layer of the double-sided adhesive tape, separating the first adhesive layer from the second adhesive layer such that the second adhesive layer remains on the active surfaces of the semiconductor chips, patterning the second adhesive layer to form first openings that selectively expose the active surfaces of the semiconductor chips, and forming first conductive components on the second adhesive layer to fill the first openings. | 12-12-2013 |
20140008818 | METHOD AND APPARATUS FOR STACKED SEMICONDUCTOR CHIPS - Stacked semiconductor chips include a bonding-wire-free interconnection electrically connecting the semiconductor chips to each. An opening in an adhesion layer between the semiconductor chips may provide a path for the interconnection from a bonding pad on one semiconductor chip, along a sidewall insulation layer of the semiconductor chip, along a sidewall insulation layer of another semiconductor chip to a bonding pad on the other semiconductor chip. | 01-09-2014 |
20140070407 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - According to example embodiments, a semiconductor package includes: a lower molding element; a lower semiconductor chip in the lower molding element and having lower chip pads on an upper surface and at an areas close to first and second sides of the lower molding element; conductive pillars surrounding the lower semiconductor chip and passing through the lower molding element; an upper semiconductor chip on the upper surface of the lower molding element and lower semiconductor chip, the upper semiconductor chip having upper chip pads on a top surface and at areas close to third and the fourth sides of the upper semiconductor chip, and a connecting structure on the lower molding element and the upper semiconductor chip and electrically connecting each of the lower chip pads and upper chip pads to a corresponding conductive pillar. The upper semiconductor chip is substantially orthogonal to the lower semiconductor chip. | 03-13-2014 |
20140103523 | SEMICONDUCTOR PACKAGE - A semiconductor package including a lower semiconductor chip, and an upper semiconductor chip flip-chip bonded on the lower semiconductor chip may be provided. Each of the lower and upper semiconductor chips includes a first bonding pad formed on an active surface, which has a center line extending in a first direction, and a first rewire electrically connected to the first bonding pad, The first rewire includes first and second connection regions. The first and second connection regions face each other and are disposed at a same distance from the center line in a second direction, which is perpendicular to the first direction. | 04-17-2014 |
20140246786 | STACKED PACKAGES HAVING THROUGH HOLE VIAS - Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs. | 09-04-2014 |
20140256089 | STACKED SEMICONDUCTOR PACKAGES - Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device. | 09-11-2014 |
20150031170 | METHOD AND APPARATUS FOR STACKED SEMICONDUCTOR CHIPS - Stacked semiconductor chips include a bonding-wire-free interconnection electrically connecting the semiconductor chips to each. An opening in an adhesion layer between the semiconductor chips may provide a path for the interconnection from a bonding pad on one semiconductor chip, along a sidewall insulation layer of the semiconductor chip, along a sidewall insulation layer of another semiconductor chip to a bonding pad on the other semiconductor chip. | 01-29-2015 |
20150042697 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF ADJUSTING LUMINANCE OF THE SAME - A method of adjusting luminance of an organic light emitting display device is provided. By the method, initial compensation data are derived from optical images of a plurality of pixels, a look-up table (LUT) is generated using the initial compensation data, compensation data are derived by measuring deterioration degrees of the pixels, the LUT is updated by applying a filter for redistributing the compensation data among the pixels, an operation for adjusting the luminance are performed with image data of the pixels and the compensation data stored in the LUT, and driving data that are calculated by the operation for adjusting the luminance are outputted. | 02-12-2015 |
20150048501 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate including a lower plate and an upper plate, a semiconductor chip mounted on a top surface of the substrate, and a mold layer surrounding a sidewall and a bottom surface of the semiconductor chip. The substrate has a mold path including an inner path extending between the lower and upper plates and a mold hole penetrating the upper plate. The mold hole is connected to the inner path. The mold layer extends into the mold path. | 02-19-2015 |