Patent application number | Description | Published |
20080244287 | Platform communication protocol - A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state. | 10-02-2008 |
20090077307 | DRAM selective self refresh - In some embodiments, an electronic apparatus comprises a communication interface, an input/output interface, a processor, and logic to collect, in the electronic apparatus, a first identifier associated with a first communication device and second identifier associated with a second communication device, logic to establish a communication connection between the electronic apparatus and the first communication device, and logic to initiate, in the electronic apparatus, a connection request for a communication connection between the first communication device and the second communication device. Other embodiments may be described. | 03-19-2009 |
20090083561 | Dynamic power management of dimms - In some embodiments, an electronic apparatus comprises a processor, at least one non-volatile memory module, and logic to activate a first DIMM while placing at least a second DIMM in a sleep mode, assign operating system memory to grow from a first location in a first DIMM device, assign application memory to grow from a second location in the first DIMM device, mark at least one DIMM boundary in the first DIMM device, generate a page fault when at least one of the operating system memory or the application memory crosses the DIMM boundary; and in response to the page fault, activate at least a second DIMM in the plurality of DIMMs in the electronic device. | 03-26-2009 |
20090089606 | Opportunistic initiation of data traffic - A method for trafficking data based at least in part on a power condition of a system resource. In one embodiment of the invention, a data trafficking device initiates data traffic in response to a detecting of an indication of the power condition. In another embodiment of the invention, the detected indication is independent of any data traffic of the data trafficking device. | 04-02-2009 |
20090172270 | DEVICE, SYSTEM, AND METHOD OF MEMORY ALLOCATION - Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System. | 07-02-2009 |
20100080218 | Protocol extensions in a display port compatible interface - Contents of extension packets of a DisplayPort specification are described that can permit a computer to control a target device. In one example, an extension packet controls the target device in at least one of power consumption, image rendering, and register updating. | 04-01-2010 |
20110047326 | DRAM SELECTIVE SELF REFRESH - In some embodiments, an electronic apparatus comprises a communication interface, an input/output interface, a processor, and logic to collect, in the electronic apparatus, a first identifier associated with a first communication device and second identifier associated with a second communication device, logic to establish a communication connection between the electronic apparatus and the first communication device, and logic to initiate, in the electronic apparatus, a connection request for a communication connection between the first communication device and the second communication device. Other embodiments may be described. | 02-24-2011 |
20110047395 | Platform Communication Protocol - A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state. | 02-24-2011 |
20110196998 | PROTOCOL EXTENSIONS IN A DISPLAY PORT COMPATIBLE INTERFACE - A computer can control a target device using a packet format described herein. In one example, an extension packet controls the target device in at least one of power consumption, image rendering, and register updating. | 08-11-2011 |
20120089772 | DEVICE, SYSTEM, AND METHOD OF MEMORY ALLOCATION - Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System. | 04-12-2012 |
20120117285 | PROTOCOL EXTENSIONS IN A DISPLAY PORT COMPATIBLE INTERFACE - A computer can control a target device using a packet format described herein. In one example, an extension packet controls the target device in at least one of power consumption, image rendering, and register updating. | 05-10-2012 |
20140115248 | DEVICE, SYSTEM, AND METHOD OF MEMORY ALLOCATION - Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System. | 04-24-2014 |