Patent application number | Description | Published |
20110010484 | OPTIMIZED PAGE PROGRAMMING ORDER FOR NON-VOLATILE MEMORY - During a programming data transfer process in a non-volatile storage system, recording units of data are transferred from a host to a memory device, such as a memory card. For each recording unit, pages of data are arranged in an order such that a page which takes longer to write to a memory array of the memory device is provided before a page which takes less time to write. Overall programming time for the recording unit is reduced since a greater degree of parallel processing occurs. While the page which takes longer to program is being programmed to the memory array, the page which takes less time to program is being transferred to the memory device. After programming is completed, the memory device signals the host to transfer a next recording unit. The pages of data may include lower, middle and upper pages. | 01-13-2011 |
20110099460 | Non-Volatile Memory And Method With Post-Write Read And Adaptive Re-Write To Manage Errors - Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. Input data is written and staged in the first portion before being copied to the second portion. An error management provides checking the quality of the copied data for excessive error bits. The copying and checking are repeated on a different location in the second portion until either a predetermined quality is satisfied or the number or repeats exceeds a predetermined limit. The error management is not started when a memory is new with little or no errors, but started after the memory has aged to a predetermined amount as determined by the number of erase/program cycling its has experienced. | 04-28-2011 |
20110149650 | Data Transfer Flows for On-Chip Folding - A memory system and methods of its operation are presented. The memory system includes a volatile buffer memory and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. When writing data to the non-volatile memory, the data is received from a host, stored in the buffer memory, transferred from the buffer memory to into read/write registers of the non-volatile memory circuit, and then written from the read/write registers to the first section of the non-volatile memory circuit using a binary write operation. Portions of the data and then subsequently folded from the first section of the non-volatile memory to the second section of the non-volatile memory, where a folding operation includes reading the portions of the data from multiple locations in the first section into the read/write registers and performing a multi-state programming operation of the potions of the data from the read/write registers into a location the second section of the non-volatile memory. The multi-state programming operations include a first phase and a second phase and one or more of the binary write operations are performed between the phases of the multi-state programming operations. | 06-23-2011 |
20110153911 | METHOD AND SYSTEM FOR ACHIEVING DIE PARALLELISM THROUGH BLOCK INTERLEAVING - A method and system for achieving die parallelism through block interleaving includes non-volatile memory having a multiple non-volatile memory dies, where each die has a cache storage area and a main storage area. A controller is configured to receive data and write sequentially addressed data to the cache storage area of a first die. The controller, after writing sequentially addressed data to the cache storage area of the first die equal to a block of the main storage area of the first die, writes additional data to a cache storage area of a next die until sequentially addressed data is written into the cache area of the next die equal to a block of the main storage area. The cache storage area may be copied to the main storage area on the first die while the cache storage area is written to on the next die. | 06-23-2011 |
20110153913 | Non-Volatile Memory with Multi-Gear Control Using On-Chip Folding of Data - A memory system and methods of its operation are presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. The memory system receives data from the host and performs a binary write operation of the received data to the first section of the non-volatile memory circuit. The memory system subsequently folds portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes reading the portions of the data from the first section rewriting it into the second section of the non-volatile memory using a multi-state programming operation. The controller determines to operate the memory system according to one of multiple modes. The modes include a first mode, where the binary write operations to the first section of the memory are interleaved with folding operations at a first rate, and a second mode, where the number of folding operations relative to the number of the binary write operations to the first section of the memory are performed at a higher than in the first mode. The memory system then operates according to determined mode. The memory system may also include a third mode, where folding operations are background operations executed when the memory system is not receiving data from the host. | 06-23-2011 |
20110271036 | PHASED NAND POWER-ON RESET - A method and system for phasing power-intensive operations is disclosed. A non-volatile storage device controller detects a power reset. The controller is in communication with non-volatile memories in the non-volatile storage device. In response to detecting a power reset, the controller determines a current consumption necessary to reset the non-volatile memories in the non-volatile storage device. The controller simultaneously resets all of the non-volatile memories when the determined current consumption is less than a current consumption threshold. If the determined current consumption is greater than the current consumption threshold, the controller resets a first subset of the plurality of non-volatile memories, and after a predetermined delay, resets a second subset of the non-volatile memories. Therefore, a power-intensive operation may be performed without exceeding a current consumption threshold by dividing the operation into a sequence of steps that do not exceed the threshold. | 11-03-2011 |
20120005405 | Pre-Emptive Garbage Collection of Memory Blocks - A method and system pre-emptively perform garbage collection operations of a forced amount on update blocks in a memory device. The amount of garbage collection needed by a certain data write is monitored and adjusted to match the forced amount if necessary. Update blocks may be selected on the basis of their recent usage or the amount of garbage collection required. Another method and system may store control information about update blocks in a temporary storage area so that a greater number of update blocks are utilized. The sequential write performance measured by the Speed Class test may be optimized by using this method and system. | 01-05-2012 |
20120281479 | Detection of Broken Word-Lines in Memory Arrays - Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. One example considers an “inter-word-line” comparison where the program loop counts of different word-lines are compared in order to determine whether a word-line may be defective. For example, the number of programming pulses needed for the cells along a word-line WLn is compared to the number needed for a preceding word-line, such as WLn or WL(n−1), to see whether it exceeds this earlier value by a threshold value. If the word-line requires an excessive number of pulses, relative the earlier word-line, to complete programming, it is treated as defective. | 11-08-2012 |
20120284574 | Non-Volatile Memory and Method Having Efficient On-Chip Block-Copying with Controlled Error Rate - A non-volatile memory chip having SLC blocks acting as a write cache for MLC blocks for high density storage requires constant copying or folding of SLC blocks into MLC blocks. To avoid the time-consuming toggling out and in of the pages of the entire SLC block for ECC checking by a controller chip, only a small sample is checked. An optimal read point for reading the memory cells in the sample of the SLC block is dynamically determined by trying different read points so that the data is read within an error budget. Once the optimal read point is determined, it is used to read the entire SLC block without further error checking. Then the SLC block can be copied (blind folded) to the MLC block with the confidence of being within the error budget. | 11-08-2012 |
20120311244 | Balanced Performance for On-Chip Folding of Non-Volatile Memories - A non-volatile memory system receives and stores host data. As the memory system receives host data, it initially writes the data in a binary format and then subsequently performs an on-chip folding operation on the data, storing the data in a multi-state format. The memory system interleaves the phases of the folding operations so that performance is made more uniform across allocation units, where the host stores data according to allocation units. The memory system also can perform the binary and subsequent on-chip folding operations on multiple memory planes in parallel, where the controller also balances the operations so that performance is made more uniform between planes with respect to allocation units as the data is received from the host. To further maintain performance, the memory system uses a free block list having a reserve portion that is only accessible for a specified set of commands. | 12-06-2012 |
20130128666 | Scrub Techniques for Use with Dynamic Read - The decision on whether to refresh or retire a memory block is based on the set of dynamic read values being used. In a memory system using a table of dynamic read values, the table is configured to include how to handle read error (retire, refresh) in addition to the read parameters for the different dynamic read cases. In a refinement, the read case number can used to prioritize blocks selected for refresh or retire. In cases where the read scrub is to be made more precise, multiple dynamic read cases can be applied. Further, which cases are applied can be intelligently selected. | 05-23-2013 |
20130166893 | AUXILIARY CARD INITIALIZATION ROUTINE - A memory system or flash card may be initialized from a protected block of flash memory as a backup process. If there is an error during regular card initialization and the firmware for the card cannot be loaded, the card may be inaccessible to a user. Booting with a protected block of memory may be used to load a different version of the firmware that can still initialize the card despite the error from loading the other firmware. | 06-27-2013 |
20130170301 | Wordline-to-Wordline Stress Configuration - A method and system for performing wordline-to-wordline stress routines on a storage device is disclosed. Stress routines may be performed to reduce state widening in multi-level memory cells in the storage device. However, data retention problems may result if the stress routines are performed too often. In order to perform the stress routines at the proper times, a stress control variable is used. The stress control variable may be indicative of age of the storage device (such as the number of erase cycles performed on a memory block in the storage device). The stress control variable is input to a look-up table (or other logical construct), with the output of the look-up table indicating whether to perform the wordline-to-wordline stress routine. In this way, the stress routines may be performed to reduce state widening while reducing the ill effects of data retention. | 07-04-2013 |
20130205066 | ENHANCED WRITE ABORT MANAGEMENT IN FLASH MEMORY - A memory system or flash card may include safe zone blocks where data is written in case of an error condition, such as a write abort. The system may utilize predetermined risk zones when selecting the data that is written to the safe zone blocks. For example, data written to a lower page may be one example of data that is a predetermined risk. Upon receiving a write command, the data that is written to a lower page may be written to a safe zone either in parallel or after the write operation. | 08-08-2013 |
20130219107 | WRITE ABORT RECOVERY THROUGH INTERMEDIATE STATE SHIFTING - A memory system or flash card may include a multi-level cell block with multiple states. Before the upper page is written, an intermediate state may be shifted to prevent or minimize overlapping of the states from the corresponding lower page. A write abort during the writing of the upper page will not result in a loss of data from the corresponding lower page. | 08-22-2013 |
20130346805 | FLASH MEMORY WITH TARGETED READ SCRUB ALGORITHM - A method and system have been described for counteracting and correcting for read disturb effects in blocks of flash memory. The method may include the step of a controller of the memory system performing a read scrub scan on only a portion of one targeted word line in a block at desired intervals. The controller may calculate whether a read scrub scan is necessary based on a probabilistic determination that is calculated in response to each received host read command. The controller may then place a block associated with the targeted word line into a refresh queue if a number of errors are detected in the targeted word line that meets or exceeds a predetermined threshold. The block refresh process may include copying the data from the block into a new block during a background operation. | 12-26-2013 |