Patent application number | Description | Published |
20080313442 | DEBUGGING TECHNIQUES FOR A PROGRAMMABLE INTEGRATED CIRCUIT - Techniques for debugging a programmable integrated circuit are described. Embodiments include steps of initiating instruction-cache-misses in the integrated circuit using a remote computer executing a test program; substituting, during an instruction-cache-miss event, instructions in the application program with test instructions provided by the test program; and debugging the integrated circuit based on analysis of its responses to the test instructions. In exemplary applications, such techniques are used for debugging graphics processors of wireless communication system-on-chip devices, among other programmable integrated circuit devices. | 12-18-2008 |
20090083497 | MULTI-MEDIA PROCESSOR CACHE WITH CAHE LINE LOCKING AND UNLOCKING - The disclosure relates to techniques for locking and unlocking cache lines in a cache included within a multi-media processor that performs read-modify-write functions using batch read and write requests for data stored in either an external memory or an embedded memory. The techniques may comprise receiving a read request in a batch of read requests for data included in a section of a cache line and setting a lock bit associated with the section in response to the read request. When the lock bit is set, additional read requests in the batch of read requests are unable to access data in that section of the cache line. The lock bit may be unset in response to a write request in a batch of write requests to update the data previously read out from that section of the cache line. | 03-26-2009 |
20090237401 | MULTI-STAGE TESSELLATION FOR GRAPHICS RENDERING - This disclosure describes a multi-stage tessellation technique for tessellating a curve during graphics rendering. In particular, a first tessellation stage tessellates the curve into a first set of line segments that each represents a portion of the curve. A second tessellation stage further tessellates the portion of the curve represented by each of the line segments of the first set into additional line segments that more finely represent the shape of the curve. In this manner, each portion of the curve that was represented by only one line segment after the first tessellation stage is represented by more than one line segment after the second tessellation stage. In some instances, more than two tessellation stages may be performed to tessellate the curve. | 09-24-2009 |
20100235578 | Cached Memory System and Cache Controller for Embedded Digital Signal Processor - A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core. | 09-16-2010 |
20120033742 | TWO-STAGE ENTROPY DECODING - The subject matter of this specification can be implemented in, among other things, a method of decoding video data that includes decoding compressed input video data using a first entropy coding technique to obtain first decoded data. The method further includes re-encoding the first decoded data using a second entropy coding technique that is different from the first entropy coding technique to obtain re-encoded data. The method further includes storing the re-encoded data in a storage device. The method further includes decoding the re-encoded data using the second entropy coding technique to obtain second decoded data. | 02-09-2012 |
20120235999 | STEREOSCOPIC CONVERSION FOR SHADER BASED GRAPHICS CONTENT - The example techniques of this disclosure are directed to generating a stereoscopic view from an application designed to generate a mono view. For example, the techniques may modify source code of a vertex shader to cause the modified vertex shader, when executed, to generate graphics content for the images of the stereoscopic view. As another example, the techniques may modify a command that defines a viewport for the mono view to commands that define the viewports for the images of the stereoscopic view. | 09-20-2012 |
20120236934 | SIGNALING OF MULTIVIEW VIDEO PLUS DEPTH CONTENT WITH A BLOCK-LEVEL 4-COMPONENT STRUCTURE - This disclosure describes techniques for coding 3D video block units. In one example, a video encoder is configured to receive one or more texture components from at least a portion of an image representing a view of three dimensional video data, receive a depth map component for at least the portion of the image, code a block unit indicative of pixels of the one or more texture components for a portion of the image and the depth map component. The coding comprises coding the depth map component relative to at least one of the texture components, and signalling an attribute of the depth map component relative to the one or more texture components. | 09-20-2012 |
20130077690 | Firmware-Based Multi-Threaded Video Decoding - Embodiments of the present disclosure provide electronic devices and methods for equipping a multi-threaded processor with firmware instructions to configure threads to perform dedicated functions to expedite decoding of video data. In a particular embodiment, an electronic device includes a multi-threaded processor and a memory. The memory includes firmware including instructions executable by the multi-threaded processor, without use of a dedicated hardware macroblock decoding module, to decode video data compliant with a VP | 03-28-2013 |
20130271565 | VIEW SYNTHESIS BASED ON ASYMMETRIC TEXTURE AND DEPTH RESOLUTIONS - An apparatus for processing video data includes a processor configured to associate, in a minimum processing unit (MPU), one pixel of a depth image of a reference picture with one or more pixels of a first chroma component of a texture image of the reference picture, associate, in the MPU, the one pixel of the depth image with one or more pixels of a second chroma component of the texture image, and associate, in the MPU, the one pixel of the depth image with a plurality of pixels of a luma component of the texture image. The number of the pixels of the luma component is different than the number of the one or more pixels of the first chroma component and the number of the one or more pixels of the second chroma component. | 10-17-2013 |