Jian-Hong
Jian-Hong Chen, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20080286682 | MATERIAL AND METHOD FOR PHOTOLITHOGRAPHY - A photosensitive material for use in semiconductor manufacture comprises a copolymer that includes a plurality of photoresist chains and a plurality of hydrophobic chains, each hydrophobic chain attached to the end of one of the photoresist chains. The copolymer in response to externally applied energy will self-assemble to a photoresist layer and a hydrophobic layer. | 11-20-2008 |
20090233238 | Double Patterning Strategy For Contact Hole and Trench in Photolithography - A method of lithography patterning includes forming a first resist pattern on a substrate, the first resist pattern including a plurality of openings therein on the substrate; forming a second resist pattern on the substrate and within the plurality of openings of the first resist pattern, the second resist pattern including at least one opening therein on the substrate; and removing the first resist pattern to uncover the substrate underlying the first resist pattern. | 09-17-2009 |
20100209852 | TRACK NOZZLE SYSTEM FOR SEMICONDUCTOR FABRICATION - The present disclosure provides a method for fabricating a semiconductor device using a track pipeline system. The method includes storing a plurality of chemicals in a plurality of storage units of the system, wherein each storage unit is operable to store one of the chemicals, mixing the chemicals into a mixture, and dispensing the mixture onto a wafer using a nozzle of the system. | 08-19-2010 |
20120009524 | MATERIAL AND METHOD FOR PHOTOLITHOGRAPHY - A photosensitive material for use in semiconductor manufacture comprises a copolymer that includes a plurality of photoresist chains and a plurality of hydrophobic chains, each hydrophobic chain attached to the end of one of the photoresist chains. The copolymer in response to externally applied energy will self-assemble to a photoresist layer and a hydrophobic layer. | 01-12-2012 |
20120034778 | Double Patterning Strategy for Contact Hole and Trench in Photolithography - A method of lithography patterning includes forming a first resist pattern on a substrate, the first resist pattern including a plurality of openings therein on the substrate; forming a second resist pattern on the substrate and within the plurality of openings of the first resist pattern, the second resist pattern including at least one opening therein on the substrate; and removing the first resist pattern to uncover the substrate underlying the first resist pattern. | 02-09-2012 |
Jian-Hong Chen, Puzih City TW
Patent application number | Description | Published |
---|---|---|
20090184081 | Temperature-sensing feeding bottle structure - A feeding bottle includes a body, a temperature sensing and measuring plate on a lateral wall portion of the body, and a plate-shaped warning device covered by the temperature sensing and measuring plate; the temperature sensing and measuring plate can change colors with temperature to indicate the temperature for the users such as the parents, nursing persons, and diners; the warning device can give a certain kind of sound effect according to the temperature so that the parents/nursing persons can easily make sure that the food contents of the feeding bottle isn't too hot before they feed little children/persons with disabilities; little children, the elderly, and persons with visual disabilities also can be directly warned by the warning sound effects given by the warning device if the temperature is too high. | 07-23-2009 |
Jian-Hong Chen, Dashu Township TW
Patent application number | Description | Published |
---|---|---|
20110214031 | ERROR CORRECTION DECODER, ERROR CORRECTION VALUE GENERATOR, AND ERROR CORRECTION SYSTEM - An error correction decoder includes a syndrome generator and an error correction value generator. The syndrome generator is operable to generate a plurality of syndromes based upon a received signal generated according to a generator polynomial. The error correction value generator is operable to generate a plurality of product values. Each of the product values is generated for one of the syndromes based upon a respective power of the roots of the generator polynomial. The respective power is determined based upon a respective index corresponding to one of the syndromes to be considered and unit positions of the received signal. The error correction value generator is further operable to generate an error correction value according to the product values, and to provide an error correcting device coupled thereto with the error correction value for correcting an error of the received signal. | 09-01-2011 |
Jian-Hong Chen, Taipei TW
Patent application number | Description | Published |
---|---|---|
20110026876 | NANO/MICRO-PATTERNED OPTICAL DEVICE AND FABRICATION METHOD THEREOF - A nano/micro-patterned optical device includes a soft film substrate and nano/micro thin wires. A surface of the soft film substrate includes a nano/micro-pattern formed through a lithography process, and the nano/micro-pattern includes a plurality of depressed grooves. The nano/micro thin wires are placed in the depressed grooves, and used to form a plurality of optical waveguides, in which the optical waveguides include at least one optical coupling region, and the optical coupling region is located on a joining position of the optical waveguides. A fabrication method of the nano/micro-patterned optical device is also provided. | 02-03-2011 |
Jian-Hong Chen, Hsinchu TW
Patent application number | Description | Published |
---|---|---|
20100068656 | HIGH ETCH RESISTANT MATERIAL FOR DOUBLE PATTERNING - The present invention includes a lithography method comprising forming a first patterned insist layer including at least one opening therein over a substrate. A water-soluble polymer layer is formed over the first patterned resist layer and the substrate, whereby a reaction occurs at the interface of the first patterned resist layer and the water-soluble polymer layer. The non-reacted water-soluble polymer layer is removed. Thereafter, a second patterned resist layer is formed over the substrate, wherein at least one portion of the second patterned resist layer is disposed within the at least one opening of the first patterned resist layer or abuts at least one portion of the first patterned resist layer. The substrate is thereafter etched using the first and second patterned resist layers as a mask. | 03-18-2010 |
Jian-Hong Lai, Taichung City TW
Patent application number | Description | Published |
---|---|---|
20140196560 | AUTOMATIC TRANSMISSION SYSTEM FOR BICYCLE - The invention includes a wheel speed detector, disposed beside a wheel of the bicycle for detecting a rotational speed of the wheel; a crankset forward rotation detector, disposed beside a crankset of the bicycle for detecting forward rotational speed of the crankset; a control module, attached on a handle bar of the bicycle, having a display, an operation interface and a program, and electrically connected to the wheel speed detector and the crank forward rotation detector for receiving sensing signals therefrom and outputting control signals; a gear change driver, electrically connected to the control module for receiving the control signals and driving at least one derailleur of the bicycle to change gears; and a power supply, having a battery to supply electric power to the automatic transmission system. | 07-17-2014 |
Jian-Hong Liao, Longtan Township TW
Patent application number | Description | Published |
---|---|---|
20100136712 | COMPOUND AND METHOD FOR PRODUCING THE SAME - The invention provides a Ti doped lead barium zirconate dielectric material which could be applied to high frequency devices. The material comprises a compound with the chemical formula (Pb | 06-03-2010 |
Jian-Hong Lin, Hsinchu TW
Patent application number | Description | Published |
---|---|---|
20110069806 | PULL-DOWN CONTROL CIRCUIT AND SHIFT REGISTER OF USING SAME - The present invention relates to a pull-down control circuit and a shift register of using same. In one embodiment, the pull-down control circuit includes a release circuit and four transistors T | 03-24-2011 |
Jian-Hong Lin, Hsin-Chu TW
Patent application number | Description | Published |
---|---|---|
20110025590 | DISPLAY DEVICE HAVING BI-DIRECTIONAL SCAN MECHANISM AND GATE SIGNAL SCANNING METHOD THEREOF - A display device having bi-directional scan mechanism includes a plurality of gate lines, a first shift register circuit and a second shift register circuit. The first shift register circuit includes a plurality of forward shift register stages. The second shift register circuit includes a plurality of backward shift register stages. Each of the gate lines is electrically connected to both a corresponding forward shift register stage and a corresponding backward shift register stage. When the first shift register circuit is enabled, the forward shift register stages are employed to provide plural forward gate signals sequentially enabled for scanning the gate lines based on a first sequence. When the second shift register circuit is enabled, the backward shift register stages are employed to provide plural backward gate signals sequentially enabled for scanning the gate lines based on a second sequence opposite to the first sequence. | 02-03-2011 |
20120146920 | TOUCH PANEL AND METHOD OF REDUCING NOISE COUPLED BY A COMMON VOLTAGE OF A TOUCH PANEL - A touch panel includes a touch sensor, a liquid crystal panel, and a reverse circuit. The reverse circuit receives common voltage ripples of the liquid crystal panel, and outputs reversed common voltage ripples after reversing the common voltage ripples. After the touch sensor receives the reversed common voltage ripples, the touch sensor outputs a sensing signal according to the reversed common voltage ripples. | 06-14-2012 |
20140347586 | LIQUID CRYSTAL DISPLAY DEVICE - A liquid crystal display device includes a first substrate, a second substrate, and a plurality of spacers. The first substrate includes a plurality of pixel units, which include at least two gate lines, and two neighboring thin film transistors connected to two gate lines, respectively. The second substrate is opposed to the first substrate. At least one of the spacers overlaps with at least a part of the first thin film transistor and at least a part of the second thin film transistor in a top view. | 11-27-2014 |
Jian-Hong Lin, Yunlin TW
Patent application number | Description | Published |
---|---|---|
20080251923 | Seal ring structures with reduced moisture-induced reliability degradation - A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening. | 10-16-2008 |
20090058434 | METHOD FOR MEASURING A PROPERTY OF INTERCONNECTIONS AND STRUCTURE FOR THE SAME - A method for measuring a property of interconnections is provided. The method includes the following steps. A plurality of interconnection test patterns are provided. A pad to which the plurality of interconnection test patterns are parallelly connected is formed. At least one resistor is formed between at least one of the plurality of interconnection test patterns and the pad. The property of the plurality of interconnection test patterns is measured by applying a current, a voltage and/or a mechanical stress to the pad. | 03-05-2009 |
20100271753 | METAL OXIDE METAL CAPACITOR WITH SLOT VIAS - A capacitor includes the first electrode comprising the first conductive lines and vias, where the first conductive lines on the same layer are parallel to each other and connected to the first periphery conductive line, and the first conductor lines aligned in adjacent layers are coupled to each other by the vias; the second electrode aligned opposite to the first electrode comprising the second conductive lines and vias, where the second conductive lines on the same layer are parallel to each other and connected to the second periphery conductive line, and the second conductor lines aligned in adjacent layers are coupled to each other by the vias; and oxide layers formed between the first electrode and the second electrode, where the vias have rectangular (slot) shape on a layout. In one embodiment, the conductive lines and vias are metal, e.g. copper, aluminum, or tungsten. The vias can have various sizes. | 10-28-2010 |
20100327456 | Process for Improving the Reliability of Interconnect Structures and Resulting Structure - An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate. | 12-30-2010 |
20110108945 | Seal Ring Structures with Reduced Moisture-Induced Reliability Degradation - A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening. | 05-12-2011 |
20130063175 | Semiconductor Device Components and Methods - Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end. | 03-14-2013 |
20130127016 | METAL OXIDE METAL CAPACITOR WITH SLOT VIAS - A capacitor includes a first electrode including a plurality of first conductive lines, at least one first via, and at least one second via. The first conductive lines are parallel and connected to a first periphery conductive line. The first conductor lines in adjacent layers are coupled by the at least one first and second via. The at least one first via has a first length, and the at least one second via has a second length. The capacitor includes a second electrode opposite to the first electrode. The second electrode includes a plurality of second conductive lines and at least one third via. The second conductive lines are parallel and connected to a second periphery conductive line. The second conductor lines in adjacent layers are coupled by the at least one third via. The capacitor includes at least one oxide layer between the first electrode and the second electrode. | 05-23-2013 |
20140103496 | SEAL RING STRUCTURES WITH REDUCED MOISTURE-INDUCED RELIABILITY DEGRADATION - A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening. | 04-17-2014 |
20140145194 | Semiconductor Device Components and Methods - Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end. | 05-29-2014 |
Jian-Hong Lin, Taipei County TW
Patent application number | Description | Published |
---|---|---|
20100014030 | ARRAY SUBSTRATE AND DISPLAY PANEL THEREOF - An array substrate having a display region and a peripheral circuit region adjacent to the display region is provided. The array substrate includes a pixel array, a plurality of test shorting bars and a plurality of wires. The pixel array is disposed in the display region. The test shorting bars are disposed in the peripheral circuit region. The wires electrically connected with the pixel array are disposed in the peripheral circuit region. Specially, at least one wire and the test shorting bar share a part for connecting each other and the part forms a common trace. | 01-21-2010 |
20120268434 | DISPLAY PANEL - A display panel including a first substrate, a second substrate, and a liquid crystal layer. The first substrate comprises a display region and a peripheral circuit region adjacent to the display region, and the first substrate includes a pixel array, a plurality of test shorting bars, and a plurality of wires. The pixel array is disposed in the display region. The test shorting bars are disposed in the peripheral circuit region. The wires are disposed in the peripheral circuit region and electrically connected with the pixel array. Moreover, at least one wire and one of the test shorting bars respectively share a part for connecting with each other and forming a common trace. Additionally, the second substrate is disposed opposite to the first substrate. The liquid crystal layer is disposed between the first substrate and the second substrate. | 10-25-2012 |
Jian-Hong Lin, Huwei Township TW
Patent application number | Description | Published |
---|---|---|
20120002375 | METHOD AND STRUCTURE FOR DISSIPATING HEAT AWAY FROM A RESISTOR HAVING NEIGHBORING DEVICES AND INTERCONNECTS - A semiconductor structure for dissipating heat away from a resistor having neighboring devices and interconnects. The semiconductor structure includes a semiconductor substrate, a resistor disposed above the semiconductor substrate, and a thermal protection structure disposed above the resistor. The thermal protection structure has a plurality of heat dissipating elements, the heat dissipating elements having one end disposed in thermal conductive contact with the thermal protection structure and the other end in thermal conductive contact with the semiconductor substrate. The thermal protection structure receives the heat generated from the resistor and the heat dissipating elements dissipates the heat to the semiconductor substrate. | 01-05-2012 |
Jian-Hong Lin, Huwei TW
Patent application number | Description | Published |
---|---|---|
20120276732 | PROTECTION LAYER FOR PREVENTING LASER DAMAGE ON SEMICONDUCTOR DEVICES - A method for forming a semiconductor structure is provided to prevent energy that is used to blow at least one fuse formed on a metal layer above a semiconductor substrate from causing damage on the structure. The semiconductor structure includes a device, guard ring, protection ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. A seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy. | 11-01-2012 |
Jian-Hong Liu, Kaohsiung City TW
Patent application number | Description | Published |
---|---|---|
20130138736 | MULTIMEDIA FILE SHARING METHOD AND SYSTEM THEREOF - A multimedia file sharing method and a system thereof are provided herein, which applies the virtual file technology to achieve near real time multimedia sharing and transparent receiving functions. In the method, an interface software system is established through a network to speed up playing of multimedia files by different multimedia players. The interface software provides a speeding up and near real time multimedia playing effect for sharing multimedia through the network, by which for different transmissions of multimedia files or for playing multimedia files with different formats, the multimedia player is not necessary to modify or add the software of the players to meet the streaming protocols or container. In addition, the interface software is capable of providing the effect of playing the multimedia files by the players with satisfied quality and near real time performance. | 05-30-2013 |
Jian-Hong Liu, Hsinchu TW
Patent application number | Description | Published |
---|---|---|
20150051856 | METHOD FOR ESTIMATING VOLTAGE STABILITY - A method for estimating voltage stability, includes establishing a multi-port equivalent model and the measurement-based equivalent impedance; calculating the reactive power response factor through two consecutive samples from wide-area phasor measurement unit measurement; finding the mitigation factor; constructing the modified coupled single-port model with the modified impedance and voltage; and using the modified maximal loading parameter for voltage stability assessment. | 02-19-2015 |
20150051866 | METHOD FOR OPTIMIZING PHASOR MEASUREMENT UNIT PLACEMENT - A method for optimizing phasor measurement unit placement includes two phase, calculating a degree of each node of a power system; selecting a node with maximum degree as a center and propagate to the entire power system so as to form a spanning tree; selecting a feasible power dominating set (PDS) of minimum cardinality for the spanning tree in the Phase I. In phase II, use the Artificial Bees Colony Algorithm. According to the minimum PDS, calculating a fitness functions by the equation | 02-19-2015 |
Jian-Hong Luo, New Taipei City TW
Patent application number | Description | Published |
---|---|---|
20150309270 | OPTICAL COUPLING ELEMENT AND OPTICAL MODULE HAVING THE SAME - An optical coupling element, for coupling a light emitting element to a light transmission element, includes a light guide element. The light guide element has a light incident part, a total reflection surface and a light output part. The light incident path is formed at the light incident part corresponding to the light emitting element. The light reflection path is formed at the light output part corresponding to the light transmission element. The first included angle θ1 is formed between the light incident path and the total reflection surface and is not equal to 45 degrees. The light emitting element is adapted to emit a beam toward the total reflection surface along the light incident path by passing through the light guide element from the light incident part. Moreover, the beam is reflected by the total reflection surface and is outputted toward the light transmission element. | 10-29-2015 |
Jian-Hong Su, Singapore SG
Patent application number | Description | Published |
---|---|---|
20130214336 | METHOD FOR FILLING TRENCH WITH METAL LAYER AND SEMICONDUCTOR STRUCTURE FORMED BY USING THE SAME - A method for filling a trench with a metal layer is disclosed. A deposition apparatus having a plurality of supporting pins is provided. A substrate and a dielectric layer disposed thereon are provided. The dielectric layer has a trench. A first deposition process is performed immediately after the substrate is placed on the supporting pins to form a metal layer in the trench, wherein during the first deposition process a temperature of the substrate is gradually increased to reach a predetermined temperature. When the temperature of the substrate reaches the predetermined temperature, a second deposition process is performed to completely fill the trench with the metal layer. | 08-22-2013 |
20140374909 | METHOD FOR FILLING TRENCH WITH METAL LAYER AND SEMICONDUCTOR STRUCTURE FORMED BY USING THE SAME - A method for filling a trench with a metal layer is disclosed. A deposition apparatus having a plurality of supporting pins is provided. A substrate and a dielectric layer disposed thereon are provided. The dielectric layer has a trench. A first deposition process is performed immediately after the substrate is placed on the supporting pins to form a metal layer in the trench, wherein during the first deposition process a temperature of the substrate is gradually increased to reach a predetermined temperature. When the temperature of the substrate reaches the predetermined temperature, a second deposition process is performed to completely fill the trench with the metal layer. The present invention further provides a semiconductor device having an aluminum layer with a reflectivity greater than 1, wherein the semiconductor device is formed by using the method. | 12-25-2014 |
Jian-Hong Wu, Tainan City TW
Patent application number | Description | Published |
---|---|---|
20130011939 | Techniques Providing Semiconductor Wafer Grouping In A Feed Forward Process - A method for processing a plurality of semiconductor wafers includes acquiring a process parameter measurement for each of the semiconductor wafers, associating each of the semiconductor wafers with one of a plurality of groups based on a respective process parameter measurement for each of the semiconductor wafers, where each respective group corresponds to a respective recipe, and for each one of the groups, processing ones of the semiconductor wafers associated with that group together according to a respective recipe. | 01-10-2013 |
Jian-Hong Zeng, Taoyuan Hsien CN
Patent application number | Description | Published |
---|---|---|
20130214842 | POWER SYSTEM, POWER MODULE THEREIN AND METHOD FOR FABRICATING POWER MODULE - A power system, a power module therein and a method for fabricating power module are disclosed herein. The power module includes a first and a second common pins, and a first and a second bridge arms. The first and the second common pins are symmetrically disposed at one side of a substrate. The first bridge arm includes a first and a second semiconductor devices, and the first and the second semiconductor devices are connected to each other through the first common pin and disposed adjacently. The second bridge arm includes a third and a fourth semiconductor devices, and the third and the fourth semiconductor devices are connected to each other through the second common pin and disposed adjacently. The first and the third semiconductor devices are disposed symmetrically, and the second and the fourth semiconductor devices are disposed symmetrically. | 08-22-2013 |