Patent application number | Description | Published |
20100138683 | POWER CONTROL UNIT WITH DIGITALLY SUPPLIED SYSTEM PARAMETERS - Methods and apparatuses provide voltage regulation for a processor. Control or configuration parameters for a voltage regulator (VR) are provided digitally over a configuration bus to a VR controller. The parameters may be provided directly from a storage element, or via a processing element or processor core. Based in whole or in part on the parameters, the VR controller provides an output control signal to affect a power output from a power converter to the processing element. In one embodiment, the VR controller is integrated onto the same IC as the processing element. | 06-03-2010 |
20110154090 | Controlling Time Stamp Counter (TSC) Offsets For Mulitple Cores And Threads - In one embodiment, the present invention includes a method for recording a time stamp counter (TSC) value of a first TSC counter of a processor before a system suspension, accessing the stored TSC value after the system suspension, and directly updating a thread offset value associated with a first thread executing on a first core of the processor with the stored TSC value, without performing a synchronization between a plurality of cores of the processor. Other embodiments are described and claimed. | 06-23-2011 |
20120216029 | METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING CONFIGURABLE MAXIMUM PROCESSOR CURRENT - An apparatus, method and system is described herein for providing multiple maximum current configuration options including corresponding turbo frequencies for a processing device. Available options for a processor are determined by initialization code. And based on platform electrical capabilities, an optimal one of the multiple current configuration options is selected. Moreover, during runtime another current configuration is dynamically selected based on current configuration considerations to provide high flexibility and best possible performance per part and computing platform. | 08-23-2012 |
20130111236 | Controlling Operating Frequency Of A Core Domain Via A Non-Core Domain Of A Multi-Domain Processor | 05-02-2013 |
20130179709 | Controlling Operating Frequency Of A Core Domain Via A Non-Core Domain Of A Multi-Domain Processor - In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed. | 07-11-2013 |
20130261814 | POWER DOWN AND QUICK START OF THERMAL SENSOR - A thermal sensor is placed in a low power state. When the sensor is triggered to wake from the low power state, it initiates a thermal sensor scan from the sensor value measured prior to the low power state. The thermal sensor initially adjusts the measured value with a fast count by a configurable adjustment of greater than 1, and after reaching an inflection point performs normal count by adjustments of 1. | 10-03-2013 |
20130275737 | COLLABORATIVE PROCESSOR AND SYSTEM PERFORMANCE AND POWER MANAGEMENT - The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system. | 10-17-2013 |
20130275796 | COLLABORATIVE PROCESSOR AND SYSTEM PERFORMANCE AND POWER MANAGEMENT - The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system. | 10-17-2013 |
20130283032 | COLLABORATIVE PROCESSOR AND SYSTEM PERFORMANCE AND POWER MANAGEMENT - The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system. | 10-24-2013 |
20130339777 | MICROPROCESSOR-ASSISTED AUTO-CALIBRATION OF VOLTAGE REGULATORS - Dynamic runtime calibration of a processor with respect to a specific voltage regulator that powers the processor or a memory subsystem coupled to the processor can reduce or eliminate the need for guardbands in power management computations. The processor receives a current measurement from the voltage regulator and computes a calibration factor based on the measured value and a stored expected value. The calibration factor can be used in making power management decisions instead of adding the guardband to power readings. A manufacturer or distributor of the processor can compute the stored values with a controlled voltage supply that has a higher precision than typical commercial power supplies used in computing systems. The computed, stored values indicate the expected value, which can be used to determine a calibration factor relative to a voltage regulator of an active system. | 12-19-2013 |
20140006761 | MECHANISM TO PROVIDE WORKLOAD AND CONFIGURATION-AWARE DETERMINISTIC PERFORMANCE FOR MICROPROCESSORS | 01-02-2014 |
20140068291 | Performing Cross-Domain Thermal Control In A Processor - In an embodiment, a processor includes a first domain with at least one core to execute instructions and a second domain coupled to the first domain and including at least one non-core circuit. These domains can operate at independent frequencies, and a power control unit coupled to the domains may include a thermal logic to cause a reduction in a frequency of the first domain responsive to occurrence of a thermal event in the second domain. Other embodiments are described and claimed. | 03-06-2014 |
20140068293 | Performing Cross-Domain Thermal Control In A Processor - In an embodiment, a processor includes a first domain with at least one core to execute instructions and a second domain coupled to the first domain and including at least one non-core circuit. These domains can operate at independent frequencies, and a power control unit coupled to the domains may include a thermal logic to cause a reduction in a frequency of the first domain responsive to occurrence of a thermal event in the second domain. Other embodiments are described and claimed. | 03-06-2014 |
20140157021 | ENFORCING A POWER CONSUMPTION DUTY CYCLE IN A PROCESSOR - In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed. | 06-05-2014 |
20140159785 | METHOD AND APPARATUS FOR ATOMIC FREQUENCY AND VOLTAGE CHANGES - A method and apparatus for atomic frequency and voltage changes in the processor. In one embodiment of the invention, the atomic frequency and voltage changes in the processor is feasible due to the enabling technology of fully integrated voltage regulators (FIVR) that are integrated in the processor. FIVR allows independent configuration of each core in the processor and the configuration includes, but is not limited to, voltage setting, frequency setting, clock setting and other parameters that affects the power consumption of each core. | 06-12-2014 |
20140176581 | CONTROLLING CONFIGURABLE PEAK PERFORMANCE LIMITS OF A PROCESSOR - In one embodiment, the present invention includes a processor having a plurality of cores each to execute instructions, a non-volatile storage to store maximum peak operating frequency values each a function of a given number of active cores, a configuration storage to store frequency limits each corresponding to one of the maximum peak operating frequency values or a configurable clip frequency value less than the maximum peak operating frequency value. In turn, a power controller is configured to limit operating frequency of the cores to a corresponding frequency limit obtained from the configuration storage. Other embodiments are described and claimed. | 06-26-2014 |
20140181538 | Controlling Configurable Peak Performance Limits Of A Processor - In one embodiment, the present invention includes a processor having a plurality of cores each to execute instructions, a non-volatile storage to store maximum peak operating frequency values each a function of a given number of active cores, a configuration storage to store frequency limits each corresponding to one of the maximum peak operating frequency values or a configurable clip frequency value less than the maximum peak operating frequency value. In turn, a power controller is configured to limit operating frequency of the cores to a corresponding frequency limit obtained from the configuration storage. Other embodiments are described and claimed. | 06-26-2014 |
20140181545 | Dynamic Balancing Of Power Across A Plurality Of Processor Domains According To Power Policy Control Bias - In an embodiment, a processor includes multiple domains including a core domain having at least one core to execute instructions and a graphics domain including at least one graphics engine to perform graphics operations and a power controller to control power consumption of the processor. The power controller may include a logic to receive an indication of a priority domain of the domains and to dynamically allocate power to the domains based on a power limit, one or more maximum domain frequency requests, and the priority domain indication. Other embodiments are described and claimed. | 06-26-2014 |
20140184317 | ELECTRONIC DEVICE TO CONTROL VOLTAGE FLUCTUATIONS - An electronic device may include a power delivery system to provide a voltage, and an integrated circuit having a processor to receive the voltage. When the received voltage exceeds a prescribed value, the integrated circuit to perform an act to consume current from the power delivery system. | 07-03-2014 |
20140189225 | Independent Control Of Processor Core Retention States - In an embodiment, a processor includes a first processor core, a second processor core, a first voltage regulator to provide a first voltage to the first processor core with a first active value when the first processor core is active, and a second voltage regulator to provide a second voltage to the second processor core with a second active value when the second processor core is active. Responsive to a request to place the first processor core in a first low power state with an associated first low power voltage value, the first voltage regulator is to reduce the first voltage to a second low power voltage value that is less than the first low power voltage value, independent of the second voltage regulator. First data stored in a first register of the first processor core is retained at the second low power value. Other embodiments are described and claimed. | 07-03-2014 |
20140195829 | DYNAMICALLY COMPUTING AN ELECTRICAL DESIGN POINT (EDP) FOR A MULTICORE PROCESSOR - In one embodiment, a multicore processor includes a controller to dynamically limit a maximum permitted turbo mode frequency of its cores based on a core activity pattern of the cores and power consumption information of a unit power table. In one embodiment, the core activity pattern can indicate, for each core, an activity level and a logic unit state of the corresponding core. Further, the unit power table can be dynamically computed based on a temperature of the processor. Other embodiments are described and claimed. | 07-10-2014 |
20140281612 | MEASUREMENT OF PERFORMANCE SCALABILITY IN A MICROPROCESSOR - A scalability algorithm causes a processor to initialize a performance indicator counter, operate at an initial frequency of the first clock signal for a first duration, and determine, based on the performance indicator counter, an initial performance of the first processing core. The algorithm may then cause the processor to operate at a second frequency of the first clock signal for a second duration and determine, based on the performance indicator counter, a second performance of the first processing core. A performance scalability of the first processing core may be determined based on the initial performance and the second performance and an operational parameter, such as one or more clock frequencies and/or supply voltage(s), may be changed based on the determined scalability. | 09-18-2014 |