Patent application number | Description | Published |
20130341605 | Substrate For OLED And Method Of Manufacturing The Same - A substrate for an organic light-emitting device (OLED) and a method of manufacturing the same, in which the light extraction efficiency and process efficiency of the OLED can be improved. The substrate for an OLED that includes a base substrate, a first metal oxide thin film coating one surface of the base substrate, the first metal oxide thin film having a first texture on a surface thereof, a second metal oxide thin film coating the other surface of the base substrate, and a third metal oxide thin film coating a surface of the second metal oxide thin film. | 12-26-2013 |
20140103336 | METAL OXIDE THIN FILM SUBSTRATE FOR OLED AND METHOD OF FABRICATING THE SAME - A metal oxide thin film substrate for an organic light-emitting device (OLED) which exhibits superior light extraction efficiency and can be easily fabricated at low cost and a method of fabricating the same and a method of fabricating the same. The metal oxide thin film substrate for an OLED includes a base substrate and a metal oxide thin film formed on the base substrate, the metal oxide thin film being made of a mixture of at least two metal oxides having different refractive indices. | 04-17-2014 |
20140167085 | LIGHT EMITTING DEVICE HAVING IMPROVED LIGHT EXTRACTION EFFICIENCY - According to example embodiments, a light emitting device includes a transparent substrate, a transparent electrode on a transparent substrate, a transparent light extraction layer at least partially on the transparent electrode, a light emitting layer on the transparent electrode, and a reflective electrode on the light extraction layer and the light emitting layer. The light extraction layer and the light emitting layer may be alternately and repeatedly arranged between the transparent electrode and the reflective electrode. | 06-19-2014 |
20140191266 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE LIGHT EMITTING DEVICE - In one example embodiment, a light emitting device includes a transparent substrate and a transparent electrode on the transparent substrate, the transparent electrode comprising at least two transparent electrode layers, the at least two transparent electrode layers being successively stacked and having different refractive indices, the refractive index of one of the at least two transparent electrode layers that is closer to the transparent substrate being higher than the refractive index of the other one of the at least two transparent electrode layers. The light emitting device further includes a light emission layer on the transparent electrode and a reflective electrode on the light emission layer. | 07-10-2014 |
Patent application number | Description | Published |
20090154868 | SEMICONDUCTOR OPTO-ELECTRONIC INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME - Provided are semiconductor opto-electronic integrated circuits and methods of forming the same. The semiconductor opto-electronic integrated circuit includes: an optical waveguide disposed on a substrate and including an input terminal and an output terminal; an optical grating formed on the optical waveguide; and an optical active device disposed on the optical grating and receiving an optical signal from the optical waveguide through the optical grating to modulate the optical signal. | 06-18-2009 |
20100142878 | ABSORPTION MODULATOR AND MANUFACTURING METHOD THEREOF - An absorption modulator is provided. The absorption modulator includes a substrate, an insulation layer disposed on the substrate, and a waveguide having a P-I-N diode structure on the insulation layer. Absorptance of an intrinsic region in the P-I-N diode structure is varied when modulating light inputted to the waveguide. The absorption modulator obtains the improved characteristics, such as high speed, low power consumption, and small size, because it greatly reduces the cross-sectional area of the P-I-N diode structure. | 06-10-2010 |
20100278477 | SEMICONDUCTOR INTEGRATED CIRCUITS INCLUDING OPTOELECTRONIC DEVICE FOR CHANGING OPTICAL PHASE - Provided is a semiconductor integrated circuit. The semiconductor integrated circuit includes a semiconductor pattern disposed on a substrate and including an optical waveguide part and a pair of recessed portions. The optical waveguide part has a thickness ranging from about 0.05 m to about 0.5 μm. The recessed portions are disposed on both sides of the optical waveguide part and have a thinner thickness than the optical waveguide part. A first doped region and a second doped region are disposed in the recessed portions, respectively. The first and second doped regions are doped with a first conductive type dopant and a second conductive type dopant, respectively. An intrinsic region is formed in at least the optical waveguide part to contact the first and second doped regions. | 11-04-2010 |
20110051222 | ELECTRO-OPTIC DEVICE - An electro-optic device is provided. The electro-optic device includes a junction layer disposed between a first conductivity type semiconductor layer and a second conductivity type semiconductor layer to which a reverse vias voltage is applied. The first conductivity type semiconductor layer and the second conductivity type semiconductor layer have an about 2 to 4-time doping concentration difference therebetween, thus making it possible to provide the electro-optic device optimized for high speed, low power consumption and high integration. | 03-03-2011 |
20110058764 | ELECTRO-OPTIC MODULATING DEVICE - Provided is an electro-optic modulating device. The electro-optic modulating device includes an optical waveguide with a vertical structure and sidewalls of the vertical structure are used to configure a junction. | 03-10-2011 |
20110109955 | ELECTRO-OPTIC DEVICE - Provided is an electro-optic device. Sine the electro-optic device includes a plurality of first conductive type semiconductor layers and a plurality of depletion layers formed by a third semiconductor disposed between the plurality of first conductive type semiconductor layers, an electro-optic device optimized for a high speed and low power consumption can be provided. | 05-12-2011 |
20110135243 | ELECTRO-OPTIC DEVICE - Provided is an electro-optic device. The electro-optic device includes an input Y-branch comprising a first input branch and a second input branch, an output Y-branch comprising a first output branch and a second output branch, a first optical modulator and a second optical modulator connected in series between the first input branch and the first output branch, and a third optical modulator connecting the second input branch to the second output branch. The first optical modulator comprises a PIN diode, and each of the second optical modulator and the third optical modulator comprises a PN diode. | 06-09-2011 |
20120027336 | MACH-ZEHNDER MODULATOR - Provided is a Mach-Zehnder modulator. The Mach-Zehnder modulator comprises an input wave guide and an output wave guide arranged on a substrate, a first branch wave guide and a second branch wave guide connected in parallel between the input and output wave guides, and a connecting region configured to connect the first branch wave guide and the second branch wave guide. Each of the first and second branch wave guides comprises first doped regions doped with a first dopant and second doped regions doped with a second dopant having different conductivity from the first dopant, and the connecting region is doped with the first dopant and arranged between the first regions of the first and second branch wave guides. | 02-02-2012 |
20120063714 | ELECTRO-OPTIC DEVICE AND MACH-ZEHNDER OPTICAL MODULATOR HAVING THE SAME - Provided are an electro-optic device with a high modulation rate and a mach-zehnder optical modulator having the same. The electro-optic device includes a slap, a rip waveguide, a first impurity region, a second impurity region, and a third impurity region. The slap is disposed on a substrate. The rip waveguide includes a mesa extending in one direction on the slap and the slap disposed under the mesa. The first impurity region is disposed in the slap of one side of the mesa. The third impurity region is disposed in the slap of the other side of the mesa to oppose the first impurity region. The second impurity region is disposed in the rip waveguide between the first impurity region and the third impurity region. | 03-15-2012 |
20120148244 | OPTICAL NETWORK STRUCTURES FOR MULTI-CORE CENTRAL PROCESSOR UNIT - Provided is an optical network structure. To configure an optical network structure between hundreds or more of cores in a CPU, intersection between waveguides does not occur, and thus, the optical network structure enables two-way communication between all the cores without an optical switch disposed in an intersection point. The present invention enables a single chip optical network using a silicon photonics optical element, and a CPU chip configured with hundreds or thousands of cores can be developed. | 06-14-2012 |
20130161541 | TERAHERTZ WAVE GENERATOR AND METHOD OF GENERATING TERAHERTZ WAVE - Disclosed is a terahertz wave generator which includes a first light source outputting a first light having a first frequency; a second light source outputting a second light having a second frequency different from the first frequency; a second harmonic generation unit performing second harmonic conversion on the first and second lights to generate a third light and a fourth light; and a photomixer converting a mixing light of the third and fourth lights into a terahertz wave alternating signal and outputting a terahertz wave. | 06-27-2013 |
20130271335 | HORN ANTENNA APPARATUS - Disclosed is a horn antenna apparatus. The horn antenna apparatus includes a substrate; and a silicone antenna part bonded to the substrate and provided with a horn cavity having a radiating aperture part having one portion opened to the outside in a horizontal direction to a bonding surface. In accordance with the embodiment of the present invention, it is possible to easily implement the horn antenna apparatus capable of saving cost and providing the high gain using the photolithography and chemical etching method and to implement the terahertz transmitting and receiving module capable of saving cost and providing the high efficiency using the same. | 10-17-2013 |
20130299701 | PHOTO DETECTOR AND OPTICAL DEVICE - An optical device may include first and second lasers generating first and second laser beams; and a photo detector detecting the first and second laser beams. The optical detector comprises a substrate, a first impurity layer on the substrate, an absorption layer on the first impurity layer and a second impurity layer on the absorption layer. The absorption layer generates a terahertz by a beating of the first and second laser beams and has a thickness of less than | 11-14-2013 |
20130320215 | INTERCONNECTION APPARATUS AND METHOD USING TERAHERTZ WAVES - Disclosed herein is an interconnection apparatus and method using terahertz waves. The interconnection apparatus using terahertz waves according to the present invention includes a first terahertz wave generation unit for generating a first transmission terahertz wave, a center frequency of which is a first center frequency, using photomixing. A second terahertz wave generation unit generates a second transmission terahertz wave, a center frequency of which is a second center frequency different from the first center frequency. A first terahertz wave detection unit detects a first reception terahertz wave corresponding to the first transmission terahertz wave. A second terahertz wave detection unit detects a second reception terahertz wave corresponding to the second transmission terahertz wave. | 12-05-2013 |
20140061475 | APPARATUS AND METHOD FOR CONTACTLESS THICKNESS MEASUREMENT - A contactless thickness measuring apparatus is provided which includes an terahertz transmitter configured to receive the first optical path signal from the coupler and to generate a terahertz continuous wave using the first optical signal and an applied bias; an optical delay line configured to delay the second optical path signal output from the coupler; and an terahertz receiver configured to receive the terahertz continuous wave penetrating a sample and to detect an optical current using the terahertz continuous wave and the second optical path signal delayed. A thickness of the sample is a value corresponding to the optical current which phase value becomes a constant regardless of a plurality of measurement frequencies. | 03-06-2014 |
20140166881 | TERAHERTZ WAVE GENERATING MODULE AND TERAHERTZ WAVE DETECTING DEVICE INCLUDING THE SAME - A terahertz wave generating module includes a bidirectional light source which provides a first dual-mode beam in a first direction and a second dual-mode beam in a second direction; a forward lens unit which focuses the first dual-mode beam; a photomixer unit which converts the first dual-mode beam focused by the forward lens unit into a terahertz wave; a backward lens unit which focuses the second dual-mode beam; and a light output unit which uses the second dual-mode beam focused by the backward lens unit as a light signal, wherein the bidirectional light source, the forward lens unit, the photomixer unit, the backward lens unit, and the light output unit are integrated in a housing. | 06-19-2014 |
20140175306 | BEATING SIGNAL MONITORING MODULE, TERAHERTZ WAVE GENERATION DEVICE AND OPTICAL SIGNAL MONITORING DEVICE INCLUDING THE BEATING SIGNAL MONITORING MODULE - The inventive concept relates to a beating signal monitoring module and a terahertz wave generation device and an optical signal monitoring device that including the beating signal monitoring module. The beating signal monitoring module includes a nonlinear unit generating an optical signal including a FWM light in response to a beating signal generated from a first light and a second light; a filter unit separating the FWM light from the optical signal and outputting the separated FWM light; and a monitoring unit monitoring the beating signal using the separated FWM light. The beating signal monitoring module and a terahertz wave generation device and an optical signal monitoring device that including the beating signal monitoring module can effectively monitor a beating signal being generated by two lasers using a Four Wave Mixing signal. | 06-26-2014 |
20140183441 | APPARATUS FOR GENERATING/DETECTING TERAHERTZ WAVE USING GRAPHENE AND MANUFACTURING METHOD OF THE SAME - Provided is a terahertz wave generating/detecting apparatus and a method for manufacturing the same. The terahertz wave generating/detecting apparatus includes; a substrate having an active region and a transmitting region; a lower metal layer extending in a first direction on the active region and the transmitting region of the substrate; a graphene layer disposed on the lower metal layer on the active region; and upper metal layers extending in the first direction on the graphene layer of the active region and the substrate in the transmission region, wherein a terahertz wave is generated or amplified by a surface plasmon polariton that is induced on a boundary surface between the graphene layer and the lower metal layer by beated laser light applied to the graphene layer and the metal layer. | 07-03-2014 |
20150090906 | TERAHERTZ CONTINUOUS WAVE EMITTING DEVICE - Provided herein is terahertz continuous wave emitting device having: a plurality of laser light sources generating a plurality of laser lights; and an absorption area formed between the plurality of laser light sources in order to adjust interaction of the plurality of laser lights, wherein the absorption area is configured to have a photo diode, an antenna integrated into the photo diode. | 04-02-2015 |
20150179842 | RECTIFIER AND TERAHERTZ DETECTOR USING THE SAME - Disclosed is a rectifier capable of performing a high speed rectifying operation, and includes: a first semiconductor layer; a second semiconductor layer; and a third semiconductor layer, in which the first semiconductor layer and the third semiconductor layer are formed of semiconductor layers having the same type, and the second semiconductor layer is formed between the first semiconductor layer and the third semiconductor layer, is formed of a semiconductor layer having a different type from that of the first semiconductor layer and the third semiconductor layer, and is formed in graded doped state. | 06-25-2015 |
Patent application number | Description | Published |
20080251494 | Method for manufacturing circuit board - A method of manufacturing a circuit board is disclosed. The method may include: forming a relievo pattern, which is in a corresponding relationship with a circuit pattern, on a metal layer that is stacked on a carrier; stacking and pressing the carrier onto an insulation layer with the relievo pattern facing the insulation layer; transcribing the metal layer and the relievo pattern into the insulation layer by removing the carrier; forming a via hole in the insulation layer on which the metal layer is transcribed; and filling the via hole and forming a plating layer over the metal layer by performing plating over the insulation layer on which the metal layer is transcribed. As the relievo pattern may be formed on the metal layer stacked on the carrier, and the relievo pattern may be transcribed into the insulation layer, high-density circuit patterns can be formed. | 10-16-2008 |
20080264676 | Circuit board and method for manufaturing thereof - A method of manufacturing a circuit board that includes: forming a conductive relievo pattern, including a first plating layer, a first metal layer, and a second plating layer stacked sequentially in correspondence with a first circuit pattern, on a seed layer stacked on a carrier; stacking and pressing together the carrier and an insulator, such that a surface of the carrier having the conductive relievo pattern faces the insulator; transcribing the conductive relievo pattern into the insulator by removing the carrier; forming a conduction pattern, including a third plating layer and a second metal layer stacked sequentially in correspondence with a second circuit pattern, on the surface of the insulator having the conductive relievo pattern transcribed; removing the first plating layer and seed layer; and removing the first and second metal layers, can provide a circuit board that has high-density circuit patterns without an increased amount of insulator. | 10-30-2008 |
20090011220 | Carrier and method for manufacturing printed circuit board - A carrier and a method for manufacturing a printed circuit board are disclosed. The method for manufacturing a printed circuit board may include: forming a first circuit pattern on each of a pair of release layers, which are attached respectively to either side of a base layer by adhesive layers; detaching the pair of release layers from the base layer; stacking and pressing the pair of release layers onto either side of an insulation substrate such that the first circuit patterns are buried in the insulation substrate; and separating the pair of release layers. By forming a circuit pattern on each of a pair of release layers with a single process, and transferring the circuit pattern into each side of an insulation substrate, the manufacturing process can be shortened and circuit patterns can be formed to a high density. | 01-08-2009 |
20090140429 | Metal interconnection of a semiconductor device and method of manufacturing the same - A method of manufacturing a metal interconnection of a semiconductor device includes forming a base layer with at least one groove, the at least one groove having an open upper portion, forming a first metal layer in the at least one groove, forming a seed metal layer on the first metal layer in the at least one groove, the seed metal layer being only on a bottom surface of the at least one groove, and forming a metal pattern grown from the seed metal layer to fill the at least one grove. | 06-04-2009 |
20100013094 | SEMICONDUCTOR PACKAGE AND METHODS OF MANUFACTURING THE SAME - A semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package include a substrate including a plurality of pads and a plurality of bumps evenly disposed on an entire region of the substrate regardless of an arrangement of the plurality of pads. According to the present invention, a simplification of a process can be accomplished, a cost of a process can be reduced, reliability can be improved and an under-filling can become easy. | 01-21-2010 |
20100018633 | METHOD OF MANUFACTURING PRINTED CIRCUIT BOARD - Disclosed is a method of manufacturing a printed circuit board. The method of manufacturing a printed circuit board having a via for connecting one layer to another layer can include forming a circuit pattern on one surface of a carrier; processing a hole corresponding to the via on one surface of the carrier; compressing the surface of the carrier into one surface of an insulation body; removing the carrier; processing a via hole on the insulation body, corresponding to a position of the hole; and forming a conductive material in the via hole, to thereby easily process a hole for forming a via and have high design freedom | 01-28-2010 |
20110226626 | APPARATUS AND METHOD FOR TREATING SUBSTRATE - A substrate treating device may include a plating treatment portion configured to perform a plating process of a substrate, a wet treatment portion configured to perform a wet treating process of the substrate, the wet treatment portion being under the plating treatment portion, and a substrate support portion configured to support the substrate so that a plating surface of the substrate faces upward, the substrate support portion being further configured to move the substrate between the plating treatment portion and the wet treatment portion. | 09-22-2011 |
20110259627 | Circuit board with buried circuit pattern - A circuit board includes: an insulator having a groove; a circuit layer filling a portion of the groove; a solder pad on the circuit layer filling the remainder of the groove; and a circuit pattern electrically connected with the circuit layer, the circuit pattern buried in the insulator such that a portion of the circuit pattern is exposed at a surface of the insulator. | 10-27-2011 |
20120086123 | SEMICONDUCTOR ASSEMBLY AND SEMICONDUCTOR PACKAGE INCLUDING A SOLDER CHANNEL - Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction. | 04-12-2012 |
20120111607 | CIRCUIT BOARD WITH HIGH-DENSITY CIRCUIT PATTERNS - A circuit board including: an insulator having a trench; a first circuit pattern formed to bury a portion of the trench; and a second circuit pattern formed on a surface of the insulator having the trench formed therein. | 05-10-2012 |
20120292195 | APPARATUS AND METHOD FOR ELECTROPLATING FOR SEMICONDUCTOR SUBSTRATE - An apparatus for electroplating a semiconductor device includes a plating bath accommodating a plating solution, and a paddle in the plating bath, the paddle including a plurality of holes configured to pass the plating solution through the paddle toward a substrate, and a plating solution flow reinforcement portion configured to selectively reinforce a flow of the plating solution to a predetermined area of the substrate, the predetermined area of the substrate being an area requiring a relatively increased supply of metal ions of the plating solution. | 11-22-2012 |
20120295434 | SOLDER COLLAPSE FREE BUMPING PROCESS OF SEMICONDUCTOR DEVICE - A method of forming bumps of a semiconductor device with reduced solder bump collapse. The method includes preparing a semiconductor substrate in which pads are exposed externally from a passivation layer; forming a seed layer on the semiconductor substrate; forming a photoresist pattern to expose the seed layer on the pads; forming pillars by performing a primary electroplating on a region exposed by the photoresist pattern; forming a solder layer by performing a secondary electroplating on the pillars; removing the photoresist pattern; forming solder bumps, in which solders partially cover surfaces of the pillars, by performing a reflow process on the semiconductor substrate; and removing portions of the seed layer formed in regions other than the solder bumps. | 11-22-2012 |
20130000978 | Joint Structures Having Organic Preservative Films - The inventive concept provides methods for inhibiting the formation of one or more oxides on metal bumps during the formation of solder joint structures and solder joint structures including one or more preservative films. In some embodiments, the solder joint structure includes a metal bump having a preservative film disposed on the surface thereof. | 01-03-2013 |
20130075905 | Semiconductor Chips and Semiconductor Packages and Methods of Fabricating the Same - A semiconductor device includes a substrate and a through via penetrating the substrate. The through via has a protruding portion at a first end thereof extending out from a first surface of the substrate and a second end of the via contacting an interconnection line proximate a second, opposite, end of the substrate. A wetting layer is positioned between the via and the substrate and extends over the protruding portion of the via. The wetting layer includes a material selected to improve an adhesive strength between the wetting layer and a solder ball contacting the wetting layer extending over the protruding portion of the via when a solder ball is coupled to the wetting layer. | 03-28-2013 |
20130313707 | Electrical Interconnections of Semiconductor Devices and Methods for Fabricating the Same - Provided are electrical interconnections and methods for fabricating the same. The electrical interconnection may include a substrate including a bonding pad, a solder ball electrically connected to the bonding pad, a solder supporter on the bonding pad, a portion of the solder ball filling the solder supporter, and a metal layer between the bonding pad and the solder supporter, the metal layer having an ionization tendency lower than the bonding pad. | 11-28-2013 |
20130334656 | ELECTRICAL INTERCONNECTION STRUCTURES INCLUDING STRESS BUFFER LAYERS - Provided are electrical connection structures and methods of fabricating the same. The structures may include a substrate including a bonding pad region provided with a bonding pad and a fuse region provided with a fuse, an insulating layer provided on the substrate and including a bonding pad opening exposing the bonding pad and a fuse opening exposing the fuse region, a connection terminal provided in the bonding pad region and electrically connected to the bonding pad, and a protection layer provided on the insulating layer including a first protection layer provided within the bonding pad region and a second protection layer in the fuse opening. | 12-19-2013 |
20150012671 | STORAGE SYSTEMS AND UFS SYSTEMS CONFIGURED TO CHANGE INTERFACE MODE IN ACTIVE STATE - A storage system includes a host and a storage device. The storage device includes a device controller and a device interface. The device controller is configured to generate interface idle time information in response to a command received from a host, the interface idle time information being determined based on an estimated time to execute at least one operation at the memory storage device. The device interface is configured to output the interface idle time information to the host. | 01-08-2015 |
20150032915 | STORAGE SYSTEM INCLUDING DATA TRANSFER SPEED MANAGER AND METHOD FOR CHANGING DATA TRANSFER SPEED THEREOF - A storage system according to an exemplary embodiment of the inventive concept includes a host and a storage device. The host includes a link speed table having data transfer speed information for an application. A data transfer speed manager is configured to calculate a predetermined transfer speed based on the data transfer speed information for the application. A device driver is configured to control an operation of the storage device. A host controller is configured to change a data transfer speed of an interface based on the predetermined transfer speed provided through the device driver. | 01-29-2015 |
20150048918 | COIL UNIT FOR THIN FILM INDUCTOR, MANUFACTURING METHOD OF COIL UNIT FOR THIN FILM INDUCTOR, THIN FILM INDUCTOR AND MANUFACTURING METHOD OF THIN FILM INDUCTOR - Embodiments of the invention provide a coil unit for a thin film inductor, a manufacturing method of a coil unit for a thin film inductor, a thin film inductor, and a manufacturing method of a thin film inductor. According to an embodiment, there is provided a coil unit for a thin film inductor. The coil unit includes an insulator having a dual insulating layer of different materials, and coil patterns respectively embedded in upper and lower surfaces of the insulator. The coil patterns include a coil pattern formed of a plurality of plating layers. | 02-19-2015 |