Patent application number | Description | Published |
20090001577 | METAL LINE OF SEMICONDUCTOR DEVICE WITH A TRIPLE LAYER DIFFUSION BARRIER AND METHOD FOR FORMING THE SAME - A metal line in a semiconductor device includes an insulation layer formed on a semiconductor substrate. A metal line forming region is formed in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region and a metal line is formed to fill the metal line forming region of the insulation layer. The diffusion barrier is formed between the metal line and the insulation layer. The diffusion barrier has a structure in which a TaSi | 01-01-2009 |
20090001578 | METAL LINE OF SEMICONDUCTOR DEVICE HAVING A DIFFUSION BARRIER WITH AN AMORPHOUS TaBN LAYER AND METHOD FOR FORMING THE SAME - A metal line in a semiconductor device includes an insulation layer formed on a semiconductor substrate. A metal line forming region is formed in the insulation layer. A metal line is formed to fill the metal line forming region of the insulation layer. And a diffusion barrier that includes an amorphous TaBN layer is formed between the metal line and the insulation layer. The amorphous TaBN layer prevents a copper component from diffusing into the semiconductor substrate, thereby improving upon the characteristics and the reliability of a device. | 01-01-2009 |
20090001579 | MULTI-LAYERED METAL LINE HAVING AN IMPROVED DIFFUSION BARRIER OF A SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A multi-layered metal line of a semiconductor device and a process of forming the same are described. The multi-layered metal line includes a lower metal line formed on a semiconductor substrate. An insulation layer is subsequently formed on the semiconductor substrate including the lower metal line and has an upper metal line forming region that exposes a portion of the lower metal line. A diffusion barrier formed on a surface of the upper metal line forming region of the insulation layer. The diffusion barrier includes a W—B—N ternary layer. An upper metal line is finally formed on the diffusion barrier to fill the upper metal line forming region of the insulation layer. | 01-01-2009 |
20090001580 | METAL LINE OF SEMICONDUCTOR DEVICE HAVING A DIFFUSION BARRIER INCLUDING CRxBy AND METHOD FOR FORMING THE SAME - A metal line of a semiconductor device having a diffusion barrier including Cr | 01-01-2009 |
20090017619 | METHOD FOR MANUFACTURING METAL SILICIDE LAYER IN A SEMICONDUCTOR DEVICE - A metal suicide layer is fabricated in a semiconductor device. A first metal layer is deposited on a silicon substrate formed with an S interlayer dielectric having a contact hole through PVD. A second metal layer is deposited on the first metal layer through any one of CVD and ALD. Annealing is performed on the silicon substrate which is formed with the first and second metal layers to form the metal silicide. The portions of the second metal layer and the first metal layer which have not reacted during annealing are removed. | 01-15-2009 |
20090166870 | METAL LINE OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate and having a metal line forming region. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer. The diffusion barrier has a multi-layered structure of a V layer, a V | 07-02-2009 |
20090166871 | METAL LINE OF SEMICONDUCTOR DEVICE WITHOUT PRODUCTION OF HIGH RESISTANCE COMPOUND DUE TO METAL DIFFUSION AND METHOD FOR FORMING THE SAME - A metal line includes a lower metal line formed on a semiconductor substrate. An insulation layer is formed on the semiconductor substrate having the lower metal line, and a metal line forming region exposing at least a portion of the lower metal line is defined in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and includes a WN | 07-02-2009 |
20090269915 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE PREVENTING LOSS OF JUNCTION REGION - A method for manufacturing a semiconductor device includes forming an insulation layer having a contact hole on a semiconductor substrate. A metal silicide layer is deposited on a surface of the contact hole and the insulation layer to have a concentration gradient that changes from a silicon-rich composition to a metal-rich composition, with the lower portion of the metal silicide layer having the silicon-rich composition and the upper portion of the metal silicide layer having the metal-rich composition. The metal silicide layer is then annealed so that the compositions of metal and silicon in the metal silicide layer become uniform. | 10-29-2009 |
20090283908 | METAL LINE OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate and a metal line forming region is formed in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer, and the diffusion layer has a multi-layered structure of an Ru layer, an Ru | 11-19-2009 |
20100019386 | ELECTRICAL CONDUCTOR LINE HAVING A MULTILAYER DIFFUSION BARRIER FOR USE IN A SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - An electrical conductor having a multilayer diffusion barrier of use in a resultant semiconductor device is presented. The electrical conductor line includes an insulation layer, a diffusion barrier, and a metal line. The insulation layer is formed on a semiconductor substrate and having a metal line forming region. The diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and has a multi-layered structure made of TaN layer, an Mo | 01-28-2010 |
20100059890 | METAL LINE OF SEMICONDUCTOR DEVICE HAVING A DIFFUSION BARRIER INCLUDING CRxBy AND METHOD FOR FORMING THE SAME - A metal line of a semiconductor device having a diffusion barrier including Cr | 03-11-2010 |
20110053370 | METAL LINE OF SEMICONDUCTOR DEVICE WITHOUT PRODUCTION OF HIGH RESISTANCE COMPOUND DUE TO METAL DIFFUSION AND METHOD FOR FORMING THE SAME - A metal line includes a lower metal line formed on a semiconductor substrate. An insulation layer is formed on the semiconductor substrate having the lower metal line, and a metal line forming region exposing at least a portion of the lower metal line is defined in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and includes a WN | 03-03-2011 |
20110233781 | METAL LINE OF SEMICONDUCTOR DEVICE HAVING A DIFFUSION BARRIER WITH AN AMORPHOUS TaBN LAYER AND METHOD FOR FORMING THE SAME - A metal line in a semiconductor device includes an insulation layer formed on a semiconductor substrate. A metal line forming region is formed in the insulation layer. A metal line is formed to fill the metal line forming region of the insulation layer. And a diffusion barrier that includes an amorphous TaBN layer is formed between the metal line and the insulation layer. The amorphous TaBN layer prevents a copper component from diffusing into the semiconductor substrate, thereby improving upon the characteristics and the reliability of a device. | 09-29-2011 |
20120015516 | ELECTRICAL CONDUCTOR LINE HAVING A MULTILAYER DIFFUSION BARRIER FOR USE IN A SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - An electrical conductor having a multilayer diffusion barrier of use in a resultant semiconductor device is presented. The electrical conductor line includes an insulation layer, a diffusion barrier, and a metal line. The insulation layer is formed on a semiconductor substrate and having a metal line forming region. The diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and has a multi-layered structure made of TaN layer, an Mo | 01-19-2012 |
20140175538 | SEMICONDUCTOR APPARATUS AND FABRICATION METHOD THEREOF - A semiconductor apparatus includes a semiconductor substrate and a semiconductor layer extending along the substrate in a first direction and connecting to the semiconductor substrate, the semiconductor layer having a portion that connects to the semiconductor substrate, and a portion that does not connect to the semiconductor substrate and forms an active region floating over the semiconductor substrate. A word line formed on the active region and extends in a direction perpendicular to the first direction. Junction regions formed in the active region at both sides of the word line; and an air gap formed in a floating region between the semiconductor substrate and the active region. | 06-26-2014 |
20140374692 | SEMICONDUCTOR MEMORY APPARATUS AND FABRICATION METHOD THEREOF - Semiconductor memory apparatus and a method of fabricating the same are provided. The semiconductor memory apparatus includes a semiconductor substrate in which a cell area and a peripheral area are defined, a plurality of pillars formed in the a cell area of the semiconductor substrate to a first depth, a stepped part formed in the peripheral area to a height corresponding to the first depth, a recessed part formed in the stepped part to a second depth, and a core switching device formed in the recessed part. | 12-25-2014 |