Patent application number | Description | Published |
20120319932 | ESD Protection Device of LCD Display - The present invention discloses an ESD protection device of an LCD display. The LCD display includes a plurality of scan lines and a plurality of data lines, the scan lines and the data lines are crossed. The ESD protection device includes a discharging extension part, positioned at ends of the scan lines and the data lines, wherein a width of the discharging extension part is larger than line widths of the scan lines or the data lines; and an electro-static conducting part, positioned in peripheral of the discharging extension part, wherein the electro-static conducting part is close to the discharging extension part without touching the discharging extension part, and the electro-static conducting part is coupled to a common conducting layer to release electro-static charges on the scan lines and data lines via the common conducting layer. The present invention can enormously reduce the ESD damages on the pixel areas. | 12-20-2012 |
20130029441 | METHODS FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY SUBSTRATE AND DISPLAY PANEL - The present invention provides methods for manufacturing a thin film transistor (TFT) array substrate and a display panel. The method for manufacturing the TFT array substrate comprises the following steps: forming a plurality of gate electrodes, a gate insulating layer, a semiconductor layer, an ohmic contact layer, an electrode layer and a photo-resist layer on a transparent substrate in sequence; using a multi tone mask to pattern the photo-resist layer; forming a plurality of source electrodes and a plurality of drain electrodes at both sides of the channels, respectively; heating the photo-resist layer; etching the semiconductor layer; removing the photo-resist layer; forming a passivation layer on the channels, the source electrodes and the drain electrodes; and forming a pixel electrode layer on the passivation layer. The present invention can reduce an amount of the required masks in the fabrication process, and only one wet etching is required to etch the metal material on the TFT array substrate. | 01-31-2013 |
20130078801 | MANUFACTURE METHODS OF DOUBLE LAYER GATE ELECTRODE AND RELEVANT THIN FILM TRANSISTOR - Disclosed is a manufacture method of a double layer gate electrode by patterning the photoresist layer with a half tone mask to make thicknesses of two sides of the photoresist layer are smaller than a thickness of middle of the photoresist layer and twice wet etchings thereafter to realize the manufacture of the double layer gate electrode. The present invention also relates to a manufacture method of a thin film transistor. The manufacture methods of a double layer gate electrode and a relevant thin film transistor according to the present invention employs half tone mask and twice wet etchings thereafter for manufacturing the gate electrode to solve technical problems of high manufacture cost and great manufacture difficulty of double layer gate electrodes according to prior arts. | 03-28-2013 |
20130126467 | METHOD FOR MANUFACTURING CONDUCTIVE LINES WITH SMALL LINE-TO-LINE SPACE - The present invention discloses a method for manufacturing conductive lines with small line-to-line space. The method for manufacturing conductive lines is to coat photoresist on a conductor layer firstly, after exposure and development treatments, then further perform an ashing treatment to completely remove the corresponding part of the photoresist that is corresponding to the exposure area, and then perform an etching step for the conductor layer to form the required conductive lines. The method provided by the present invention can manufacture wire patterns that meet the requirement of small line-to-line space under a condition that the exposure apparatus has limited exposure accuracy. | 05-23-2013 |
20130128191 | DISPLAY PANEL - The present invention provides a display pane comprising a liquid crystal cell and two polarizers disposed at both sides of the liquid crystal cell, wherein one of the polarizers at one side of the liquid crystal cell includes a compensation film, and a first optical path difference R | 05-23-2013 |
20130141705 | EXPOSURE APPARATUS AND EXPOSURE METHOD - The present invention provides an exposure apparatus and an exposure method. The method comprises: utilizing an exposure light source to provide light rays to the photo-resist layer, wherein the light rays pass through the mask and the transparent substrate to reach the photo-resist layer; and utilizing a reflective plate to reflect the light rays passing through the transparent substrate and the photo-resist layer back to the photo-resist layer. The present invention can reduce a line space of a pattern of the photo-resist layer. | 06-06-2013 |
20130155364 | METHOD OF REDUCING PARASITIC CAPACITANCE OF LIQUID CRYSTAL DISPLAY DEVICE AND LIQUID CRYSTAL DISPLAY DEVICE - A method of reducing parasitic capacitance of liquid crystal display device is disclosed where the liquid crystal display device comprises a first substrate, a second substrate and a liquid crystal layer. The first substrate comprises data lines and a first transparent electrode, and the second substrate is provided with a second transparent electrode. The method comprises the following steps: A. by means of photolithography and patterning, the second transparent electrode is separated into a primary second transparent electrode and a secondary second transparent electrode; B. offering the secondary second transparent electrode the same signal to the relevant data line. The invention further relates to a liquid crystal display device and the parasitic capacitance in the data lines of the liquid crystal display device can be diminished. | 06-20-2013 |
20130155365 | LIQUID CRYSTAL DISPLAY DEVICE - A liquid crystal display device is disclosed, comprising a first substrate, a second substrate and a liquid crystal layer. The first substrate comprises gate lines and a first transparent electrode while the second substrate is provided with a second transparent electrode. Relative to the first substrate, the inner side of the second substrate is separated into a first zone and a second zone. The first zone is locations on the second substrate to which the gate lines correspond, and the second zone is located aside to the locations on the second substrate that correspond to the gate lines. The second transparent electrode is disposed in the second zone. The liquid crystal display device of the present invention is capable of reducing parasitic capacitance of gate lines preferably, enabling the signal delay to subside in the gate lines. | 06-20-2013 |
20130235317 | Patterned Vertical Alignment Pixel Electrode - A patterned vertical alignment (PVA) pixel electrode is disclosed. The PVA pixel electrode includes a first electrode and a second electrode. The first and second electrodes form a pre-tilt angle with respect to a periphery of the pixel. By disposing unequal lengths of indium-tin oxide (ITO) gaps at a periphery of the first and second electrodes, a distance between the first and second electrodes gradually becomes shortened from the center of the pixel outwards. The ITO gaps which are disposed at the periphery of a thin film transistor (TFT)-array substrate and/or a color filter (CF) are adjusted for eliminating a fringe field effect in the present invention, which a transmittance on the pixel regions is improved and an effect of image display quality is enhanced. | 09-12-2013 |
20140146259 | LCD DEVICE, ARRAY SUBSTRATE, AND METHOD FOR MANUFACTURING THE ARRAY SUBSTRATE - The present disclosure provides a liquid crystal display device, an array substrate, and a method for manufacturing the array substrate. The array substrate includes a glass substrate, gate scan lines formed on the glass substrate, and a pixel electrode. An edge of the pixel electrode has an overlapping region with the gate scan lines, and the pixel electrode and the gate scan lines form a parasitic capacitance in the overlapping region. The overlapping region between the pixel electrode and the gate scan lines is configured with at least one protection layer that reduces the parasitic capacitance. | 05-29-2014 |