| Patent application number | Description | Published |
|---|
| 20100130021 | METHOD FOR PROCESSING A SILICON-ON-INSULATOR STRUCTURE - A method is disclosed for processing the cleaved surface of a silicon-on-insulator structure. The silicon-on-insulator structures comprises a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer. The silicon layer has a cleaved surface defining an outer surface of the structure. The methods disclosed include an etching process to reduce the time and cost required to process the silicon-on-insulator structure to remove the surface damage and defects formed when a portion of the donor wafer is separated along a cleave plane from the silicon-on-insulator structure. The method includes, annealing the structure, etching the cleaved surface, and performing a non-contact smoothing process on the cleaved surface. | 05-27-2010 |
| 20110151592 | METHODS FOR MONITORING THE AMOUNT OF CONTAMINATION IMPARTED INTO SEMICONDUCTOR WAFERS DURING WAFER PROCESSING - Methods are disclosed for monitoring the amount of metal contamination imparted during wafer processing operations such as polishing and cleaning. The methods include subjecting a silicon-on-insulator structure to the semiconductor process, precipitating metal contamination in the structure and delineating the metal contaminants. | 06-23-2011 |
| 20110159665 | METHOD FOR THE PREPARATION OF A MULTI-LAYERED CRYSTALLINE STRUCTURE - This invention generally relates to a process for making a multi-layered crystalline structure. The process includes implanting ions into a donor structure, bonding the implanted donor structure to a second structure to form a bonded structure, cleaving the bonded structure, and removing any residual portion of the donor structure from the finished multi-layered crystalline structure. | 06-30-2011 |
| 20110212547 | METHODS FOR MONITORING THE AMOUNT OF METAL CONTAMINATION IMPARTED INTO WAFERS DURING A SEMICONDUCTOR PROCESS - Methods are disclosed for monitoring the amount of metal contamination imparted during wafer processing operations such as polishing and cleaning. The methods include subjecting a silicon-on-insulator structure to the semiconductor process, precipitating metal contamination in the structure and delineating the metal contaminants. | 09-01-2011 |
| 20110212550 | METHODS FOR DETECTING METAL PRECIPITATES IN A SEMICONDUCTOR WAFER - Methods are disclosed for monitoring the amount of metal contamination imparted during wafer processing operations such as polishing and cleaning. The methods include subjecting a silicon-on-insulator structure to the semiconductor process, precipitating metal contamination in the structure and delineating the metal contaminants. | 09-01-2011 |
| 20120115258 | METHODS FOR MONITORING THE AMOUNT OF METAL CONTAMINATION IN A PROCESS - Methods are disclosed for monitoring the amount of metal contamination imparted during wafer processing operations such as polishing and cleaning. The methods include subjecting a silicon-on-insulator structure to the semiconductor process, precipitating metal contamination in the structure and delineating the metal contaminants. | 05-10-2012 |
| 20120235283 | SILICON ON INSULATOR STRUCTURES HAVING HIGH RESISTIVITY REGIONS IN THE HANDLE WAFER - Silicon on insulator structures having a high resistivity region in the handle wafer of the silicon on insulator structure are disclosed. Methods for producing such silicon on insulator structures are also provided. Exemplary methods involve creating a non-uniform thermal donor profile and/or modifying the dopant profile of the handle wafer to create a new resistivity profile in the handle wafer. Methods may involve one or more SOI manufacturing steps or electronic device (e.g., RF device) manufacturing steps. | 09-20-2012 |
| 20120238070 | METHODS FOR PRODUCING SILICON ON INSULATOR STRUCTURES HAVING HIGH RESISTIVITY REGIONS IN THE HANDLE WAFER - Silicon on insulator structures having a high resistivity region in the handle wafer of the silicon on insulator structure are disclosed. Methods for producing such silicon on insulator structures are also provided. Exemplary methods involve creating a non-uniform thermal donor profile and/or modifying the dopant profile of the handle wafer to create a new resistivity profile in the handle wafer. Methods may involve one or more SOI manufacturing steps or electronic device (e.g., RF device) manufacturing steps. | 09-20-2012 |
| 20130062020 | Systems and Methods for Cleaving A Bonded Wafer Pair - Systems and methods are provided for mechanically cleaving a bonded wafer pair by controlling the rate of cleaving. This controlled rate of cleaving results in a reduction or elimination of non-uniform thickness variations in the cleaved surface of the resulting SOI wafer. One embodiment uses flexible chucks attached to the faces of the wafers and actuators attached to the flexible chucks to cleave the bonded wafer pair. Other embodiments also use rollers in contact with the surfaces to control the rate of cleaving. | 03-14-2013 |
| 20130105538 | METHODS FOR CLEAVING A BONDED WAFER STRUCTURE | 05-02-2013 |
| 20130105539 | CLAMPING APPARATUS FOR CLEAVING A BONDED WAFER STRUCTURE | 05-02-2013 |
| 20130137241 | METHOD FOR THE PREPARATION OF A MULTI-LAYERED CRYSTALLINE STRUCTURE - This invention generally relates to a process for making a multi-layered crystalline structure. The process includes implanting ions into a donor structure, bonding the implanted donor structure to a second structure to form a bonded structure, cleaving the bonded structure, and removing any residual portion of the donor structure from the finished multi-layered crystalline structure. | 05-30-2013 |
| 20130237032 | Method of Manufacturing Silicon-On-Insulator Wafers - A method is provided for preparing multilayer semiconductor structures, such as silicon-on-insulator wafers, having reduced warp and bow. Reduced warp multilayer semiconductor structures are prepared by forming a dielectric structure on the exterior surfaces of a bonded pair of a semiconductor device substrate and a semiconductor handle substrate having an intervening dielectric layer therein. Forming a dielectric layer on the exterior surfaces of the bonded pair offsets stresses that may occur within the bulk of the semiconductor handle substrate due to thermal mismatch between the semiconductor material and the intervening dielectric layer as the structure cools from process temperatures to room temperatures. | 09-12-2013 |
| 20140187020 | METHOD FOR LOW TEMPERATURE LAYER TRANSFER IN THE PREPARATION OF MULTILAYER SEMICONDUTOR DEVICES - A method of preparing a monocrystalline donor substrate, the method comprising (a) implanting helium ions through the front surface of the monocrystalline donor substrate to an average depth D | 07-03-2014 |
| 20140273405 | SEMICONDUCTOR-ON-INSULATOR WAFER MANUFACTURING METHOD FOR REDUCING LIGHT POINT DEFECTS AND SURFACE ROUGHNESS - A method for reducing light point defects of a semiconductor-on-insulator structure and a method for reducing the surface roughness of a semiconductor-on-insulator structure are disclosed. The methods can include a combination of thermally annealing the structure followed by a non-contact smoothing process. | 09-18-2014 |
| 20140327112 | METHOD TO DELINEATE CRYSTAL RELATED DEFECTS - Process for detecting grown-in-defects in a semiconductor silicon substrate. The process includes contacting a surface of the semiconductor silicon substrate with a gaseous acid in a reducing atmosphere at a temperature and duration sufficient to grow grown-in -defects disposed in the semiconductor silicon substrate to a size capable of being detected by an optical detection device. | 11-06-2014 |
