Patent application number | Description | Published |
20140054724 | ALIGNED GATE-ALL-AROUND STRUCTURE - Among other things, a semiconductor device comprising an aligned gate and a method for forming the semiconductor device are provided. The semiconductor device comprises a gate formed according to a multi-gate structure, such as a gate-all-around structure. A first gate portion of the gate is formed above a first channel of the semiconductor device. A second gate portion of the gate is formed below the first channel, and is aligned with the first gate portion. In an example of forming the gate, a cavity is etched within a semiconductor layer formed above a substrate. A dielectric layer is formed around at least some of the cavity to define a region of the cavity within which the second gate portion is to be formed in a self-aligned manner with the first gate portion. In this way, the semiconductor device comprises a first gate portion aligned with a second gate portion. | 02-27-2014 |
20140138780 | FINFET HAVING UNIFORM DOPING PROFILE AND METHOD OF FORMING THE SAME - An embodiment fin field effect transistor (FinFET) device and method of forming the same. An embodiment method of forming a fin field effect transistor (FinFET) includes forming fins from a semiconductor substrate, forming a field oxide between the fins, forming a sacrificial gate over a channel region of the fins projecting from the field oxide, and implanting ions through the sacrificial gate to provide the channel region of the fins with a uniform doping profile. | 05-22-2014 |
20140183643 | Transistors with Wrapped-Around Gates and Methods for Forming the Same - A device includes a substrate, a semiconductor strip over the substrate, a gate dielectric wrapping around the semiconductor strip, and a gate electrode wrapping around the gate dielectric. A dielectric region is overlapped by the semiconductor strip. The semiconductor strip and the dielectric region are spaced apart from each other by a bottom portion of the gate dielectric and a bottom portion of the gate electrode. | 07-03-2014 |
20140312388 | Apparatus and Method for Forming Semiconductor Contacts - A method for forming semiconductor contacts comprises forming a germanium fin structure over a silicon substrate, depositing a doped amorphous silicon layer over the first drain/source region and the second drain/source region at a first temperature, wherein the first temperature is lower than a melting point of the germanium fin structure and performing a solid phase epitaxial regrowth process on the amorphous silicon layer at a second temperature, wherein the second temperature is lower than the melting point of the germanium fin structure. | 10-23-2014 |
20140332859 | Self-Aligned Wrapped-Around Structure - An embodiment vertical wrapped-around structure and method of making. An embodiment method of making a self-aligned vertical structure-all-around device including forming a spacer around an exposed portion of a semiconductor column projecting from a structure layer, forming a photoresist over a protected portion of the structure layer and a first portion of the spacer, etching away an unprotected portion of the structure layer disposed outside a periphery collectively defined by the spacer and the photoresist to form a structure having a footer portion and a non-footer portion, the non-footer portion and the footer portion collectively encircling the semiconductor column, and removing the photoresist and the spacer. | 11-13-2014 |
20140353731 | Tuning Strain in Semiconductor Devices - A Fin Field-Effect Transistor (FinFET) includes a semiconductor layer over a substrate, wherein the semiconductor layer forms a channel of the FinFET. A first silicon germanium oxide layer is over the substrate, wherein the first silicon germanium oxide layer has a first germanium percentage. A second silicon germanium oxide layer is over the first silicon germanium oxide layer. The second silicon germanium oxide layer has a second germanium percentage greater than the first germanium percentage. A gate dielectric is on sidewalls and a top surface of the semiconductor layer. A gate electrode is over the gate dielectric. | 12-04-2014 |
20150021697 | Thermally Tuning Strain in Semiconductor Devices - A method includes performing a first epitaxy to grow a silicon germanium layer over a semiconductor substrate, performing a second epitaxy to grow a silicon layer over the silicon germanium layer, and performing a first oxidation to oxidize the silicon germanium layer, wherein first silicon germanium oxide regions are generated. A strain releasing operation is performed to release a strain caused by the first silicon germanium oxide regions. A gate dielectric is formed on a top surface and a sidewall of the silicon layer. A gate electrode is formed over the gate dielectric. | 01-22-2015 |
20150048453 | FinFETs and Methods for Forming the Same - Embodiments of the present disclosure include a semiconductor device, a FinFET device, and methods for forming the same. An embodiment is a semiconductor device including a first semiconductor fin extending above a substrate, the first semiconductor fin having a first lattice constant, an isolation region surrounding the first semiconductor fin, and a first source/drain region in the first semiconductor fin, the first source/drain having a second lattice constant different from the first lattice constant. The semiconductor device further includes a first oxide region along a bottom surface of the first source/drain region, the first oxide region extending into the isolation region. | 02-19-2015 |