Patent application number | Description | Published |
20110149661 | MEMORY ARRAY HAVING EXTENDED WRITE OPERATION - In some embodiments, an apparatus comprising a memory array of static random access memory (SRAM) cells arranged in a plurality of rows and a plurality of columns and configured to receive a clock signal having a plurality of clock cycles; a plurality of word-lines associated with the plurality of rows of the SRAM cells; and a selected word-line driver configured during an extended write operation to drive a selected one of the plurality of word-lines with a write word-line signal having an extended duration. Other embodiments may be described and claimed. | 06-23-2011 |
20110317508 | MEMORY WRITE OPERATION METHODS AND CIRCUITS - In some embodiments, write wordline boost may be obtained from wordline driver boost and/or from bit line access transistor boost. | 12-29-2011 |
20120151235 | METHODS AND SYSTEMS FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING ENTRY AND EXIT LATENCY REDUCTION FOR LOW POWER STATES - Systems and methods for entry and exit latency reduction for low power states are described. In one embodiment, a computer implemented method initiates an energy-efficient low power state (e.g., deep sleep state) to reduce power consumption of a device. The method sets a power supply voltage that provides sufficient power to a dual power supply array for retention of states. Logic is powered down in this low power state. | 06-14-2012 |
20130003469 | CIRCUITS AND METHODS FOR MEMORY - Embodiments for data dependent boosted (DDB) bit cells that may allow for smaller minimum cell supplies (Vmin) without necessarily having to increase device dimensions are presented. | 01-03-2013 |
20130262768 | ADAPTIVE SELF-REPAIRING CACHE - A method for operating a cache that includes both robust cells and standard cells may include receiving a data to be written to the cache, determining whether a type of the data is unmodified data or modified data, and writing the data to robust cells or standard cells as a function of the type of the data. A processor includes a core that includes a cache including both robust cells and standard cells for receiving data, wherein the data is written to robust cells or standard cells as a function of whether a type of the data is determined to be unmodified data or modified data. | 10-03-2013 |
20140003132 | APPARATUS FOR REDUCING WRITE MINIMUM SUPPLY VOLTAGE FOR MEMORY | 01-02-2014 |
20140032980 | RESILIENT REGISTER FILE CIRCUIT FOR DYNAMIC VARIATION TOLERANCE AND METHOD OF OPERATING THE SAME - The disclosed system and method detect and correct register file read path errors that may occur as a result of reducing or eliminating supply voltage guardbands and/or frequency guardbands for a CPU, thereby increasing overall energy efficiency of the system. | 01-30-2014 |
20140218069 | MULTI-SUPPLY SEQUENTIAL LOGIC UNIT - Described herein are apparatus, method, and system for reducing clock-to-output delay of a sequential logic unit in a processor. The apparatus comprises a sequential unit including: a data path, to receive an input signal, including logic gates to operate on a first power supply level, the data path to generate an output signal; and a clock path including logic gates to operate on a second power supply level, the logic gates of the clock path to sample the input signal using a sampling signal to generate the output signal, wherein the second power supply level is higher than the first power supply level. The apparatus improves (i.e. reduces) setup time of the sequential unit and allows the processor to operate at minimum operating voltage (Vmin) without degrading performance of the sequential unit. | 08-07-2014 |
20150009751 | METHODS AND SYSTEMS TO SELECTIVELY BOOST AN OPERATING VOLTAGE OF, AND CONTROLS TO AN 8T BIT-CELL ARRAY AND/OR OTHER LOGIC BLOCKS - Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase. | 01-08-2015 |