Patent application number | Description | Published |
20100204339 | Orally Bioavailable Stilbenoids- Compositions and Therapeutic Applications Thereof - Disclosed is a novel sirtuin modulating composition comprising an orally bioavailable SIRT-1 enhancing compound 3,5-dimethoxy-3,4′-dihydroxystilbene represented by STR#I. Also disclosed is an anti-acne composition comprising 3,5-dimethoxy- 3,4′-dihydroxystilbenes represented by STR#I. Further, a novel sirtuin modulating composition comprising an orally bioavailable SIRT-1 enhancing compound 2,3′,5′, 6-tetrahydroxy-trans-stilbene represented by STR#II is also disclosed. | 08-12-2010 |
20100204340 | ORALLY BIOAVAILABLE STILBENOIDS- COMPOSITIONS AND THERAPEUTIC APPLICATIONS THEREOF - A novel, bioavailable and safe stilbenoid 3,5-dimethoxy-3,4′-dihydroxystilbene represented by STR#1 with an unexpected enhanced ability to prevent the accumulation of lipids accompanying the terminal differentiation of adipocytes, thereby inhibiting adipogenesis, and nutraceutical and cosmeceutical compositions comprising 3,5-dimethoxy-3,4′-dihydroxystilbene useful for anti-obesity and anti-cellulite therapy, are disclosed. Further the enhanced SIRT-1 activation ability of 3,5-dimethoxy-3,4′-dihydroxystilbene represented by STR#1 and 2,3′,5′,6-tetrahydroxy-trans-stilbene represented by STR#II are disclosed. The enhancement of SIRT-1 polypeptide activity of the said compounds is unexpectedly much higher than resveratrol or its natural analog pterostilbene. Sirtuin modulating compositions comprising an orally bioavailable SIRT-1 enhancing compounds (i) 3,5-dimethoxy-3,4′-dihydroxystilbene represented by STR#I and (ii) 2,3′,5′,6-tetrahydroxy-trans-stilbene represented by STR#II are also disclosed. An additional embodiment, also discloses the enhanced anti-Propionibacterium acnes activity of 3,5-dimethoxy-3,4′-dihydroxystilbenes represented by STR#I and compositions thereof. | 08-12-2010 |
20130017605 | ORALLY BIOAVAILABLE STILBENOIDS- COMPOSITIONS AND THERAPEUTIC APPLICATIONS THEREOF - A novel, bioavailable and safe stilbenoid 3,5-dimethoxy-3,4′-dihydroxystilbene represented by SIR#1 with an unexpected enhanced ability to prevent the accumulation of lipids accompanying the terminal differentiation of adipocytes, thereby inhibiting adipogenesis, and nutraceutical and cosmeceutical compositions comprising, dimethoxy-3,4′-dihydroxystilbene useful for anti-obesity and anti-cellulite therapy, are disclosed. Further the enhanced SIRT-1 activation ability of 3,5-dimethoxy-3,4′-dihydroxystilbene represented by STR#1 and 2,3′,5′,6-tetrahydroxy-trans-stilbene represented by STR#II are disclosed. The enhancement of SIRT-1 polypeptide activity of the said compounds is unexpectedly much higher than resveratrol or its natural analog pterostilbene. Sirtuin modulating compositions comprising an orally bioavailable SIRT-1 enhancing compounds (i) 3,5-dimethoxy-3,4′-dihydroxystilbene represented by STR#I and (ii) 2,3′,5′,6-tetrahydroxy-trans-stilbene represented by are also disclosed. An additional embodiment, also discloses the enhanced anti- | 01-17-2013 |
20130217782 | Orally bioavailable stilbenoids-Compositions and therapeutic applications thereof - Disclosed is a novel sirtuin modulating composition comprising an orally bioavailable SIRT-1 enhancing compound 3,5-dimethoxy-3,4′-dihydroxystilbene represented by STR#I. Also disclosed is an anti-acne composition comprising 3,5-dimethoxy-3,4′-dihydroxystilbenes represented by STR#I. Further, a novel sirtuin modulating composition comprising an orally bioavailable SIRT-1 enhancing compound 2,3′,5′,6-tetrahydroxy-trans-stilbene represented by STR#II is also disclosed. | 08-22-2013 |
Patent application number | Description | Published |
20120330616 | FREQUENCY GUARD BAND VALIDATION OF PROCESSORS - A frequency guard band validation unit can determine whether at least one of a plurality of previously validated processors was validated on a first system having a substantially similar configuration as a second system in which an unvalidated processor is being tested. If at least one of the plurality of previously validated processors was validated on the first system, a validation start frequency associated with the unvalidated processor can be computed based, at least in part, on system parametric data associated with a subset of the plurality of previously validated processors that were validated on the first system. Otherwise, the validation start frequency associated with the unvalidated processor is computed based, at least in part, on tester parametric data associated with the unvalidated processor. Validation of the guard band frequency for the unvalidated processor is initiated at the validation start frequency. This can reduce the overall validation cycle time. | 12-27-2012 |
20130103354 | DETECTING CROSS-TALK ON PROCESSOR LINKS - A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a quiet data pattern is transmitted via a second set of the remainder processor links. If performance of the first data lane increases vis-à-vis the corresponding base performance measurement, the first set of remainder processor links is eliminated from the remainder processor links. If performance of the first data lanes decreases vis-à-vis the corresponding base performance measurement, the second set of remainder processor links is eliminated from the remainder processor links. The above operations are repeatedly executed until an aggressor processor link that is determined to decrease performance of the first of the plurality of data lanes is identified. | 04-25-2013 |
20130103927 | CHARACTERIZATION AND VALIDATION OF PROCESSOR LINKS - A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link. | 04-25-2013 |
20140053016 | Using A Buffer To Replace Failed Memory Cells In A Memory Component - Methods and data processing systems for using a buffer to replace failed memory cells in a memory component are provided. Embodiments include determining that a first copy of data stored within a plurality of memory cells of a memory component contains one or more errors; in response to determining that the first copy contains one or more errors, determining whether a backup cache within the buffer contains a second copy of the data; and in response to determining that the backup cache contains the second copy of the data, transferring the second copy from the backup cache to a location within an error data queue (EDQ) within the buffer and updating the buffer controller to use the location within the EDQ instead of the plurality of memory cells within the memory component. | 02-20-2014 |
20140059327 | DETECTING CROSS-TALK ON PROCESSOR LINKS - A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a quiet data pattern is transmitted via a second set of the remainder processor links. If performance of the first data lane increases vis-à-vis the corresponding base performance measurement, the first set of remainder processor links is eliminated from the remainder processor links. If performance of the first data lanes decreases vis-à-vis the corresponding base performance measurement, the second set of remainder processor links is eliminated from the remainder processor links. The above operations are repeatedly executed until an aggressor processor link that is determined to decrease performance of the first of the plurality of data lanes is identified. | 02-27-2014 |
20140082335 | CHARACTERIZATION AND VALIDATION OF PROCESSOR LINKS - A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link. | 03-20-2014 |
20140112754 | Thermal Control System Based on Nonlinear Zonal Fan Operation and Optimized Fan Power - An approach is provided in which a cooling manager retrieves pre-characterization data corresponding to a fan that electronic components included in a computer system. The pre-characterization data includes operational zones based upon fan power measurements and fan speed settings. The cooling manager sets the fan to a first speed setting within a first operational zone, and detects that one of the components generates a temperature change value that exceeds a specified temperature change value corresponding to the component. In turn, the cooling manager selects a second operational zone and sets the fan to a second speed setting within the second operational zone. | 04-24-2014 |
20140114496 | Thermal Control System Based on Nonlinear Zonal Fan Operation and Optimized Fan Power - An approach is provided in which a cooling manager retrieves pre-characterization data corresponding to a fan that electronic components included in a computer system. The pre-characterization data includes operational zones based upon fan power measurements and fan speed settings. The cooling manager sets the fan to a first speed setting within a first operational zone, and detects that one of the components generates a temperature change value that exceeds a specified temperature change value corresponding to the component. In turn, the cooling manager selects a second operational zone and sets the fan to a second speed setting within the second operational zone. | 04-24-2014 |
20140157044 | IMPLEMENTING DRAM FAILURE SCENARIOS MITIGATION BY USING BUFFER TECHNIQUES DELAYING USAGE OF RAS FEATURES IN COMPUTER SYSTEMS - A method, system and computer program product are provided for implementing dynamic random access memory (DRAM) failure scenarios mitigation using buffer techniques delaying usage of RAS features in computer systems. A buffer is provided with a memory controller. Physical address data read/write failures are analyzed. Responsive to identifying predefined failure types for physical address data read/write failures, the buffer is used to selectively store and retrieve data. | 06-05-2014 |
20140359241 | MEMORY DATA MANAGEMENT - A method and computer-readable storage media are provided for rearranging data in physical memory units. In one embodiment, a method may include monitoring utilization counters. The method may further include, comparing the utilization counters for a match with an instance in a first table containing one or more instances when data may be rearranged in the physical memory units. The table may further include where the data should be relocated by a rearrangement. The method may also include, continuing to monitor the utilization counters if a match is not found with an instance in the first table. The method may further include, rearranging the data in the physical memory units if a match between the utilization counters and an instance in the first table is found. | 12-04-2014 |
20140359310 | SUBSYSTEM-LEVEL POWER MANAGEMENT IN A MULTI-NODE VIRTUAL MACHINE ENVIRONMENT - A computer-implemented method includes capping the amount of power available to each of a plurality of compute nodes, and managing power allocation among subsystems within each of the compute nodes according to the requirements of workloads assigned to each of the compute nodes. The method further comprises reporting an actual performance level and performance capability for each subsystem within each of the plurality of compute nodes, and monitoring parametric data for a particular workload. A target compute node is identified from among the compute nodes, wherein the target compute node would be capable of performing the particular workload if power was reallocated from a first subsystem to a second subsystem within the target compute node. The particular workload is then assigned to the target compute node. Optionally, assigning the particular workload may include migrating the workload to the target compute node from another of the compute nodes. | 12-04-2014 |
20140379288 | CHARACTERIZATION AND VALIDATION OF PROCESSOR LINKS - A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link. | 12-25-2014 |
20150057975 | FREQUENCY GUARD BAND VALIDATION OF PROCESSORS - It is determined that a guard band frequency for a first processor is to be determined. The guard band frequency is associated with a first system configuration. A validation start frequency is determined based, at least in part, on data associated with at least one of the first processor or a second processor. The validation start frequency is between a nominal operating frequency for the first processor and a system maximum operating frequency for the first processor. A guard band frequency for the second processor was previously determined. The guard band frequency for the first processor is determined based, at least in part, on the validation start frequency. | 02-26-2015 |
20150192981 | SYSTEM INTERCONNECT DYNAMIC SCALING BY PREDICTING I/O REQUIREMENTS - Interface management techniques provide reduced power consumption along with reducing heat and EMI generation in a computer system having multiple interconnected processing units. Physical link layers of external interfaces that interconnect the processing units of have dynamically adjustable bandwidth and the bandwidths are dynamically adjusted by predicting interface bandwidth requirements. An interface control method detects events other than I/O requests that occur in a processing unit that are indicators of potential future transactions on one of the external interfaces connected to the processing unit. The method predicts, from the detected events, that future transactions will likely occur on the interface, and in response, controls the dynamically adjustable bandwidth of physical link layer of the interface to accommodate the future transactions. | 07-09-2015 |
20150193287 | BUS INTERFACE OPTIMIZATION BY SELECTING BIT-LANES HAVING BEST PERFORMANCE MARGINS - A bus interface selects bit-lanes to allocate as spares by testing the performance margins of individual bit-lanes during initialization or calibration of the bus interface. The performance margins of the individual bit-lanes are evaluated as the operating frequency of the interface is increased until a number of remaining bit-lanes that meet specified performance margins is equal to the required width of the interface. The bit-lanes that do not meet the required performance margins are allocated as spares and the interface can be operated at the highest evaluated operating frequency. When an operating bit-lane fails, one of the spare bit-lanes is allocated as a replacement bit-lane and the interface operating frequency is reduced to a frequency at which the new set of operating bit-lanes meets the performance margins. The operating frequency of the interface can be dynamically increased and decreased during operation and the performance margins evaluated to optimize performance. | 07-09-2015 |
20150193316 | BUS INTERFACE OPTIMIZATION BY SELECTING BIT-LANES HAVING BEST PERFORMANCE MARGINS - A bus interface selects bit-lanes to allocate as spares by testing the performance margins of individual bit-lanes during initialization or calibration of the bus interface. The performance margins of the individual bit-lanes are evaluated as the operating frequency of the interface is increased until a number of remaining bit-lanes that meet specified performance margins is equal to the required width of the interface. The bit-lanes that do not meet the required performance margins are allocated as spares and the interface can be operated at the highest evaluated operating frequency. When an operating bit-lane fails, one of the spare bit-lanes is allocated as a replacement bit-lane and the interface operating frequency is reduced to a frequency at which the new set of operating bit-lanes meets the performance margins. The operating frequency of the interface can be dynamically increased and decreased during operation and the performance margins evaluated to optimize performance. | 07-09-2015 |
20150193690 | SYSTEM INTERCONNECT DYNAMIC SCALING BY PREDICTING I/O REQUIREMENTS - Interface management techniques provide reduced power consumption along with reducing heat and EMI generation in a computer system having multiple interconnected processing units. Physical link layers of external interfaces that interconnect the processing units of have dynamically adjustable bandwidth and the bandwidths are dynamically adjusted by predicting interface bandwidth requirements. An interface controller detects events other than I/O requests that occur in a processing unit that are indicators of potential future transactions on one of the external interfaces connected to the processing unit. The interface controller predicts, from the detected events, that future transactions will likely occur on the interface, and in response, controls the dynamically adjustable bandwidth of physical link layer of the interface to accommodate the future transactions. | 07-09-2015 |
20150205730 | IMPLEMENTING ENHANCED SECURITY WITH STORING DATA IN DRAMs - A method, system and memory controller for implementing enhanced security in a memory subsystem including DRAM in a computer system. A memory includes a register to hold scrambling information transmitted from a memory controller; and scrambling circuitry on the memory to scramble at least one of bank select bits and data bits responsive to the scrambling information in the register. | 07-23-2015 |
20150205731 | IMPLEMENTING ENHANCED SECURITY WITH STORING DATA IN DRAMs - A method, system and memory controller for implementing enhanced security in a memory subsystem including DRAM in a computer system. A memory includes a register to hold scrambling information transmitted from a memory controller; and scrambling circuitry on the memory to scramble at least one of bank select bits and data bits responsive to the scrambling information in the register. | 07-23-2015 |
20150279433 | ALLOCATING MEMORY ADDRESS SPACE BETWEEN DIMMS USING MEMORY CONTROLLERS - A memory controller enters a memory mode, allocating memory address space within a pair of DIMMs such that each DIMM of the pair contains unallocated memory address space corresponding to allocated memory space in the other DIMM. The memory controller enters another memory mode, modifying the allocation of the memory address space from a first DIMM of the pair of DIMMs to a second DIMM of the pair of DIMMs. The data is moved from allocated memory address space of the first DIMM to unallocated memory address space in the second DIMM. | 10-01-2015 |
20150279461 | ALLOCATING MEMORY ADDRESS SPACE BETWEEN DIMMS USING MEMORY CONTROLLERS - A memory controller enters a memory mode, allocating memory address space within a pair of DIMMs such that each DIMM of the pair contains unallocated memory address space corresponding to allocated memory space in the other DIMM. The memory controller enters another memory mode, modifying the allocation of the memory address space from a first DIMM of the pair of DIMMs to a second DIMM of the pair of DIMMs. The data is moved from allocated memory address space of the first DIMM to unallocated memory address space in the second DIMM. | 10-01-2015 |
20150301575 | SYSTEM INTERCONNECT DYNAMIC SCALING BY LANE WIDTH AND OPERATING FREQUENCY BALANCING - Interface management techniques provide reduced power consumption along with reducing heat and EMI generation in a computer system having multiple interconnected processing units. Physical link layers of external interfaces that interconnect the processing units have dynamically adjustable bandwidth provided by an adjustable width and adjustable operating frequency. The bandwidths may be dynamically adjusted by predicting interface bandwidth requirements. From a required bandwidth, an active width and an operating frequency for the physical link layers are determined and set. The interface is operated according to the determined width and operating frequency. | 10-22-2015 |
20150301576 | SYSTEM INTERCONNECT DYNAMIC SCALING BY LANE WIDTH AND OPERATING FREQUENCY BALANCING - Interface management techniques provide reduced power consumption along with reducing heat and EMI generation in a computer system having multiple interconnected processing units. Physical link layers of external interfaces that interconnect the processing units have dynamically adjustable bandwidth provided by an adjustable width and adjustable operating frequency. The bandwidths may be dynamically adjusted by predicting interface bandwidth requirements. From a required bandwidth, an active width and an operating frequency for the physical link layers are determined and set. The interface is operated according to the determined width and operating frequency. | 10-22-2015 |
20150316970 | BUDGETING FOR POWER CONSUMPTION IN A CHASSIS ENVIRONMENT THAT INCLUDES A PLURALITY OF INTEGRATED TECHNOLOGY ELEMENTS - Methods, apparatuses, and products for budgeting for power consumption in a chassis environment that includes a plurality of integrated technology elements (‘ITEs’), each ITE having power utilization information indicating an average power consumption of the ITE, including: determining, by a chassis management module, a total power requirement value based on a sum of the average power consumption for each ITE; increasing, by the chassis management module, the total power requirement value in dependence upon a predetermined power utilization delta; identifying, by the chassis management module, one or more power supplies to provide power to the ITEs in the chassis environment in dependence upon power delivery capabilities of the one or more power supplies and the total power requirement value; and powering on the identified one or more power supplies by the chassis management module. | 11-05-2015 |
20150355847 | TRANSFER SIZE MONITOR, DETERMINATION, AND OPTIMIZATION ENGINE FOR STORAGE DEVICES - A method of monitoring, optimizing, and dynamically varying transfer size in a storage device is provided, including: receiving data transfer parameters for a Solid State Disk (SSD) device; selecting a data transfer size from the disk characterization data associated with the SSD device, based on a SSD device identifier in the received data transfer parameters matching the SSD device identifier in the disk characterization data; searching a weight-age table for a process identifier (PID) matching the PID from the received data transfer parameters; determining a heuristic representing a statistical distribution of Input/Output (I/O) operations per second (IOPS) and transfer sizes over time; modifying the received data transfer parameters based on at least one of: the selected data transfer size from the disk characterization data; the weight-age table; and the heuristic; and completing one or more (I/O) operations with the SSD device using the modified data transfer parameters. | 12-10-2015 |
20150355861 | TRANSFER SIZE MONITOR, DETERMINATION, AND OPTIMIZATION ENGINE FOR STORAGE DEVICES - A method of monitoring, optimizing, and dynamically varying transfer size in a storage device is provided, including: receiving data transfer parameters for a Solid State Disk (SSD) device; selecting a data transfer size from the disk characterization data associated with the SSD device, based on a SSD device identifier in the received data transfer parameters matching the SSD device identifier in the disk characterization data; searching a weight-age table for a process identifier (PID) matching the PID from the received data transfer parameters; determining a heuristic representing a statistical distribution of Input/Output (I/O) operations per second (IOPS) and transfer sizes over time; modifying the received data transfer parameters based on at least one of: the selected data transfer size from the disk characterization data; the weight-age table; and the heuristic; and completing one or more (I/O) operations with the SSD device using the modified data transfer parameters. | 12-10-2015 |
20150362971 | BUDGETING FOR POWER CONSUMPTION IN A CHASSIS ENVIRONMENT THAT INCLUDES A PLURALITY OF INTEGRATED TECHNOLOGY ELEMENTS - Methods, apparatuses, and products for budgeting for power consumption in a chassis environment that includes a plurality of integrated technology elements (‘ITEs’), each ITE having power utilization information indicating an average power consumption of the ITE, including: determining, by a chassis management module, a total power requirement value based on a sum of the average power consumption for each ITE; increasing, by the chassis management module, the total power requirement value in dependence upon a predetermined power utilization delta; identifying, by the chassis management module, one or more power supplies to provide power to the ITEs in the chassis environment in dependence upon power delivery capabilities of the one or more power supplies and the total power requirement value; and powering on the identified one or more power supplies by the chassis management module. | 12-17-2015 |
20160048473 | SYSTEM INTERCONNECT DYNAMIC SCALING HANDSHAKE USING SPARE BIT-LANE - A communications technique using spare bit-lanes to communicate changes in interface physical link layer bandwidth and/or active width provides for dynamic adjustment of power consumption of interface links without requiring a separate control path for exchanging the change information. One or more spare bit-lanes are used to communicate an indication of the operating frequency/active width change to the physical link layer of the remote side of the interface and an acknowledgement is sent back to provide complete handshaking of the operating characteristic change. The method can determine whether or not a spare bit-lane is available and prevent making the change if a spare bit-lane is not available until the interface is repaired and a spare bit-lane can then be used for communicating operating changes in operating frequency/active width. | 02-18-2016 |
20160050301 | SYSTEM INTERCONNECT DYNAMIC SCALING HANDSHAKE USING SPARE BIT-LANE - A communications technique using spare bit-lanes to communicate changes in interface physical link layer bandwidth and/or active width provides for dynamic adjustment of power consumption of interface links without requiring a separate control path for exchanging the change information. One or more spare bit-lanes are used to communicate an indication of the operating frequency/active width change to the physical link layer of the remote side of the interface and an acknowledgement is sent back to provide complete handshaking of the operating characteristic change. The method can determine whether or not a spare bit-lane is available and prevent making the change if a spare bit-lane is not available until the interface is repaired and a spare bit-lane can then be used for communicating operating changes in operating frequency/active width. | 02-18-2016 |
20160065219 | DYNAMIC PRESCALING FOR PERFORMANCE COUNTERS - A method of configuring a prescaling circuit in a performance counter circuit for a computer processing system can include receiving a first number of signaled events at a prescaling circuit configured to generate event counts for a performance counter circuit. The method can include generating event counts at a current event-count rate for the first number of signaled events and determining a detected event-count rate for the signaled events based on a rate at which the first number of signaled events are received at the prescaling circuit. The method can include determining that the detected event-count rate is greater than the current event-count rate. The method can include increasing the current event-count rate in response to determining that the detected event-count rate is greater than the current event-count rate. | 03-03-2016 |