Patent application number | Description | Published |
20100109721 | SYSTEM FOR DETECTING A RESET CONDITION IN AN ELECTRONIC CIRCUIT - There is disclosed a system for detecting the assertion of a reset signal. A plurality of circuit elements is configurable by a reset signal to output a string of data values in a predetermined pattern. A comparator receives the string of data values and determines whether the string of data values matches the predetermined pattern. If so, the comparator generates an output signal indicative of a reset. In one embodiment, the output signal of the comparator can be used to automatically trigger a reset if the reset signal has not been asserted. | 05-06-2010 |
20110210770 | SYSTEM FOR DETECTING A RESET CONDITION IN AN ELECTRONIC CIRCUIT - There is disclosed a system for detecting the assertion of a reset signal. A plurality of circuit elements is configurable by a reset signal to output a string of data values in a predetermined pattern. A comparator receives the string of data values and determines whether the string of data values matches the predetermined pattern. If so, the comparator generates an output signal indicative of a reset. In one embodiment, the output signal of the comparator can be used to automatically trigger a reset if the reset signal has not been asserted. | 09-01-2011 |
20120102334 | System and Method for Hardware Based Security - An asset management system is provided, which includes a hardware module operating as an asset control core. The asset control core generally includes a small hardware core embedded in a target system on chip that establishes a hardware-based point of trust on the silicon die. The asset control core can be used as a root of trust on a consumer device by having features that make it difficult to tamper with. The asset control core is able to generate a unique identifier for one device and participate in the tracking and provisioning of the device through a secure communication channel with an appliance. The appliance generally includes a secure module that caches and distributes provisioning data to one of many agents that connect to the asset control core, e.g. on a manufacturing line or in an after-market programming session. | 04-26-2012 |
20120268174 | SYSTEM FOR DETECTING A RESET CONDITION IN AN ELECTRONIC CIRCUIT - There is disclosed a system for detecting the assertion of a reset signal. A plurality of circuit elements is configurable by a reset signal to output a string of data values in a predetermined pattern. A comparator receives the string of data values and determines whether the string of data values matches the predetermined pattern. If so, the comparator generates an output signal indicative of a reset. In one embodiment, the output signal of the comparator can be used to automatically trigger a reset if the reset signal has not been asserted. | 10-25-2012 |
20130111224 | INTEGRATED CIRCUIT WITH LOGIC CIRCUITRY AND MULTIPLE CONCEALING CIRCUITS | 05-02-2013 |
20140108825 | System and Method for Hardware Based Security - An asset management system is provided, which includes a hardware module operating as an asset control core. The asset control core generally includes a small hardware core embedded in a target system on chip that establishes a hardware-based point of trust on the silicon die. The asset control core can be used as a root of trust on a consumer device by having features that make it difficult to tamper with. The asset control core is able to generate a unique identifier for one device and participate in the tracking and provisioning of the device through a secure communication channel with an appliance. The appliance generally includes a secure module that caches and distributes provisioning data to one of many agents that connect to the asset control core, e.g. on a manufacturing line or in an after-market programming session. | 04-17-2014 |
20140169553 | MASKING WITH SHARED RANDOM BITS - A non-linear transformation including a plurality of non-linear logical operations is masked to a second or higher order. The masking includes receiving a set of random bits, and machine-masking two or more of the plurality of non-linear logical operations with a same random bit from the set of random bits. | 06-19-2014 |
20160048462 | SYSTEM AND METHOD FOR HARDWARE BASED SECURITY - An asset management system is provided, which includes a hardware module operating as an asset control core. The asset control core generally includes a small hardware core embedded in a target system on chip that establishes a hardware-based point of trust on the silicon die. The asset control core can be used as a root of trust on a consumer device by having features that make it difficult to tamper with. The asset control core is able to generate a unique identifier for one device and participate in the tracking and provisioning of the device through a secure communication channel with an appliance. The appliance generally includes a secure module that caches and distributes provisioning data to one of many agents that connect to the asset control core, e.g. on a manufacturing line or in an after-market programming session. | 02-18-2016 |