Patent application number | Description | Published |
20100159662 | RAISED SOURCE/DRAIN WITH SUPER STEEP RETROGRADE CHANNEL - Systems and methods for raised source/drain with super steep retrograde channel. In accordance with a first embodiment of the present invention, in one embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments in accordance with one embodiment may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art. | 06-24-2010 |
20110300681 | RAISED SOURCE/DRAIN WITH SUPER STEEP RETROGRADE CHANNEL - Systems and methods for raised source/drain with super steep retrograde channel are described. In accordance with a first embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art. | 12-08-2011 |
20120151235 | METHODS AND SYSTEMS FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING ENTRY AND EXIT LATENCY REDUCTION FOR LOW POWER STATES - Systems and methods for entry and exit latency reduction for low power states are described. In one embodiment, a computer implemented method initiates an energy-efficient low power state (e.g., deep sleep state) to reduce power consumption of a device. The method sets a power supply voltage that provides sufficient power to a dual power supply array for retention of states. Logic is powered down in this low power state. | 06-14-2012 |
20120166838 | METHOD AND SYSTEMS FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING ON-OFF KEYING FOR POWER CONTROL - Systems and a method for controlling power of a device with power management software are described. In one embodiment, a computer implemented method initiates power control having ON-OFF keying to control power consumption of a device for energy efficiency and energy conservation. An ON-OFF period of the ON-OFF keying for the device is computed. The method sets a target frequency, a target supply voltage, and a power gate control for the device based on the ON-OFF keying. | 06-28-2012 |
20140189240 | Apparatus and Method For Reduced Core Entry Into A Power State Having A Powered Down Core Cache - A method performed by a multi-core processor is described. The method includes, while a core is executing program code, reading a dirty cache line from the core's last level cache and sending the dirty cache line from the core for storage external from the core, where, the dirty cache line has not been evicted from the cache nor requested by another core or processor. | 07-03-2014 |
20140281254 | Semiconductor Chip With Adaptive BIST Cache Testing During Runtime - A method is described that includes during runtime of a semiconductor die, determining that a next BIST test sequence of a storage component embedded on the die is appropriate. The method further includes applying a BIST test sequence to each valid entry in the storage component. The method also includes marking any newly invalid entries in the storage component as invalid and configuring a respective replacement entry for each of the newly invalid entries. | 09-18-2014 |
20140281602 | Controlling Processor Consumption Using On-Off Keying Having A Maximum Off Time - In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the off times each correspond to a maximum off time for a platform including the processor. Other embodiments are described and claimed. | 09-18-2014 |
20140344596 | Controlling Power Consumption Of A Processor Using Interrupt-Mediated On-Off Keying - In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the on and off times vary depending on whether and when an interrupt is incurred. Other embodiments are described and claimed. | 11-20-2014 |