Patent application number | Description | Published |
20110031565 | MICROMACHINED DEVICES AND FABRICATING THE SAME - Micromachined devices and methods for making the devices. The device includes: a first wafer having at least one via; and a second wafer having a micro-electromechanical-systems (MEMS) layer. The first wafer is bonded to the second wafer. The via forms a closed loop when viewed in a direction normal to the top surface of the first wafer to thereby define an island electrically isolated. The method for fabricating the device includes: providing a first wafer having at least one via; bonding a second wafer having a substantially uniform thickness to the first wafer; and etching the bonded second wafer to form a micro-electromechanical-systems (MEMS) layer. | 02-10-2011 |
20130247668 | INERTIAL SENSOR MODE TUNING CIRCUIT - This document discusses, among other things, an mode matching circuit for a inertial sensor including an oscillator circuit configured to selectively couple to a sense axis of an inertial sensor and to provide sense frequency information of the sense axis, a frequency comparator configured to receive the sense frequency information of the sense axis and drive frequency information of the inertial sensor, and to provide frequency difference information to a processor, and a programmable bias source configured to apply a bias voltage to the sense axis to set a sense frequency of the sense axis in response to a command from the processor, and to maintain a desired frequency difference between the sense frequency and a drive frequency of the inertial sensor. | 09-26-2013 |
20130250532 | MULTI-DIE MEMS PACKAGE - This document refers to multi-die micromechanical system (MEMS) packages. In an example, a multi-die MEMS package can include a controller integrated circuit (IC) configured to couple to a circuit board, a MEMS IC mounted to a first side of the controller IC, a through silicon via extending through the controller IC between the first side and a second side of the controller IC, the second side opposite the first side, and wherein the MEMS IC is coupled to the through silicon via. | 09-26-2013 |
20130270660 | SEALED PACKAGING FOR MICROELECTROMECHANICAL SYSTEMS - One example includes an integrated circuit including at least one electrical interconnects disposed on an elongate are extending away from a main portion of the integrated circuit and a microelectromechanical layer including an oscillating portion, the microelectromechanical layer coupled to the main portion of the integrated circuit, wherein the microelectromechanical layer includes a cap comprising a membrane that extends to the integrated circuit. | 10-17-2013 |
20130277772 | MICROELECTROMECHANICAL PRESSURE SENSOR INCLUDING REFERENCE CAPACITOR - This document discusses, among other things, an apparatus including a silicon die including a vibratory diaphragm, the die having a silicon die top opposite a silicon die bottom, with a top silicon die port extending from the silicon die top through the silicon die to a top of the vibratory diaphragm, and with a bottom silicon die port extending from the silicon die bottom to a bottom of the vibratory diaphragm, wherein the bottom silicon die port has a cross sectional area that is larger than a cross-sectional area of the top silicon die port, a capacitor electrode disposed along a bottom of the silicon die, across the bottom silicon die port, the capacitor electrode including a first signal generation portion that is coextensive with the top silicon die port, and a second signal generation portion surrounding the first portion. | 10-24-2013 |
20130277773 | THROUGH SILCON VIA WITH REDUCED SHUNT CAPACITANCE - This document refers to apparatus and methods for a device layer of a microelectromechanical system (MEMS) sensor having vias with reduced shunt capacitance. In an example, a device layer can include a substrate having a pair of trenches separated in a horizontal direction by a portion of the substrate, wherein each trench of the pair of trenches includes first and second vertical layers including dielectric, the first and second vertical layers separated by a third vertical layer including polysilicon. | 10-24-2013 |
20130341737 | PACKAGING TO REDUCE STRESS ON MICROELECTROMECHANICAL SYSTEMS - One example includes an integrated circuit including at least one electrical interconnects disposed on an elongate are extending away from a main portion of the integrated circuit and a microelectromechanical layer including an oscillating portion, the microelectromechanical layer coupled to the main portion of the integrated circuit. | 12-26-2013 |
20140070339 | THROUGH SILICON VIA INCLUDING MULTI-MATERIAL FILL - An apparatus includes a substrate having at least one via disposed in the substrate, wherein the substrate includes a trench having a substantially trapezoidal cross-section, the trench extending through the substrate between a lower surface of the substrate and an upper surface of the substrate, wherein the top of the trench opens to a top opening, and the bottom of the trench opens to a bottom opening, the top opening being larger than the bottom opening. The apparatus can include a mouth surrounding the top opening and extending between the upper surface and the top opening, wherein a mouth opening in the upper surface is larger than the top opening of the trench, wherein the via includes a dielectric layer disposed on an inside surface of a trench. The apparatus includes and a fill disposed in the trench, with the dielectric layer sandwiched between the fill and the substrate. | 03-13-2014 |