Patent application number | Description | Published |
20130124025 | METHOD OF OPERATING A HYBRID POWERTRAIN - A method of operating a hybrid powertrain including an engine, an electric motor and a high voltage battery includes preventing fuel flow to the engine when the high voltage battery includes a state of charge at or above a pre-defined upper limit, and when the hybrid powertrain is operating in a second fueling condition in which fuel flow to the engine is preferably maintained. The engine is rotated with torque supplied by the electric motor to maintain rotation of the engine without producing any engine torque. | 05-16-2013 |
20140324306 | METHOD OF MANAGING AVAILABLE OPERATING STATES IN AN ELECTRIC VEHICLE POWERTRAIN - A method of managing available operating states in an electrified powertrain includes: identifying a plurality of operating states; determining an allowable hardware operating speed range for each of the plurality of operating states; determining a real operating speed range for each of the plurality of operating states; determining an ideal operating speed range for each of the plurality of operating states, the ideal operating speed range being a subset of the allowable real operating speed range; indicating an operating state of the plurality of operating states as ideal-allowed if an actual output speed of the electrified powertrain is within the ideal operating speed range for that operating state; and commanding the electrified powertrain to operate within one of the operating states that is indicated as ideal-allowed. | 10-30-2014 |
20140350805 | METHOD OF CONTROLLING A TRANSMISSION OF A VEHICLE - A method of controlling a transmission includes detecting an occurrence of a downshift in the transmission from a first gear ratio to a second gear ratio. A determination is made whether the vehicle is operating within a freeway speed range, and whether an accelerator pedal is depressed at least a minimum percentage of a fully depressed position. When the downshift from the high gear ratio to the low gear ratio is detected, the vehicle is operating within the freeway speed range, and the accelerator pedal is depressed at least the minimum percentage of the fully depressed position, a countdown timer is started to count down from a pre-defined time to zero. An upshift of the transmission from the second gear ratio to the first gear ratio is restricted while the countdown timer defines a time that is greater than zero. | 11-27-2014 |
Patent application number | Description | Published |
20110209127 | Register Allocation With SIMD Architecture Using Write Masks - A single instruction multiple data processor may accomplish register allocation by identifying live ranges that have incompatible write masks during compilation. Then, edges are added in an interference graph between live ranges that have incompatible masks so that those live ranges will not be assigned to the same physical register. | 08-25-2011 |
20120254497 | METHOD AND APPARATUS TO FACILITATE SHARED POINTERS IN A HETEROGENEOUS PLATFORM - A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified. | 10-04-2012 |
20140071144 | METHOD AND APPARATUS TO FACILITATE SHARED POINTERS IN A HETEROGENEOUS PLATFORM - A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified. | 03-13-2014 |
20140198110 | REDUCING THE NUMBER OF SEQUENTIAL OPERATIONS IN AN APPLICATION TO BE PERFORMED ON A SHARED MEMORY CELL - Methods and apparatuses to reduce the number of sequential operations such as atomic operations in an application to be performed on a shared memory cell may be provided. A translation unit can detect in the application multiple atomic operations to be performed on the same memory and replaces the multiple atomic operations with an equivalent single atomic operation. In some implementations, the application includes shader code. In some implementations, each of the multiple atomic operations increment a value stored at the same memory by an update amount. The translation unit may calculate the partial prefix sum over all the atomic operations and replace the multiple atomic operations with a single atomic operation to increment the value stored at memory by the sum of the update amounts. | 07-17-2014 |
20140198113 | SERIALIZED ACCESS TO GRAPHICS RESOURCES - Methods and systems may provide for identifying a plurality of subject commands that reference a common screen location and access a read/write resource, and serializing the plurality of subject commands according to a predefined order. Additionally, execution of the plurality of subject commands may be deferred until one or more additional commands referencing the common screen location are executed. In one example, the plurality of subject commands are serialized in response to a serialization command. | 07-17-2014 |
20140327682 | REDUCING THE NUMBER OF IO REQUESTS TO MEMORY WHEN EXECUTING A PROGRAM THAT ITERATIVELY PROCESSES CONTIGUOUS DATA - Methods and apparatuses to reduce the number of IO requests to memory when executing a program that iteratively processes contiguous data are provided. A first set of data elements may be loaded in a first register and a second set of data elements may be loaded in a second register. The first set of data elements and the second set of data elements can be used during the execution of a program to iteratively process the data elements. For each of a plurality of iterations, a corresponding set of data elements to be used during the execution of an operation for the iteration may be selected from the first set of data elements stored in the first register and the second set of data elements stored in the second register. In this way, the same data elements are not re-loaded from memory during each iteration. | 11-06-2014 |
20150287240 | Mapping Multi-Rate Shading to Monolithic Programs - In multi-rate shading, a coarse-rate shading phase is added on top of existing pixel-rate phase to significantly improve performance with minimum impact to image quality. Two shading phases evaluated at different rates may be mapped to one monolithic program running on processor graphics single instruction multiple data (SIMD) engines. In one embodiment, multi-rate shading allows a single rendering pass to execute shading code at one or more different rates: per group of pixels, per pixel, and per sample. | 10-08-2015 |