Patent application number | Description | Published |
20080268585 | SOI DEVICE HAVING A SUBSTRATE DIODE WITH PROCESS TOLERANT CONFIGURATION AND METHOD OF FORMING THE SOI DEVICE - A substrate diode for an SOI device is formed in accordance with an appropriately designed manufacturing flow, wherein transistor performance enhancing mechanisms may be implemented substantially without affecting the diode characteristics. In one aspect, respective openings for the substrate diode may be formed after the formation of a corresponding sidewall spacer structure used for defining the drain and source regions, thereby obtaining a significant lateral distribution of the dopants in the diode areas, which may therefore provide sufficient process margins during a subsequent silicidation sequence on the basis of a removal of the spacers in the transistor devices. In a further aspect, in addition to or alternatively, an offset spacer may be formed substantially without affecting the configuration of respective transistor devices. | 10-30-2008 |
20090218633 | CMOS DEVICE COMPRISING AN NMOS TRANSISTOR WITH RECESSED DRAIN AND SOURCE AREAS AND A PMOS TRANSISTOR HAVING A SILICON/GERMANIUM MATERIAL IN THE DRAIN AND SOURCE AREAS - A recessed transistor configuration may be provided selectively for one type of transistor, such as N-channel transistors, thereby enhancing strain-inducing efficiency and series resistance, while a substantially planar configuration or raised drain and source configuration may be provided for other transistors, such as P-channel transistors, which may also include a strained semiconductor alloy, while nevertheless providing a high degree of compatibility with CMOS techniques. For this purpose, an appropriate masking regime may be provided to efficiently cover the gate electrode of one transistor type during the formation of the corresponding recesses, while completely covering the other type of transistor. | 09-03-2009 |
20090298249 | DRIVE CURRENT INCREASE IN TRANSISTORS BY ASYMMETRIC AMORPHIZATION IMPLANTATION - By providing a substantially non-damaged semiconductor region between a pre-amorphization region and the gate electrode structure, an increase of series resistance at the drain side during the re-crystallization may be reduced, thereby contributing to overall transistor performance, in particular in the linear operating mode. Thus, symmetric and asymmetric transistor architectures may be achieved with enhanced performance without unduly adding to overall process complexity. | 12-03-2009 |
20090321837 | CONTACT TRENCHES FOR ENHANCING STRESS TRANSFER IN CLOSELY SPACED TRANSISTORS - Scalability of a strain-inducing mechanism on the basis of a stressed dielectric overlayer may be enhanced by forming a single stress-inducing layer in combination with contact trenches, which may shield a significant amount of a non-desired stress component in the complementary transistor, while also providing a strain component in the transistor width direction when the contact material may be provided with a desired internal stress level. | 12-31-2009 |
20090321841 | CMOS DEVICE COMPRISING MOS TRANSISTORS WITH RECESSED DRAIN AND SOURCE AREAS AND NON-CONFORMAL METAL SILICIDE REGIONS - A non-conformal metal silicide in a transistor of recessed drain and source configuration may provide enhanced efficiency with respect to strain-inducing mechanisms, drain/source resistance and the like. For this purpose, in some cases, an amorphizing implantation process may be performed prior to the silicidation process, while in other cases an anisotropic deposition of the refractory metal may be used. | 12-31-2009 |
20090321850 | Threshold adjustment for MOS devices by adapting a spacer width prior to implantation - Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and/or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing to process complexity compared to conventional approaches in which threshold voltage values may be adjusted on the basis of complex halo and well doping regimes. | 12-31-2009 |
20090325355 | REDUCING IMPLANT DEGRADATION IN TILTED IMPLANTATIONS BY SHIFTING IMPLANTATION MASKS - In extremely scaled semiconductor devices, an asymmetric transistor configuration may be established on the basis of tilted implantation processes with increased resist height and/or tilt angles during tilted implantation processes by providing an asymmetric mask arrangement for masked transistor elements. For this purpose, the implantation mask may be shifted by an appropriate amount so as to enhance the overall blocking effect for the masked transistors while reducing any shadowing effect of the implantation masks for the non-masked transistors. The shift of the implantation masks may be accomplished by performing the automatic alignment procedure on the basis of “shifted” target values or by providing asymmetrically arranged photolithography masks. | 12-31-2009 |
20100025743 | TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING ENHANCED BORON CONFINEMENT - By incorporating a diffusion hindering species at the vicinity of PN junctions of P-channel transistors comprising a silicon/germanium alloy, diffusion related non-uniformities of the PN junctions may be reduced, thereby contributing to enhanced device stability and increased overall transistor performance. The diffusion hindering species may be provided in the form of carbon, nitrogen and the like. | 02-04-2010 |
20100025771 | PERFORMANCE ENHANCEMENT IN PMOS AND NMOS TRANSISTORS ON THE BASIS OF SILICON/CARBON MATERIAL - A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation species may be provided through exposed surface areas of the cavities prior to forming the corresponding strained semiconductor alloy, thereby additionally contributing to enhanced overall transistor performance. In other embodiments a silicon/carbon material may be formed in a P-channel transistor and an N-channel transistor, while the corresponding tensile strain component may be overcompensated for by means of a stress memorization technique in the P-channel transistor. Thus, the advantageous effects of the carbon species, such as enhancing overall dopant profile of P-channel transistors, may be combined with an efficient strain component while enhanced overall process uniformity may also be accomplished. | 02-04-2010 |
20100052068 | DRIVE CURRENT ADJUSTMENT FOR TRANSISTORS FORMED IN THE SAME ACTIVE REGION BY LOCALLY PROVIDING EMBEDDED STRAIN-INDUCING SEMICONDUCTOR MATERIAL IN THE ACTIVE REGION - The drive current capability of a pull-down transistor and a pass transistor formed in a common active region may be adjusted on the basis of different strain levels obtained by providing at least one embedded semiconductor alloy in the active region, thereby providing a simplified overall geometric configuration of the active region. Hence, static RAM cells may be formed on the basis of a minimum channel length with a simplified configuration of the active region, thereby avoiding significant yield losses as may be observed in sophisticated devices, in which a pronounced variation of the transistor width is conventionally used to adjust the ratio of the drive currents for the pull-down and pass transistors. | 03-04-2010 |
20100055867 | STRUCTURED STRAINED SUBSTRATE FOR FORMING STRAINED TRANSISTORS WITH REDUCED THICKNESS OF ACTIVE LAYER - In a strained SOI semiconductor layer, the stress relaxation which may typically occur during the patterning of trench isolation structures may be reduced by selecting an appropriate reduced target height of the active regions, thereby enabling the formation of transistor elements on the active region of reduced height, which may still include a significant amount of the initial strain component. The active regions of reduced height may be advantageously used for forming fully depleted field effect transistors. | 03-04-2010 |
20100078653 | TRANSISTOR HAVING A HIGH-K METAL GATE STACK AND A COMPRESSIVELY STRESSED CHANNEL - In a manufacturing flow for adapting the band gap of the semiconductor material with respect to the work function of a metal-containing gate electrode material, a strain-inducing material may be deposited to provide an additional strain component in the channel region. For instance, a layer stack with silicon/carbon, silicon and silicon/germanium may be used for providing the desired threshold voltage for a metal gate while also providing compressive strain in the channel region. | 04-01-2010 |
20100078691 | TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING ENHANCED ACROSS-SUBSTRATE UNIFORMITY - In sophisticated semiconductor devices, a strain-inducing semiconductor alloy may be positioned close to the channel region by forming cavities on the basis of a wet chemical etch process, which may have an anisotropic etch behavior with respect to different crystallographic orientations. In one embodiment, TMAH may be used which exhibits, in addition to the anisotropic etch behavior, a high etch selectivity with respect to silicon dioxide, thereby enabling extremely thin etch stop layers which additionally provide the possibility of further reducing the offset from the channel region while not unduly contributing to overall process variability. | 04-01-2010 |
20100078735 | CMOS DEVICE COMPRISING NMOS TRANSISTORS AND PMOS TRANSISTORS HAVING INCREASED STRAIN-INDUCING SOURCES AND CLOSELY SPACED METAL SILICIDE REGIONS - In a CMOS manufacturing process flow, a cap layer formed on top of a gate electrode material may be maintained throughout the entire implantation sequence for defining the drain and source regions and may be removed during an etch process in which the width of a sidewall spacer structure may be reduced so as to reduce a lateral offset of metal silicide regions and of a stressed dielectric material. Thus, overall enhanced transistor performance may be obtained while nevertheless providing a high degree of compatibility with existing CMOS process strategies. | 04-01-2010 |
20100078736 | ASYMMETRIC TRANSISTOR DEVICES FORMED BY ASYMMETRIC SPACERS AND TILTED IMPLANTATION - An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor. | 04-01-2010 |
20100081244 | TRANSISTOR DEVICE COMPRISING AN ASYMMETRIC EMBEDDED SEMICONDUCTOR ALLOY - Transistor characteristics may be adjusted on the basis of asymmetrically formed cavities in the drain and source areas so as to maintain a strain-inducing mechanism while at the same time providing the possibility of obtaining asymmetric configuration of the drain and source areas while avoiding highly complex implantation processes. For this purpose, the removal rate during a corresponding cavity etch process may be asymmetrically modified on the basis of a tilted ion implantation process. | 04-01-2010 |
20100109012 | STRESS TRANSFER ENHANCEMENT IN TRANSISTORS BY A LATE GATE RE-CRYSTALLIZATION - A gate electrode structure of a transistor may be formed so as to exhibit a high crystalline quality at the interface formed with a gate dielectric material, while upper portions of the gate electrode may have an inferior crystalline quality. In a later manufacturing stage after implementing one or more strain-inducing mechanisms, the gate electrode may be re-crystallized, thereby providing increased stress transfer efficiency, which in turn results in an enhanced transistor performance. | 05-06-2010 |
20100109091 | RECESSED DRAIN AND SOURCE AREAS IN COMBINATION WITH ADVANCED SILICIDE FORMATION IN TRANSISTORS - During the manufacturing process for forming sophisticated transistor elements, the gate height may be reduced and a recessed drain and source configuration may be obtained in a common etch sequence prior to forming respective metal silicide regions. Since the corresponding sidewall spacer structure may be maintained during the etch sequence, controllability and uniformity of the silicidation process in the gate electrode may be enhanced, thereby obtaining a reduced degree of threshold variability. Furthermore, the recessed drain and source configuration may provide reduced overall series resistance and enhanced stress transfer efficiency. | 05-06-2010 |
20100133614 | MULTIPLE GATE TRANSISTOR HAVING HOMOGENOUSLY SILICIDED FIN END PORTIONS - In a multiple gate transistor, the plurality of Fins of the drain or source of the transistor are electrically connected to each other by means of a common contact element, wherein enhanced uniformity of the corresponding contact regions may be accomplished by an enhanced silicidation process sequence. For this purpose, the Fins may be embedded into a dielectric material in which an appropriate contact opening may be formed to expose end faces of the Fins, which may then act as silicidation surface areas. | 06-03-2010 |
20100133615 | MULTIPLE GATE TRANSISTOR HAVING FINS WITH A LENGTH DEFINED BY THE GATE ELECTRODE - The drain and source regions of a multiple gate transistor may be formed without an epitaxial growth process by using a placeholder structure for forming the drain and source dopant profiles and subsequently masking the drain and source areas and removing the placeholder structures so as to expose the channel area of the transistor. Thereafter, corresponding fins may be patterned and a gate electrode structure may be formed. Consequently, reduced cycle times may be accomplished due to the avoidance of the epitaxial growth process. | 06-03-2010 |
20100134167 | COMPENSATION OF DEGRADATION OF PERFORMANCE OF SEMICONDUCTOR DEVICES BY CLOCK DUTY CYCLE ADAPTATION - The device degradation of integrated circuits may be compensated for by appropriately adapting the duty cycle of the clock signal. For this purpose, a correlation between the duty cycle and the overall performance characteristics of the integrated circuit may be established and may be used during the normal field operation of the device in order to modify the duty cycle. Hence, an efficient control strategy may be implemented since the duty cycle may be efficiently controlled, while at the same time a change of clock signal frequency and/or an increase of supply voltage may not be required. | 06-03-2010 |
20100155850 | TECHNIQUE FOR PROVIDING STRESS SOURCES IN TRANSISTORS IN CLOSE PROXIMITY TO A CHANNEL REGION BY RECESSING DRAIN AND SOURCE REGIONS - By recessing drain and source regions, a highly stressed layer, such as a contact etch stop layer, may be formed in the recess in order to enhance the strain generation in the adjacent channel region of a field effect transistor. Moreover, a strained semiconductor material may be positioned in close proximity to the channel region by reducing or avoiding undue relaxation effects of metal silicides, thereby also providing enhanced efficiency for the strain generation. In some aspects, both effects may be combined to obtain an even more efficient strain-inducing mechanism. | 06-24-2010 |
20100163939 | TRANSISTOR DEVICE COMPRISING AN EMBEDDED SEMICONDUCTOR ALLOY HAVING AN ASYMMETRIC CONFIGURATION - In sophisticated semiconductor devices, an asymmetric transistor configuration may be obtained on the basis of a strain-inducing semiconductor alloy. To this end, strain relaxation implantation processes may be performed at the drain side according to some illustrative embodiments, while, in other cases, the deposition of the strain-inducing alloy may be performed in an asymmetric manner with respect to the drain side and the source side of the transistor. | 07-01-2010 |
20100164530 | ADJUSTING CONFIGURATION OF A MULTIPLE GATE TRANSISTOR BY CONTROLLING INDIVIDUAL FINS - In a sophisticated semiconductor device, FINFET elements may be provided with individually accessible semiconductor fins which may be connected to a controllable inter-connect structure for appropriately adjusting the transistor configuration, for instance with respect to current drive capability, replacing defective semiconductor fins and the like. Consequently, different transistor configurations may be obtained on the basis of a standard transistor cell architecture, which may result in increased production yield of highly complex manufacturing strategies in forming non-planar transistor devices. | 07-01-2010 |
20100181619 | METHOD OF FORMING A FIELD EFFECT TRANSISTOR - A method of forming a field effect transistor comprises providing a substrate comprising a biaxially strained layer of a semiconductor material. A gate electrode is formed on the biaxially strained layer of semiconductor material. A raised source region and a raised drain region are formed adjacent the gate electrode. Ions of a dopant material are implanted into the raised source region and the raised drain region to form an extended source region and an extended drain region. Moreover, in methods of forming a field effect transistor according to embodiments of the present invention, a gate electrode can be formed in a recess of a layer of semiconductor material. Thus, a field effect transistor wherein a source side channel contact region and a drain side channel contact region located adjacent a channel region are subject to biaxial strain can be obtained. | 07-22-2010 |
20100193866 | GRADED WELL IMPLANTATION FOR ASYMMETRIC TRANSISTORS HAVING REDUCED GATE ELECTRODE PITCHES - In sophisticated semiconductor devices, an asymmetric transistor configuration may be obtained on the basis of an asymmetric well implantation while avoiding a tilted implantation process. For this purpose, a graded implantation mask may be formed, such as a graded resist mask, which may have a higher ion blocking capability at the drain side compared to the source side of the asymmetric transistor. For instance, the asymmetric configuration may be obtained on the basis of a non-tilted implantation process with a high degree of performance gain and may be accomplished irrespective of the technology standard under consideration. | 08-05-2010 |
20100193873 | INCREASED DEPTH OF DRAIN AND SOURCE REGIONS IN COMPLEMENTARY TRANSISTORS BY FORMING A DEEP DRAIN AND SOURCE REGION PRIOR TO A CAVITY ETCH - Deep drain and source regions of an N-channel transistor may be formed through corresponding cavities, which may be formed together with cavities of a P-channel transistor, wherein the lateral offsets of the cavities may be adjusted on the basis of an appropriate reverse spacer regime. Consequently, the dopant species in the N-channel transistor extends down to a specific depth, for instance down to the buried insulating layer of an SOI device, while at the same time providing an efficient strain-inducing mechanism for the P-channel transistor with a highly efficient overall manufacturing process flow. | 08-05-2010 |
20100193882 | IN SITU FORMED DRAIN AND SOURCE REGIONS INCLUDING A STRAIN-INDUCING ALLOY AND A GRADED DOPANT PROFILE - The dopant profile of a transistor may be obtained on the basis of an in situ doped strain-inducing semiconductor alloy wherein a graded dopant concentration may be established along the height direction. Consequently, the semiconductor alloy may be positioned in close proximity to the channel region, thereby enhancing the overall strain-inducing efficiency, while not unduly compromising the finally obtained dopant profile. Furthermore, additional implant species may be incorporated prior to selectively growing the semiconductor alloy, thereby avoiding implantation-induced relaxation of the internal strain. | 08-05-2010 |
20100301416 | STRAIN TRANSFORMATION IN BIAXIALLY STRAINED SOI SUBSTRATES FOR PERFORMANCE ENHANCEMENT OF P-CHANNEL AND N-CHANNEL TRANSISTORS - In advanced SOI devices, a high tensile strain component may be achieved on the basis of a globally strained semiconductor layer, while at the same time a certain compressive strain may be induced in P-channel transistors by appropriately selecting a height-to-length aspect ratio of the corresponding active regions. It has been recognized that the finally obtained strain distribution in the active regions is strongly dependent on the aspect ratio of the active regions. Thus, by selecting a moderately low height-to-length aspect ratio for N-channel transistors, a significant fraction of the initial tensile strain component may be preserved. On the other hand, a moderately high height-to-length aspect ratio for the P-channel transistor may result in a compressive strain component in a central surface region of the active region. | 12-02-2010 |
20110049641 | STRESS ADJUSTMENT IN STRESSED DIELECTRIC MATERIALS OF SEMICONDUCTOR DEVICES BY STRESS RELAXATION BASED ON RADIATION - In sophisticated semiconductor devices, an efficient adjustment of an intrinsic stress level of dielectric materials, such as contact etch stop layers, may be accomplished by selectively exposing the dielectric material to radiation, such as ultraviolet radiation. Consequently, different stress levels may be efficiently obtained without requiring sophisticated stress relaxation processes based on ion implantation, which typically leads to significant device failures. | 03-03-2011 |
20110073875 | OPTICAL SIGNAL TRANSFER IN A SEMICONDUCTOR DEVICE BY USING MONOLITHIC OPTO-ELECTRONIC COMPONENTS - In a semiconductor device, optical signal transfer capabilities are implemented on the basis of silicon-based monolithic opto-electronic components in combination with an appropriate waveguide. Thus, in complex circuitries, such as microprocessors and the like, superior performance may be obtained in terms of signal propagation delay, while at the same time thermal requirements may be less critical. | 03-31-2011 |
20110076028 | SEMICONDUCTOR DEVICE COMPRISING A BURIED WAVEGUIDE FOR DEVICE INTERNAL OPTICAL COMMUNICATION - In an integrated circuit device, such as a microprocessor, a device internal optical communication system is provided in order to enhance signal transfer capabilities while relaxing overall thermal conditions. Furthermore, the device internal optical data or signal transfer capabilities may result in superior operating speed and a high degree of design flexibility. The optical communication system may be applied as a chip internal system in single chip systems or as an inter-chip optical system in three-dimensional chip configurations provided in a single package. | 03-31-2011 |
20110101427 | TRANSISTOR INCLUDING A HIGH-K METAL GATE ELECTRODE STRUCTURE FORMED PRIOR TO DRAIN/SOURCE REGIONS ON THE BASIS OF A SUPERIOR IMPLANTATION MASKING EFFECT - When forming a sophisticated high-k metal gate stack in an early manufacturing stage, the dielectric cap layer may be efficiently removed without unduly affecting the drain and source extension regions. To this end, a specifically designed sidewall spacer structure may be used, such as a silicon dioxide spacer element in combination with a silicon nitride etch stop liner. The spacer structure may thus enable the removal of the dielectric cap layer while still maintaining the functions of an implantation mask and a silicidation mask during the further processing. | 05-05-2011 |
20110101456 | STRAIN ENGINEERING IN THREE-DIMENSIONAL TRANSISTORS BASED ON GLOBALLY STRAINED SEMICONDUCTOR BASE LAYERS - Non-planar transistors, such as FINFETs, may be formed on the basis of a globally strained semiconductor material, thereby preserving a high uniaxial strain component in the resulting semiconductor fins. In this manner, a significant performance enhancement may be achieved without adding process complexity when implementing FINFET transistors. | 05-05-2011 |
20110104863 | TRANSISTOR INCLUDING A HIGH-K METAL GATE ELECTRODE STRUCTURE FORMED PRIOR TO DRAIN/SOURCE REGIONS ON THE BASIS OF A SACRIFICIAL CARBON SPACER - When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage, the dielectric cap layer of the gate electrode structures may be efficiently removed on the basis of a carbon spacer element, which may thus preserve the integrity of the silicon nitride spacer structure. Thereafter, the sacrificial carbon spacer may be removed substantially without affecting other device areas, such as isolation structures, active regions and the like, which may contribute to superior process conditions during the further processing of the semiconductor device. | 05-05-2011 |
20110121398 | TECHNIQUE FOR ENHANCING DOPANT PROFILE AND CHANNEL CONDUCTIVITY BY MILLISECOND ANNEAL PROCESSES - During the fabrication of advanced transistors, significant dopant diffusion may be suppressed by performing a millisecond anneal process after completing the basic transistor configuration, wherein a stress memorization technique may also be obtained by forming a strain-inducing area within a sidewall spacer structure. Due to the corresponding void formation in the spacer structure, a high tensile strain component may be obtained in the adjacent channel region. | 05-26-2011 |
20110127614 | REDUCING THE SERIES RESISTANCE IN SOPHISTICATED TRANSISTORS BY EMBEDDING METAL SILICIDE CONTACT REGIONS RELIABLY INTO HIGHLY DOPED SEMICONDUCTOR MATERIAL - In sophisticated transistor elements, an additional silicon-containing semiconductor material may be provided after forming the drain and source extension regions, thereby reducing the probability of forming metal silicide regions, such as nickel silicide regions, which may extend into the channel region, thereby causing a significant increase in series resistance. Consequently, an increased degree of flexibility in adjusting the overall transistor characteristics may be achieved, for instance, by selecting a reduced spacer width and the like. | 06-02-2011 |
20110127616 | WORK FUNCTION ADJUSTMENT IN HIGH-K GATE STACKS FOR DEVICES OF DIFFERENT THRESHOLD VOLTAGE - In sophisticated semiconductor devices, different threshold voltage levels for transistors may be set in an early manufacturing stage, i.e., prior to patterning the gate electrode structures, by using multiple diffusion processes and/or gate dielectric materials. In this manner, substantially the same gate layer stacks, i.e., the same electrode materials and the same dielectric cap materials, may be used, thereby providing superior patterning uniformity when applying sophisticated etch strategies. | 06-02-2011 |
20110127617 | PERFORMANCE ENHANCEMENT IN TRANSISTORS COMPRISING HIGH-K METAL GATE STACK BY AN EARLY EXTENSION IMPLANTATION - In sophisticated transistor elements, integrity of sensitive gate materials may be enhanced while, at the same time, the lateral offset of extension regions may be reduced. To this end, at least a portion of the extension regions may be implanted at an early manufacturing stage, i.e., in the presence of a protective liner material, which may, after forming the extension regions, be patterned into a protective spacer structure used for preserving integrity of the sensitive gate electrode structure. | 06-02-2011 |
20110127618 | PERFORMANCE ENHANCEMENT IN PFET TRANSISTORS COMPRISING HIGH-K METAL GATE STACK BY INCREASING DOPANT CONFINEMENT - In a P-channel transistor comprising a high-k metal gate electrode structure, a superior dopant profile may be obtained, at least in the threshold adjusting semiconductor material, such as a silicon/germanium material, by incorporating a diffusion blocking species, such as fluorine, prior to forming the threshold adjusting semiconductor material. Consequently, the drain and source extension regions may be provided with a high dopant concentration as required for obtaining the target Miller capacitance without inducing undue dopant diffusion below the threshold adjusting semiconductor material, which may otherwise result in increased leakage currents and increased risk of punch through events. | 06-02-2011 |
20110129972 | TRANSISTOR INCLUDING A HIGH-K METAL GATE ELECTRODE STRUCTURE FORMED ON THE BASIS OF A SIMPLIFIED SPACER REGIME - In sophisticated semiconductor devices, the threshold voltage adjustment of high-k metal gate electrode structures may be accomplished by a work function metal species provided in an early manufacturing stage. For this purpose, a protective sidewall spacer structure is provided, which is, in combination with a dielectric cap material, also used as an efficient implantation mask during the implantation of extension and halo regions, thereby increasing the ion blocking capability of the complex gate electrode structure substantially without affecting the sensitive gate materials. | 06-02-2011 |
20110156099 | ENHANCED CONFINEMENT OF SENSITIVE MATERIALS OF A HIGH-K METAL GATE ELECTRODE STRUCTURE - When forming sophisticated high-k metal gate electrode structures, the removal of a dielectric cap material may be accomplished with superior process uniformity by using a silicon dioxide material. In other illustrative embodiments, an enhanced spacer regime may be applied, thereby also providing superior implantation conditions for forming drain and source extension regions and drain and source regions. | 06-30-2011 |
20110156154 | HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED AT DIFFERENT PROCESS STAGES OF A SEMICONDUCTOR DEVICE - Sophisticated high-k metal gate electrode structures are provided on the basis of a hybrid process strategy in which the work function of certain gate electrode structures is adjusted in an early manufacturing stage, while, in other gate electrode structures, the initial gate stack is used as a dummy material and is replaced in a very advanced manufacturing stage. In this manner, superior overall process robustness in combination with enhanced device performance may be achieved. | 06-30-2011 |
20110159657 | ENHANCED INTEGRITY OF A HIGH-K METAL GATE ELECTRODE STRUCTURE BY USING A SACRIFICIAL SPACER FOR CAP REMOVAL - In a process strategy for forming sophisticated high-k metal gate electrode structures in an early manufacturing phase, the dielectric cap material may be removed on the basis of a protective spacer element, thereby ensuring integrity of a silicon nitride sidewall spacer structure, which may preserve integrity of sensitive gate materials and may also determine the lateral offset of a strain-inducing semiconductor material. | 06-30-2011 |
20110183477 | SOI DEVICE HAVING A SUBSTRATE DIODE WITH PROCESS TOLERANT CONFIGURATION AND METHOD OF FORMING THE SOI DEVICE - A substrate diode for an SOI device is formed in accordance with an appropriately designed manufacturing flow, wherein transistor performance enhancing mechanisms may be implemented substantially without affecting the diode characteristics. In one aspect, respective openings for the substrate diode may be formed after the formation of a corresponding sidewall spacer structure used for defining the drain and source regions, thereby obtaining a significant lateral distribution of the dopants in the diode areas, which may therefore provide sufficient process margins during a subsequent silicidation sequence on the basis of a removal of the spacers in the transistor devices. In a further aspect, in addition to or alternatively, an offset spacer may be formed substantially without affecting the configuration of respective transistor devices. | 07-28-2011 |
20110186915 | REPLACEMENT GATE APPROACH BASED ON A REVERSE OFFSET SPACER APPLIED PRIOR TO WORK FUNCTION METAL DEPOSITION - In a replacement gate approach, a spacer may be formed in the gate opening after the removal of the placeholder material, thereby providing a superior cross-sectional shape upon forming any electrode metals in the gate opening. Moreover, the spacer may be used for reducing the gate length, while not requiring more complex gate patterning strategies. | 08-04-2011 |
20110186937 | ADJUSTMENT OF TRANSISTOR CHARACTERISTICS BASED ON A LATE WELL IMPLANTATION - A self-aligned well implantation process may be performed so as to adjust threshold voltage and/or body resistance of transistors. To this end, after removing a placeholder material of gate electrode structures, the implantation process may be performed on the basis of appropriate process parameters to obtain the desired transistor characteristics. Thereafter, any appropriate electrode metal may be filled in, thereby providing gate electrode structures having superior performance. For example, high-k metal gate electrode structures may be formed on the basis of a replacement gate approach, while the additional late well implantation may provide a high degree of flexibility in providing different transistor versions of the same basic configuration. | 08-04-2011 |
20110201165 | CMOS DEVICE COMPRISING MOS TRANSISTORS WITH RECESSED DRAIN AND SOURCE AREAS AND NON-CONFORMAL METAL SILICIDE REGIONS - A non-conformal metal silicide in a transistor of recessed drain and source configuration may provide enhanced efficiency with respect to strain-inducing mechanisms, drain/source resistance and the like. For this purpose, in some cases, an amorphizing implantation process may be performed prior to the silicidation process, while in other cases an anisotropic deposition of the refractory metal may be used. | 08-18-2011 |
20110210380 | CONTACT BARS WITH REDUCED FRINGING CAPACITANCE IN A SEMICONDUCTOR DEVICE - In sophisticated semiconductor devices, the contact structure may be formed on the basis of contact bars formed in a lower portion of an interlayer dielectric material, which may then be contacted by contact elements having reduced lateral dimensions so as to preserve a desired low overall fringing capacitance. The concept of contact bars of reduced height level may be efficiently combined with sophisticated replacement gate approaches. | 09-01-2011 |
20110210389 | Transistor Comprising a Buried High-K Metal Gate Electrode Structure - A buried gate electrode structures may be formed in the active regions of sophisticated transistors by providing a recess in the active region and incorporating appropriate gate materials, such as a high-k dielectric material and a metal-containing electrode material. Due to the recessed configuration, the channel length and thus the channel controllability may be increased, without increasing the overall lateral dimensions of the transistor structure. | 09-01-2011 |
20110210398 | TRANSISTORS COMPRISING HIGH-K METAL GATE ELECTRODE STRUCTURES AND ADAPTED CHANNEL SEMICONDUCTOR MATERIALS - In sophisticated semiconductor devices, a replacement gate approach may be applied, in which a channel semiconductor material may be provided through the gate opening prior to forming the gate dielectric material and the electrode metal. In this manner, specific channel materials may be provided in a late manufacturing stage for different transistor types, thereby providing superior transistor performance and superior flexibility in adjusting the electronic characteristics of the transistors. | 09-01-2011 |
20110210427 | STRAIN MEMORIZATION IN STRAINED SOI SUBSTRATES OF SEMICONDUCTOR DEVICES - In sophisticated semiconductor devices, the initial strain component of a globally strained semiconductor layer may be substantially preserved during the formation of shallow trench isolations by using a rigid mask material, which may efficiently avoid or reduce a deformation of the semiconductor islands upon patterning the isolation trenches. Consequently, selected regions with high internal stress levels may be provided, irrespective of the height-to-length aspect ratio, which may limit the application of globally strained semiconductor layers in conventional approaches. Furthermore, in some illustrative embodiments, active regions of substantially relaxed strain state or of inverse strain type may be provided in addition to the highly strained active regions, thereby enabling an efficient process strategy for forming complementary transistors. | 09-01-2011 |
20110211394 | FIELD EFFECT TRANSISTORS FOR A FLASH MEMORY COMPRISING A SELF-ALIGNED CHARGE STORAGE REGION - Storage transistors for flash memory areas in semiconductor devices may be provided on the basis of a self-aligned charge storage region. To this end, a floating spacer element may be provided in some illustrative embodiments, while, in other cases, the charge storage region may be efficiently embedded in the electrode material in a self-aligned manner during a replacement gate approach. Consequently, enhanced bit density may be achieved, since additional sophisticated lithography processes for patterning the charge storage region may no longer be required. | 09-01-2011 |
20110223732 | THRESHOLD ADJUSTMENT FOR MOS DEVICES BY ADAPTING A SPACER WIDTH PRIOR TO IMPLANTATION - Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and/or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing to process complexity compared to conventional approaches in which threshold voltage values may be adjusted on the basis of complex halo and well doping regimes. | 09-15-2011 |
20110241086 | ALUMINUM FUSES IN A SEMICONDUCTOR DEVICE COMPRISING METAL GATE ELECTRODE STRUCTURES - In sophisticated semiconductor devices, electronic fuses may be provided on the basis of a replacement gate approach by using the aluminum material as an efficient metal for inducing electromigration in the electronic fuses. The electronic fuse may be formed on an isolation structure, thereby providing an efficient thermal decoupling of the electronic fuse from the semiconductor material and the substrate material, thereby enabling the provision of efficient electronic fuses in a bulk configuration, while avoiding incorporation of fuses into the metallization system. | 10-06-2011 |
20110266633 | Semiconductor Device Comprising Metal Gates and Semiconductor Resistors Formed on the Basis of a Replacement Gate Approach - In a replacement gate approach, the semiconductor material or at least a significant portion thereof in a non-transistor structure, such as a precision resistor, an electronic fuse and the like, may be preserved upon replacing the semiconductor material in the gate electrode structures. To this end, an appropriate dielectric material may be provided at least prior to the removal of the semiconductor material in the gate electrode structures, without requiring significant modifications of established replacement gate approaches. | 11-03-2011 |
20110269278 | Stress Memorization with Reduced Fringing Capacitance Based on Silicon Nitride in MOS Semiconductor Devices - In sophisticated semiconductor devices, stress memorization techniques may be applied on the basis of a silicon nitride material, which may be subsequently modified into a low-k dielectric material in order to obtain low-k spacer elements, thereby enhancing performance of sophisticated semiconductor devices. The modification of the initial silicon nitride-based spacer material may be accomplished on the basis of an oxygen implantation process. | 11-03-2011 |
20110291269 | Semiconductor Device Comprising a Stacked Die Configuration Including an Integrated Peltier Element - In a stacked semiconductor device, a Peltier element may be incorporated as a distributed element so as to provide active heat transfer from a high power device into a low power device, thereby achieving superior temperature control in stacked device configurations. For example, a CPU and a dynamic RAM device may be provided as a stacked configuration, wherein waste heat of the CPU may be efficiently distributed into the low power memory device. | 12-01-2011 |
20120025266 | Transistors Comprising High-K Metal Gate Electrode Structures and Embedded Strain-Inducing Semiconductor Alloys Formed in a Late Stage - In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration. | 02-02-2012 |
20120025312 | Strain Engineering in Three-Dimensional Transistors Based on a Strained Channel Semiconductor Material - In three-dimensional transistor configurations, such as finFETs, at least one surface of the semiconductor fin may be provided with a strained semiconductor material, which may thus have a pronounced uniaxial strain component along the current flow direction. The strained semiconductor material may be provided at any appropriate manufacturing stage, for instance, prior to actually patterning the semiconductor fins and/or after the patterning the semiconductor fins, thereby providing superior performance and flexibility in adjusting the overall characteristics of three-dimensional transistors. | 02-02-2012 |
20120119259 | SEMICONDUCTOR DEVICE SUBSTRATE WITH EMBEDDED STRESS REGION, AND RELATED FABRICATION METHODS - A semiconductor device substrate is presented here. The semiconductor device substrate includes a layer of first semiconductor material having a first lattice constant, a region of second semiconductor material located in the layer of first semiconductor material, and a layer of epitaxially grown third semiconductor material overlying the layer of first semiconductor material and overlying the region of second semiconductor material. The second semiconductor material has a second lattice constant that is different than the first lattice constant. Moreover, the layer of epitaxially grown third semiconductor material exhibits a stressed zone overlying the region of second semiconductor material. The stressed zone has a third lattice constant that is different than the first lattice constant. | 05-17-2012 |
20120129308 | Performance Enhancement in PMOS and NMOS Transistors on the Basis of Silicon/Carbon Material - A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation species may be provided through exposed surface areas of the cavities prior to forming the corresponding strained semiconductor alloy, thereby additionally contributing to enhanced overall transistor performance. In other embodiments a silicon/carbon material may be formed in a P-channel transistor and an N-channel transistor, while the corresponding tensile strain component may be overcompensated for by means of a stress memorization technique in the P-channel transistor. Thus, the advantageous effects of the carbon species, such as enhancing overall dopant profile of P-channel transistors, may be combined with an efficient strain component while enhanced overall process uniformity may also be accomplished. | 05-24-2012 |
20120146155 | TECHNIQUE FOR ENHANCING DOPANT PROFILE AND CHANNEL CONDUCTIVITY BY MILLISECOND ANNEAL PROCESSES - During the fabrication of advanced transistors, significant dopant diffusion may be suppressed by performing a millisecond anneal process after completing the basic transistor configuration, wherein a stress memorization technique may also be obtained by forming a strain-inducing area within a sidewall spacer structure. Due to the corresponding void formation in the spacer structure, a high tensile strain component may be obtained, in the adjacent channel region. | 06-14-2012 |
20120153399 | Low-Diffusion Drain and Source Regions in CMOS Transistors for Low Power/High Performance Applications - The drain and source regions may at least be partially formed by in situ doped epitaxially grown semiconductor materials for complementary transistors in sophisticated semiconductor devices designed for low power and high performance applications. To this end, cavities may be refilled with in situ doped semiconductor material, which in some illustrative embodiments also provides a desired strain in the channel regions of the complementary transistors. | 06-21-2012 |
20120156839 | Patterning of a Stressed Dielectric Material in a Contact Level Without Using an Underlying Etch Stop Layer - An efficient strain-inducing mechanism may be implemented in the form of differently stressed material layers that are formed above transistors of different types. The strain-inducing dielectric materials may be formed so as to be in direct contact with the corresponding transistors, thereby enhancing the overall strain transfer efficiency. Moreover, the disclosed manufacturing strategy avoids or at least significantly reduces any interaction of reactive etch atmospheres used to pattern the strain-inducing material layers with metal silicide regions, which may be formed individually for each type of transistor. | 06-21-2012 |
20120161203 | Strain Enhancement in Transistors Comprising an Embedded Strain-Inducing Semiconductor Material by Alloy Species Condensation - In transistors requiring a high compressive strain, the germanium contents may be increased by applying a germanium condensation technique. In some illustrative embodiments, an oxidation process is performed in the presence of a silicon/germanium material obtained on the basis of selective epitaxial growth techniques, thereby increasingly oxidizing the silicon species, while driving the germanium into the lower lying areas of the active region, which finally results in an increased germanium concentration. | 06-28-2012 |
20120161204 | Transistor Comprising an Embedded Sigma Shaped Sequentially Formed Semiconductor Alloy - In sophisticated transistors, a specifically designed semiconductor material, such as a strain-inducing semiconductor material, may be sequentially provided in the drain region and the source region, thereby enabling a significant degree of lateral extension of the grown semiconductor materials without jeopardizing mechanical integrity of the transistor during the processing thereof. For example, semiconductor devices having different drain and source sides may be provided on the basis of sequentially provided embedded semiconductor materials. | 06-28-2012 |
20120171830 | ASYMMETRIC TRANSISTOR DEVICES FORMED BY ASYMMETRIC SPACERS AND TILTED IMPLANTATION - An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor. | 07-05-2012 |
20120193686 | SEMICONDUCTOR DEVICES HAVING ENCAPSULATED STRESSOR REGIONS AND RELATED FABRICATION METHODS - Apparatus and related fabrication methods are provided for semiconductor device structures having silicon-encapsulated stressor regions. One method for fabricating a semiconductor device structure involves the steps of forming a gate structure overlying the semiconductor substrate, forming recesses in the semiconductor substrate about the gate structure, forming a stress-inducing semiconductor material in the recesses, and forming a silicon material in the recesses overlying the stress-inducing semiconductor material. In an exemplary embodiment, the silicon material formed in the recesses is epitaxially-grown on the stress-inducing semiconductor material. | 08-02-2012 |
20120193708 | Drive Current Increase in Field Effect Transistors by Asymmetric Concentration Profile of Alloy Species of a Channel Semiconductor Alloy - When forming sophisticated transistors, the channel region may be provided such that the gradient of the band gap energy of the channel material may result in superior charge carrier velocity. For example, a gradient in concentration of germanium, carbon and the like may be implemented along the channel length direction, thereby obtaining higher transistor performance. | 08-02-2012 |
20120196422 | Stress Memorization Technique Using Gate Encapsulation - Generally, the subject matter disclosed herein relates to sophisticated semiconductor devices and methods for forming the same, wherein a stress memorization technique is used to enhance the performance of MOS transistor elements. One illustrative embodiment includes a method for forming a gate electrode above a channel region of a semiconductor device, wherein the channel region is formed in an active region of a semiconductor substrate. The method further includes forming a dielectric encapsulating layer in direct contact with the gate electrode, and performing a heat treatment process to induce a residual stress in the channel region. | 08-02-2012 |
20120196425 | High-K Metal Gate Electrode Structures Formed by a Replacement Gate Approach Based on Superior Planarity of Placeholder Materials - When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, superior process uniformity may be achieved by implementing at least one planarization process after the deposition of the placeholder material, such as the polysilicon material, and prior to actually patterning the gate electrode structures. | 08-02-2012 |
20120199912 | COMPLEMENTARY STRESS LINER TO IMPROVE DGO/AVT DEVICES AND POLY AND DIFFUSION RESISTORS - Electron mobility and hole mobility is improved in long channel semiconductor devices and resistors by employing complementary stress liners. Embodiments include forming a long channel semiconductor device on a substrate, and forming a complementary stress liner on the semiconductor device. Embodiments include forming a resistor on a substrate, and tuning the resistance of the resistor by forming a complementary stress liner on the resistor. Compressive stress liners are employed for improving electron mobility in n-type devices, and tensile stress liners are employed for improving hole mobility in p-type devices. | 08-09-2012 |
20120211810 | TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING ENHANCED ACROSS-SUBSTRATE UNIFORMITY - In sophisticated semiconductor devices, a strain-inducing semiconductor alloy may be positioned close to the channel region by forming cavities on the basis of a wet chemical etch process, which may have an anisotropic etch behavior with respect to different crystallographic orientations. In one embodiment, TMAH may be used which exhibits, in addition to the anisotropic etch behavior, a high etch selectivity with respect to silicon dioxide, thereby enabling extremely thin etch stop layers which additionally provide the possibility of further reducing the offset from the channel region while not unduly contributing to overall process variability. | 08-23-2012 |
20120231591 | METHODS FOR FABRICATING CMOS INTEGRATED CIRCUITS HAVING METAL SILICIDE CONTACTS - Methods are provided for fabricating CMOS integrated circuits. In accordance with one embodiment the methods include forming a gate electrode structure overlying an N-doped portion of a semiconductor substrate and growing an embedded silicon germanium area in the N-doped portion in alignment with the gate electrode structure. A layer of silicon is selectively grown overlying the embedded silicon germanium area and a nickel silicide contact is made to the layer of silicon. | 09-13-2012 |
20120235215 | PERFORMANCE ENHANCEMENT IN TRANSISTORS BY REDUCING THE RECESSING OF ACTIVE REGIONS AND REMOVING SPACERS - Sophisticated transistors for semiconductor devices may be formed on the basis of a superior process sequence in which an increased space between closely spaced gate electrode structures may be obtained in combination with a reduced material loss in the active regions. To this end, an offset spacer conventionally used for laterally profiling the drain and source extension regions is omitted and the spacer for the deep drain and source areas may be completely removed. | 09-20-2012 |
20120280289 | Method of Increasing the Germanium Concentration in a Silicon-Germanium Layer and Semiconductor Device Comprising Same - Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming layer of silicon germanium on a P-active region of a semiconducting substrate wherein the layer of silicon germanium has a first concentration of germanium, and performing an oxidation process on the layer of silicon germanium to increase a concentration of germanium in at least a portion of the layer of silicon germanium to a second concentration that is greater than the first concentration of germanium. | 11-08-2012 |
20120292637 | Dual Cavity Etch for Embedded Stressor Regions - Generally, the present disclosure is directed to methods for forming embedded stressor regions in semiconductor devices such as transistor elements and the like. One illustrative method disclosed herein includes forming a first material in first cavities formed in a first active area adjacent to a first channel region of a semiconductor device, wherein the first material induces a first stress in the first channel region. The method also includes, among other things, forming a second material in second cavities formed in a second active area adjacent to a second channel region of the semiconductor device, wherein the second material induces a second stress in the second channel region that is of an opposite type of the first stress in the first channel region, and wherein the first and second cavities are formed during a common etch process. | 11-22-2012 |
20120292671 | Method of Forming Spacers That Provide Enhanced Protection for Gate Electrode Structures - Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming a gate electrode structure above a semiconducting substrate and forming a plurality of spacers proximate the gate electrode structures, wherein the plurality of spacers comprises a first silicon nitride spacer positioned adjacent a sidewall of the gate electrode structure, a generally L-shaped silicon nitride spacer positioned adjacent the first silicon nitride spacer, and a silicon dioxide spacer positioned adjacent the generally L-shaped silicon nitride spacer. | 11-22-2012 |
20120309182 | Method of Forming Sidewall Spacers Having Different Widths Using a Non-Conformal Deposition Process - Disclosed herein is a method of forming sidewall spacers for a semiconductor device. In one example, the method comprises forming a gate electrode structure above a semiconducting substrate. performing a non-conformal deposition process to deposit a layer of spacer material above the gate electrode structure and performing an anisotropic etching process on the layer of spacer material to define a first sidewall spacer proximate a first side of the gate electrode structure and a second sidewall spacer proximate a second side of the gate electrode structure, wherein the first and second sidewall spacers have different widths. | 12-06-2012 |
20130052782 | Implantation of Hydrogen to Improve Gate Insulation Layer-Substrate Interface - Generally, the present disclosure is directed to various methods of making a semiconductor device by implanting hydrogen or hydrogen-containing clusters to improve the interface between a gate insulation layer and the substrate. One illustrative method disclosed herein involves forming a gate insulation layer on a substrate, forming a layer of gate electrode material above the gate insulation material and performing an ion implantation process with a material comprising hydrogen or a hydrogen-containing compound to introduce the hydrogen or hydrogen-containing compound proximate an interface between the gate insulation layer and said substrate with a concentration of the implanted hydrogen or hydrogen-containing compound being at least 1e | 02-28-2013 |
20130052783 | Methods of Forming Stressed Silicon-Carbon Areas in an NMOS Transistor - Disclosed herein are various methods of forming stressed silicon-carbon areas in an NMOS transistor device. In one example, a method disclosed herein includes forming a layer of amorphous carbon above a surface of a semiconducting substrate comprising a plurality of N-doped regions and performing an ion implantation process on the layer of amorphous carbon to dislodge carbon atoms from the layer of amorphous carbon and to drive the dislodged carbon atoms into the N-doped regions in the substrate. | 02-28-2013 |
20130056854 | COMPLEMENTARY STRESS LINER TO IMPROVE DGO/AVT DEVICES AND POLY AND DIFFUSION RESISTORS - Electron mobility and hole mobility is improved in long channel semiconductor devices and resistors by employing complementary stress liners. Embodiments include forming a long channel semiconductor device on a substrate, and forming a complementary stress liner on the semiconductor device. Embodiments include forming a resistor on a substrate, and tuning the resistance of the resistor by forming a complementary stress liner on the resistor. Compressive stress liners are employed for improving electron mobility in n-type devices, and tensile stress liners are employed for improving hole mobility in p-type devices. | 03-07-2013 |
20130065373 | Methods and Systems for Forming Implanted Doped Regions for a Semiconductor Device Using Reduced Temperature Ion Implantation - In one example, a method disclosed herein includes reducing a temperature of at least an implant surface of a semiconducting substrate to a temperature less than −50° C. and after reducing the temperature of the implant surface, performing at least one ion implantation process to implant ions into the substrate with the implant surface at a temperature less than −50° C. | 03-14-2013 |
20130069111 | STRAINED SEMICONDUCTOR DEVICES HAVING ASYMMETRICAL HETEROJUNCTION STRUCTURES AND METHODS FOR THE FABRICATION THEREOF - Embodiments of a strained semiconductor device are provided, as are embodiments of a method for fabricating such a strained semiconductor device. In one embodiment, the method includes providing a partially-fabricated semiconductor device including a semiconductor substrate having a source side and a drain side, a gate stack formed on the semiconductor substrate, and a channel region formed within the semiconductor substrate beneath the gate stack and extending from the source side to the drain side of the semiconductor substrate. A cavity is produced in only one of the source side and the drain side of the semiconductor substrate, and a strain-inducing material is formed within the cavity to create an asymmetric heterojunction structure within the semiconductor substrate. | 03-21-2013 |
20130095620 | METHODS OF FORMING HIGHLY SCALED SEMICONDUCTOR DEVICES USING A DISPOSABLE SPACER TECHNIQUE - In one example, a method disclosed herein includes the steps of forming a first liner layer above a substrate and above gate structures for both a PMOS transistor and an NMOS transistor, and, after forming extension implant regions and halo implant regions, forming a first spacer proximate the gate structures of both the PMOS and NMOS transistors, forming deep source/drain implant regions in the substrate for the PMOS and NMOS transistors, removing the first spacer and, after removing the first spacer, forming a layer of material between the adjacent gate structures, wherein the layer of material occupies at least the space formerly occupied by the first spacer. | 04-18-2013 |
20130146976 | INTEGRATED CIRCUITS FORMED ON STRAINED SUBSTRATES AND INCLUDING RELAXED BUFFER LAYERS AND METHODS FOR THE MANUFACTURE THEREOF - Embodiments of a method for producing an integrated circuit are provided, as are embodiments of an integrated circuit. In one embodiment, the method includes providing a strained substrate having an n-active region and a p-active region, etching a cavity into one of the n-active region and the p-active region, embedding a relaxed buffer layer within the cavity, forming a body of strain material over the relaxed buffer layer having a strain orientation opposite that of the strained substrate, and fabricating n-type and t-type transistors over the n-active and p-active regions, respectively. The channel of the n-type transistor extends within one of the strained substrate and the body of strain material, while the channel of the p-type transistor extends within the other of the strained substrate and the body of strain material. | 06-13-2013 |
20130157421 | METHODS FOR THE FABRICATION OF INTEGRATED CIRCUITS INCLUDING BACK-ETCHING OF RAISED CONDUCTIVE STRUCTURES - Embodiments of a method for fabricating an integrated circuit are provided. In one embodiment, the method includes producing a partially-completed semiconductor device including a substrate, source/drain (S/D) regions, a channel region between the S/D regions, and a gate stack over the channel region. At least one raised electrically-conductive structure is formed over at least one of the S/D regions and separated from the gate stack by a lateral gap. The raised electrically-conductive structure is then back-etched to increase the width of the lateral gap and reduce the parasitic fringing capacitance between the raised electrically-conductive structure and the gate stack during operation of the completed semiconductor device. | 06-20-2013 |
20130175545 | SEMICONDUCTOR DEVICE WITH STRAIN-INDUCING REGIONS AND METHOD THEREOF - Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions. | 07-11-2013 |
20130178034 | Methods of Making Transistor Devices with Elevated Source/Drain Regions to Accommodate Consumption During Metal Silicide Formation Process - Disclosed herein are various semiconductor devices with dual metal silicide regions and to various methods of making such devices. One illustrative method disclosed herein includes the steps of forming an upper portion of a source/drain region that is positioned above a surface of a semiconducting substrate, wherein the upper portion of the source/drain region has an upper surface that is positioned above the surface of the substrate by a distance that is at least equal to a target thickness of a metal silicide region to be formed in the upper portion of the source/drain region and forming the metal silicide region in the upper portion of the source/drain region. | 07-11-2013 |
20130187209 | SEMICONDUCTOR DEVICES HAVING ENCAPSULATED STRESSOR REGIONS AND RELATED FABRICATION METHODS - Apparatus and related fabrication methods are provided for semiconductor device structures having silicon-encapsulated stressor regions. One semiconductor device includes a semiconductor substrate, a gate structure overlying the semiconductor substrate, stressor regions formed in the semiconductor substrate proximate the gate structure, and a silicon material overlying the stressor regions, the silicon material encapsulating the stressor regions. | 07-25-2013 |
20130240988 | TRANSISTORS COMPRISING HIGH-K METAL GATE ELECTRODE STRUCTURES AND EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOYS FORMED IN A LATE STAGE - In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration. | 09-19-2013 |
20130256901 | METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING SUBSTRATE CONTACTS AND INTEGRATED CIRCUITS HAVING SUBSTRATE CONTACTS - Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts are provided. One method includes forming a first trench in a SOI substrate extending through a buried insulating layer to a silicon substrate. A metal silicide region is formed in the silicon substrate exposed by the first trench. A first stress-inducing layer is formed overlying the metal silicide region. A second stress-inducing layer is formed overlying the first stress-inducing layer. An ILD layer of dielectric material is formed overlying the second stress-inducing layer. A second trench is formed extending through the ILD layer and the first and second stress-inducing layers to the metal silicide region. The second trench is filled with a conductive material. | 10-03-2013 |
20130270645 | WORKFUNCTION METAL STACKS FOR A FINAL METAL GATE - Transistor devices are formed with a pMOS and an nMOS workfunction stack of substantially equal thickness after gate patterning. Embodiments include forming n-type and p-type areas in a substrate, forming a pMOS workfunction metal stack layer on both areas, forming a hardmask layer on the pMOS workfunction metal stack layer on the n-type area, removing the pMOS workfunction metal stack layer from the p-type area, forming an nMOS workfunction metal stack layer on the p-type area and on the hardmask layer, and removing the nMOS workfunction metal stack layer from the hardmask layer. | 10-17-2013 |
20130292774 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING RAISED DRAIN AND SOURCE REGIONS AND CORRESPONDING SEMICONDUCTOR DEVICE - A semiconductor device having raised source and drain regions is formed by forming a gate electrode structure on a semiconductor substrate, forming a first spacer structure laterally to the gate electrode structure, forming a semiconductor layer over an exposed surface of the semiconductor substrate at both sides of the gate electrode structure such that a layer portion is formed which is beveled towards the gate electrode with regard to the exposed surface of the semiconductor substrate, and forming a second spacer structure over the first spacer structure, wherein the second spacer structure covers at least a portion of the beveled layer portion. | 11-07-2013 |
20130299891 | FIELD EFFECT TRANSISTORS FOR A FLASH MEMORY COMPRISING A SELF-ALIGNED CHARGE STORAGE REGION - Storage transistors for flash memory areas in semiconductor devices may be provided on the basis of a self-aligned charge storage region. To this end, a floating spacer element may be provided in some illustrative embodiments, while, in other cases, the charge storage region may be efficiently embedded in the electrode material in a self-aligned manner during a replacement gate approach. Consequently, enhanced bit density may be achieved, since additional sophisticated lithography processes for patterning the charge storage region may no longer be required. | 11-14-2013 |
20130302956 | Methods of Forming Semiconductor Devices with Embedded Semiconductor Material as Source/Drain Regions Using a Reduced Number of Spacers - In one example, a method disclosed herein includes the steps of forming a gate structure for a first transistor and a second transistor above a semiconducting substrate, forming a liner layer above the gate structures and performing a plurality of extension ion implant processes through the liner layer to form extension implant regions in the substrate for the first transistor and the second transistor. The method further includes forming a first sidewall spacer proximate the gate structure for the first transistor and a patterned hard mask layer positioned above the second transistor, performing at least one etching process to remove the first sidewall spacer, the patterned hard mask layer and the liner layer, forming a second sidewall spacer proximate both of the gate structures and performing a plurality of source/drain ion implant processes to form deep source/drain implant regions in the substrate for the first transistor and the second transistor. | 11-14-2013 |
20130306967 | ADJUSTING CONFIGURATION OF A MULTIPLE GATE TRANSISTOR BY CONTROLLING INDIVIDUAL FINS - In a sophisticated semiconductor device, FINFET elements may be provided with individually accessible semiconductor fins which may be connected to a controllable interconnect structure for appropriately adjusting the transistor configuration, for instance with respect to current drive capability, replacing defective semiconductor fins and the like. Consequently, different transistor configurations may be obtained on the basis of a standard transistor cell architecture, which may result in increased production yield of highly complex manufacturing strategies in forming non-planar transistor devices. | 11-21-2013 |
20130313572 | SEMICONDUCTOR DEVICE WITH STRAIN-INDUCING REGIONS AND METHOD THEREOF - Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions. | 11-28-2013 |
20130320449 | LATE IN-SITU DOPED SIGE JUNCTIONS FOR PMOS DEVICES ON 28 NM LOW POWER/HIGH PERFORMANCE TECHNOLOGIES USING A SILICON OXIDE ENCAPSULATION, EARLY HALO AND EXTENSION IMPLANTATIONS - A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side of each HKMG gate stack, performing halo/extension implants at each side of each HKMG gate stack, forming an oxide liner and nitride spacers on the oxide spacers of each HKMG gate stack, forming deep source/drain regions at opposite sides of the second HKMG gate stack, forming an oxide hardmask over the second HKMG gate stack, forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack, and removing the oxide hardmask. | 12-05-2013 |
20130320450 | MIDDLE IN-SITU DOPED SIGE JUNCTIONS FOR PMOS DEVICES ON 28 NM LOW POWER/HIGH PERFORMANCE TECHNOLOGIES USING A SILICON OXIDE ENCAPSULATION, EARLY HALO AND EXTENSION IMPLANTATIONS - A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, each including a SiO | 12-05-2013 |
20130323892 | METHODS OF PERFORMING HIGHLY TILTED HALO IMPLANTATION PROCESSES ON SEMICONDUCTOR DEVICES - One illustrative method disclosed herein involves forming first and second gate structures that include a cap layer for a first transistor device and a second transistor device, respectively, wherein the first and second transistors are oriented transverse to one another, performing a first halo ion implant process to form first halo implant regions for the first transistor with the cap layer in position in the first gate structure of the first transistor, removing the cap layer from at least the second gate structure of the second transistor and, after removing the cap layer, performing a second halo ion implant process to form second halo implant regions for the second transistor, wherein the first and second halo implant processes are performed at transverse angles relative to the substrate. | 12-05-2013 |
20130330900 | METHODS OF TAILORING WORK FUNCTION OF SEMICONDUCTOR DEVICES WITH HIGH-K/METAL LAYER GATE STRUCTURES BY PERFORMING A FLUORINE IMPLANT PROCESS - One illustrative method disclosed herein includes forming a plurality of layers of material above a semiconducting substrate, wherein the plurality of layers of material will comprise a gate structure for a transistor, performing a fluorine ion implantation process to implant fluorine ions into at least one of the plurality of layers of material, performing at least one ion implantation process to implant one of a P-type dopant material or an N-type dopant material into the substrate to form source/drain regions for the transistor, and performing an anneal process after the fluorine ion implantation process and the at least one ion implantation process have been performed. | 12-12-2013 |
20140015055 | FINFET STRUCTURES AND METHODS FOR FABRICATING THE SAME - A method is disclosed for fabricating an integrated circuit in a replacement-gate process flow utilizing a dummy-gate structure overlying a plurality of fin structures. The method includes removing the dummy-gate structure to form a first void space, depositing a shaper material to fill the first void space, removing a portion of the plurality of fin structures to form a second void space, epitaxially growing a high carrier mobility material to fill the second void space, removing the shaper material to form a third void space, and depositing a replacement metal gate material to fill the third void space. | 01-16-2014 |
20140015060 | STRESS ENHANCED CMOS CIRCUITS AND METHODS FOR THEIR MANUFACTURE - A method for fabricating a stress enhanced CMOS circuit includes forming a first plurality of MOS transistors at a first pitch and forming a second plurality of MOS transistors at a second pitch. The second pitch is larger than the first pitch. The method further includes depositing a single stress liner overlying the first and second plurality of MOS transistors. The single stress liner is the only stress liner deposited in the fabrication of the stress enhanced CMOS circuit. A stress enhanced CMOS circuit includes a first plurality of MOS transistors formed at a first pitch and a second plurality of MOS transistors formed at a second pitch. The second pitch is larger than the first pitch. The circuit further includes a single stress liner overlying the first and second plurality of MOS transistors. The single stress liner is the only stress liner formed on the stress enhanced CMOS circuit. | 01-16-2014 |
20140042550 | INTEGRATED CIRCUITS WITH IMPROVED SPACERS AND METHODS FOR FABRICATING SAME - Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes simultaneously shielding a shielded region of a semiconductor substrate and exposing a surface of the shielded region of the semiconductor substrate. An ion implantation is performed to form implant areas in a non-shielded region of the semiconductor substrate adjacent the shielded region. Also, the semiconductor substrate is silicided to form a silicided area in the shielded region of the semiconductor substrate. | 02-13-2014 |
20140103449 | OXYGEN FREE RTA ON GATE FIRST HKMG STACKS - A method of fabricating a semiconductor device with improved Vt and the resulting device are disclosed. Embodiments include forming an HKMG stack on a substrate; implanting dopants in active regions of the substrate; and performing an RTA in an environment of nitrogen and no more than 30% oxygen. | 04-17-2014 |
20140113419 | METHODS OF REDUCING MATERIAL LOSS IN ISOLATION STRUCTURES BY INTRODUCING INERT ATOMS INTO OXIDE HARD MASK LAYER USED IN GROWING CHANNEL SEMICONDUCTOR MATERIAL - In one example, the method includes forming a plurality of isolation structures in a semiconducting substrate that define first and second active regions where first and second transistor devices, respectively, will be formed, forming a hard mask layer on a surface of the substrate above the first and second active regions, wherein the hard mask layer comprises at least one of carbon, fluorine, xenon or germanium ions, performing a first etching process to remove a portion of the hard mask layer and expose a surface of one of the first and second active regions, after performing the first etching process, forming a channel semiconductor material on the surface of the active region that was exposed by the first etching process, and after forming the channel semiconductor material, performing a second etching process to remove remaining portions of the hard mask layer that were not removed during the first etching process. | 04-24-2014 |
20140117418 | THREE-DIMENSIONAL SILICON-BASED TRANSISTOR COMPRISING A HIGH-MOBILITY CHANNEL FORMED BY NON-MASKED EPITAXY - Three-dimensional transistors may be formed on the basis of high mobility semiconductor materials, which may be provided locally restricted in the channel region by selective epitaxial growth processes without using a mask material for laterally confining the growing of the high mobility semiconductor material. That is, by controlling process parameters of the selective epitaxial growth process, the cross-sectional shape may be adjusted without requiring a mask material, thereby reducing overall process complexity and providing an additional degree of freedom for adjusting the transistor characteristics in terms of threshold voltage, drive current and electrostatic control of the channel region. | 05-01-2014 |
20140131735 | SOURCE AND DRAIN DOPING USING DOPED RAISED SOURCE AND DRAIN REGIONS - A method comprises providing a semiconductor structure comprising a substrate, an electrically insulating layer on the substrate and a semiconductor feature on the electrically insulating layer. A gate structure is formed on the semiconductor feature. An in situ doped semiconductor material is deposited on portions of the semiconductor feature adjacent the gate structure. Dopant is diffused from the in situ doped semiconductor material into the portions of the semiconductor feature adjacent the gate structure, the diffusion of the dopant into the portions of the semiconductor feature adjacent the gate structure forming doped source and drain regions in the semiconductor feature. | 05-15-2014 |
20140131771 | SEMICONDUCTOR STRUCTURE INCLUDING A SEMICONDUCTOR-ON-INSULATOR REGION AND A BULK REGION, AND METHOD FOR THE FORMATION THEREOF - A structure comprises a semiconductor substrate, a semiconductor-on-insulator region and a bulk region. The semiconductor-on-insulator region comprises a first semiconductor region, a dielectric layer provided between the semiconductor substrate and the first semiconductor region, and a first transistor comprising an active region provided in the first semiconductor region. The dielectric layer provides electrical isolation between the first semiconductor region and the semiconductor substrate. The bulk region comprises a second semiconductor region provided directly on the semiconductor substrate. | 05-15-2014 |
20140151818 | SEMICONDUCTOR DEVICE WITH A SILICON DIOXIDE GATE INSULATION LAYER IMPLANTED WITH A RARE EARTH ELEMENT AND METHODS OF MAKING SUCH A DEVICE - One illustrative method disclosed herein includes forming a gate insulation layer on a semiconducting substrate, performing an ion implantation process to implant a rare earth element into the gate insulation layer, and forming a silicon-containing gate electrode above the gate insulation layer comprising the implanted rare earth element. One illustrative device disclosed herein includes a gate insulation layer positioned on a semiconducting substrate, wherein the gate insulation layer is comprised of silicon dioxide and a rare earth element, and a silicon-containing gate electrode positioned on the gate insulation layer. | 06-05-2014 |
20140183654 | MIDDLE IN-SITU DOPED SIGE JUNCTIONS FOR PMOS DEVICES ON 28 NM LOW POWER/HIGH PERFORMANCE TECHNOLOGIES USING A SILICON OXIDE ENCAPSULATION, EARLY HALO AND EXTENSION IMPLANTATIONS - A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, each including a SiO | 07-03-2014 |
20140197498 | INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH IMPROVED SILICIDE CONTACTS - Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming over a semiconductor substrate a gate structure. The method further includes depositing a non-conformal spacer material around the gate structure. A protection mask is formed over the non-conformal spacer material. The method etches the non-conformal spacer material and protection mask to form a salicidation spacer. Further, a self-aligned silicide contact is formed adjacent the salicidation spacer. | 07-17-2014 |
20140238045 | SEMICONDUCTOR DEVICE COMPRISING A STACKED DIE CONFIGURATION INCLUDING AN INTEGRATED PELTIER ELEMENT - A method of controlling temperature in a semiconductor device that includes a stacked device configuration is disclosed. The method includes providing a Peltier element having a metal-based heat sink formed above a first substrate of the stacked device configuration and a metal-based heat source formed above a second substrate of the stacked device configuration, and establishing a current flow through the Peltier element when the semiconductor device is in a specified operating phase. | 08-28-2014 |
20140246698 | CHANNEL SiGe REMOVAL FROM PFET SOURCE/DRAIN REGION FOR IMPROVED SILICIDE FORMATION IN HKMG TECHNOLOGIES WITHOUT EMBEDDED SiGe - When forming sophisticated P-channel transistors, a semiconductor alloy layer is formed on the surface of the semiconductor layer including the transistor active region. When a metal silicide layer is formed contiguous to this semiconductor alloy layer, an agglomeration of the metal silicide layer into isolated clusters is observed. In order to solve this problem, the present invention proposes a method and a semiconductor device wherein the portion of the semiconductor alloy layer lying on the source and drain regions of the transistor is removed before formation of the metal silicide layer is performed. In this manner, the metal silicide layer is formed so as to be contiguous to the semiconductor layer, and not to the semiconductor alloy layer. | 09-04-2014 |
20140248749 | STRESS MEMORIZATION TECHNIQUE - A method comprises providing a semiconductor structure comprising a gate structure provided over a semiconductor region. An ion implantation process is performed. In the ion implantation process, a first portion of the semiconductor region adjacent the gate structure and a second portion of the semiconductor region adjacent the gate structure are amorphized so that a first amorphized region and a second amorphized region are formed adjacent the gate structure. An atomic layer deposition process is performed. The atomic layer deposition process deposits a layer of a material having an intrinsic stress over the semiconductor structure. A temperature at which at least a part of the atomic layer deposition process is performed and a duration of the at least a part of the atomic layer deposition process are selected such that the first amorphized region and the second amorphized region are re-crystallized during the atomic layer deposition process. | 09-04-2014 |
20140252429 | CONTACT GEOMETRY HAVING A GATE SILICON LENGTH DECOUPLED FROM A TRANSISTOR LENGTH - Methods for forming a semiconductor device are provided. In one embodiment, a gate structure having a gate insulating layer and a gate electrode structure formed on the gate insulating layer is provided. The methods provide reducing a dimension of the gate electrode structure relative to the gate insulating layer along a direction extending in parallel to a direction connecting the source and drain. A semiconductor device structure having a gate structure including a gate insulating layer and a gate electrode structure formed above the gate insulating layer is provided, wherein a dimension of the gate electrode structure extending along a direction which is substantially parallel to a direction being oriented from source to drain is reduced relative to a dimension of the gate insulating layer. According to some examples, gate structures are provided having a gate silicon length which is decoupled from the channel width induced by the gate structure. | 09-11-2014 |
20140252481 | TRANSISTOR INCLUDING A GATE ELECTRODE EXTENDING ALL AROUND ONE OR MORE CHANNEL REGIONS - A semiconductor structure comprises a substrate and a transistor. The transistor comprises a raised source region and a raised drain region provided above the substrate, one or more elongated semiconductor lines, a gate electrode and a gate insulation layer. The one or more elongated semiconductor lines are connected between the raised source region and the raised drain region, wherein a longitudinal direction of each of the one or more elongated semiconductor lines extends substantially along a horizontal direction that is perpendicular to a thickness direction of the substrate. Each of the elongated semiconductor lines comprises a channel region. The gate electrode extends all around each of the channel regions of the one or more elongated semiconductor lines. The gate insulation layer is provided between each of the one or more elongated semiconductor lines and the gate electrode. | 09-11-2014 |
20140252557 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE STRUCTURES - Semiconductor device structures and methods for forming a semiconductor device are provided. In embodiments, one or more fins are provided, each of the one or more fins having a lower portion and an upper portion disposed on the lower portion. The lower portion is embedded in a first insulating material. The shape of the upper portion is at least one of a substantially triangular shape and a substantially rounded shape and a substantially trapezoidal shape. Furthermore, a layer of a second insulating material different from the first insulating material is formed on the upper portion. | 09-11-2014 |
20140256097 | METHODS FOR FORMING INTEGRATED CIRCUIT SYSTEMS EMPLOYING FLUORINE DOPING - A method for forming a semiconductor device is provided which includes providing a gate structure in an active region of a semiconductor substrate, wherein the gate structure includes a gate insulating layer having a high-k material, a gate metal layer and a gate electrode layer, forming sidewall spacers adjacent to the gate structure and, thereafter, performing a fluorine implantation process. Also a method for forming a CMOS integrated circuit structure is provided which includes providing a semiconductor substrate with a first active region and a second active region, forming a first gate structure in the first active region and a second gate structure in the second active region, wherein each gate structure includes a gate insulating layer having a high-k material, a gate metal layer and a gate electrode layer, forming sidewall spacers adjacent to each of the first and second gate structures and, thereafter, performing a fluorine implantation process. | 09-11-2014 |
20140256135 | METHODS OF REMOVING GATE CAP LAYERS IN CMOS APPLICATIONS - One illustrative method disclosed herein includes the steps of forming a masking layer that covers a P-type transistor and exposes at least a gate cap layer of an N-type transistor, performing a first etching process through the masking layer to remove a portion of the gate cap of the N-type transistor so as to thereby define a reduced thickness gate cap layer for the N-type transistor, removing the masking layer, and performing a common second etching process on the P-type transistor and the N-type transistor that removes a gate cap layer of the P-type transistor and the reduced thickness gate cap of the N-type transistor. | 09-11-2014 |
20140256137 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING AN IMPLANTATION OF IONS INTO A LAYER OF SPACER MATERIAL - A method includes providing a semiconductor structure including a substrate and a transistor element. A layer of a spacer material is deposited over the substrate and the gate structure, wherein the deposited layer of spacer material has an intrinsic stress. Ions are implanted into the layer of spacer material. After the deposition of the layer of spacer material and the implantation of ions into the layer of spacer material, a sidewall spacer is formed at sidewalls of the gate structure from the layer of spacer material. | 09-11-2014 |
20140264347 | TRANSISTOR WITH EMBEDDED STRAIN-INDUCING MATERIAL FORMED IN CAVITIES BASED ON AN AMORPHIZATION PROCESS AND A HEAT TREATMENT - When forming cavities in active regions of semiconductor devices in order to incorporate a strain-inducing semiconductor material, an improved shape of the cavities may be achieved by using an amorphization process and a heat treatment so as to selectively modify the etch behavior of exposed portions of the active regions and to adjust the shape of the amorphous regions. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility. Consequently, the efficiency of the strain-inducing technique may be improved. | 09-18-2014 |
20140264349 | LOW THERMAL BUDGET SCHEMES IN SEMICONDUCTOR DEVICE FABRICATION - In aspects of the present invention, a method of forming a semiconductor device is disclosed, wherein amorphous regions are formed at an early stage during fabrication and the amorphous regions are conserved during subsequent processing sequences, and an intermediate semiconductor device structure with amorphous regions are provided at an early stage during fabrication. Herein a gate structure is provided over a semiconductor substrate and amorphous regions are formed adjacent the gate structure. Source/drain extension regions or source/drain regions are formed in the amorphous regions. In some illustrative embodiments, fluorine may be implanted into the amorphous regions. After the source/drain extension regions and/or the source/drain regions are formed, a rapid thermal anneal process is performed. | 09-18-2014 |
20140264386 | PERFORMANCE ENHANCEMENT IN PMOS AND NMOS TRANSISTORS ON THE BASIS OF SILICON/CARBON MATERIAL - A semiconductor device includes a first transistor having first drain and source regions and a first channel region and a second transistor having second drain and source regions and a second channel region. A first silicon/carbon alloy material is embedded in the first drain and source regions, the first silicon/carbon alloy material inducing a first strain component along a first channel length direction of the first channel region. A second silicon/carbon alloy material is embedded in the second drain and source regions, the second silicon/carbon alloy material inducing a second strain component along a second channel length direction of the second channel region, wherein the second strain component is of an opposite type of the first strain component. | 09-18-2014 |
20140264484 | FLUORINE-DOPED CHANNEL SILICON-GERMANIUM LAYER - Methods for forming P-type channel metal-oxide-semiconductor field effect transistors (PMOSFETs) with improved interface roughness at the channel silicon-germanium (cSiGe) layer and the resulting devices are disclosed. Embodiments may include designating a region in a substrate as a channel region, forming a cSiGe layer above the designated channel region, and implanting fluorine directly into the cSiGe layer. Embodiments may alternatively include implanting fluorine into a region in a silicon substrate designated a channel region, forming a cSiGe layer above the designated channel region, and heating the silicon substrate and the cSiGe layer to diffuse the fluorine into the cSiGe layer. | 09-18-2014 |
20140264617 | HK/MG PROCESS FLOWS FOR P-TYPE SEMICONDUCTOR DEVICES - The present disclosure provides semiconductor device structures with a first PMOS active region and a second PMOS active region provided within a semiconductor substrate. A silicon germanium channel layer is only formed over the second PMOS active region. Gate electrodes are formed over the first and second PMOS active regions, wherein the gate electrode over the second PMOS active region is formed over the silicon germanium channel. | 09-18-2014 |
20140264626 | METHOD FOR FORMING A GATE ELECTRODE OF A SEMICONDUCTOR DEVICE, GATE ELECTRODE STRUCTURE FOR A SEMICONDUCTOR DEVICE AND ACCORDING SEMICONDUCTOR DEVICE STRUCTURE - The present disclosure provides, in some aspects, a gate electrode structure for a semiconductor device. In some illustrative embodiments herein, the gate electrode structure includes a first high-k dielectric layer over a first active region of a semiconductor substrate and a second high-k dielectric layer on the first high-k dielectric layer. The first high-k dielectric layer has a metal species incorporated therein for adjusting the work function of the first high-k dielectric layer. | 09-18-2014 |
20140264632 | SEMICONDUCTOR STRUCTURE INCLUDING A TRANSISTOR HAVING A LAYER OF A STRESS-CREATING MATERIAL AND METHOD FOR THE FORMATION THEREOF - A semiconductor structure is provided including a transistor, the transistor including one or more elongated semiconductor regions, each of the one or more elongated semiconductor regions having a channel region, a gate electrode, wherein the gate electrode is provided at least at two opposite sides of each of the one or more elongated semiconductor regions, and a layer of a stress-creating material, the stress-creating material providing a variable stress, wherein the layer of stress-creating material is arranged to provide a stress at least in the channel region of each of the one or more elongated semiconductor regions, the stress provided in the channel region of each of the one or more elongated semiconductor regions being variable. | 09-18-2014 |
20140273375 | METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH SEMICONDUCTOR SUBSTRATE PROTECTION - Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. A first sacrificial oxide layer is formed overlying the semiconductor substrate and a first implant mask is patterned overlying the first sacrificial oxide layer to expose a portion of the first sacrificial oxide layer adjacent the gate electrode structure. Conductivity determining ions are implanted into the semiconductor substrate, through the first sacrificial oxide layer. The first implant mask and the first sacrificial oxide layer are removed after implanting the conductivity determining ions into the semiconductor substrate. | 09-18-2014 |
20140319620 | METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH POLYCRYSTALLINE SILICON RESISTOR STRUCTURES USING A REPLACMENT GATE PROCESS FLOW, AND THE INTEGRATED CIRCUITS FABRICATED THEREBY - Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a first transistor structure that includes an etch-stop material layer, a first workfunction material layer disposed over the etch-stop material layer, a second workfunction material layer disposed over the first workfunction material layer, and a metal fill material disposed over the second workfunction material layer. The integrated circuit further includes a second transistor structure that includes a layer of the etch-stop material, a layer of the second workfunction material disposed over the etch-stop material layer, and a layer of the metal fill material disposed over the second workfunction material layer. Still further, the integrated circuit includes a resistor structure that includes a layer of the etch-stop material, a layer of the metal fill material disposed over the etch-stop material layer, and a silicon material layer disposed over the metal fill material layer. | 10-30-2014 |
20140342514 | METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH THE IMPLANTATION OF NITROGEN - A method for fabricating an integrated circuit includes forming a first gate electrode structure above a first active region and a second gate electrode structure above a second active region, forming a sacrificial spacer on sidewalls of the first and second gate electrode structures, and forming deep drain and source regions selectively in the first and second active regions by using the sacrificial spacer as an implantation mask. The method further includes forming drain and source extension and halo regions in the first and second active regions after removal of the sacrificial spacer and forming a nitrogen implant region in the halo region of the first active region after formation of the drain and source extension and halo regions. | 11-20-2014 |
20140357042 | SPACER STRESS RELAXATION - A known problem when manufacturing transistors is the stress undesirably introduced by the spacers into the transistor channel region. In order to solve this problem, the present invention proposes an ion implantation aimed at relaxing the stress of the spacer materials. The relax implantation is performed after the spacer has been completely formed. The relax implantation may be performed after a silicidation process or after an implantation step in the source and drain regions followed by an activation annealing and before performing the silicidation process. | 12-04-2014 |
20140361385 | METHOD OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE EMPLOYING FLUORINE DOPING AND ACCORDING SEMICONDUCTOR DEVICE STRUCTURE - Methods of forming a semiconductor device structure at advanced technology nodes and respective semiconductor device structures are provided at advanced technology nodes, i.e., smaller than 100 nm. In some illustrative embodiments, a fluorine implantation process for implanting fluorine at least into a polysilicon layer formed over a dielectric layer structure is performed prior to patterning the gate dielectric layer structure and the polysilicon layer for forming a gate structure and implanting source and drain regions at opposing sides of the gate structure. | 12-11-2014 |
20150014777 | CHANNEL SEMICONDUCTOR ALLOY LAYER GROWTH ADJUSTED BY IMPURITY ION IMPLANTATION - The present disclosure provides an improved method for forming a thin semiconductor alloy layer on top of a semiconductor layer. The proposed method relies on an implantation of appropriate impurity species before performing deposition of the semiconductor alloy film. The implanted species cause the semiconductor alloy layer to be less unstable to wet and dry etches performed on the device surface after deposition. Thus, the thickness uniformity of the semiconductor alloy film may be substantially increased if the film is deposited after performing the implantation. On the other hand, some implanted impurities have been found to decrease the growth rate of the semiconductor alloy layer. Thus, by selectively implanting appropriate impurities in predetermined portions of a wafer, a single deposition step may be used in order to form a semiconductor alloy layer with a thickness which may be locally adjusted at will. | 01-15-2015 |
20150021703 | GATE OXIDE QUALITY FOR COMPLEX MOSFET DEVICES - In various aspects, methods of forming a semiconductor device and semiconductor devices are provided. In some illustrative embodiments herein, a silicon/germanium layer is provided on a semiconductor substrate. On the silicon/germanium layer, at least one insulating material layer is formed. After having performed a thermal annealing process, the at least one insulating material layer is removed in subsequent process sequences such that the silicon/germanium layer is at least partially exposed. In further processing sequences which are to be subsequently applied, a gate electrode is formed on the exposed silicon/germanium layer. | 01-22-2015 |
20150041910 | INTEGRATED CIRCUITS WITH A PARTIALLY-DEPLETED REGION FORMED OVER A BULK SILICON SUBSTRATE AND METHODS FOR FABRICATING THE SAME - Integrated circuits and methods of fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a bulk silicon substrate that is lightly-doped with a first dopant type divided into a first device region and a second device region, and a well region that is lightly-doped with a second dopant type formed in the second device region. The integrate circuit further includes heavily-doped source/drain extension regions of the first dopant type aligned to a first gate electrode structure and heavily-doped source/drain extension regions of the second dopant type aligned to a second gate electrode structure, and an intermediately-doped halo region of the second dopant type formed underneath the first gate electrode structure and an intermediately-doped halo regions of the first dopant type underneath the second gate electrode structure. Still further, the integrated circuit includes heavily-doped source/drain regions. | 02-12-2015 |
20150050787 | FULLY SILICIDED GATE FORMED ACCORDING TO THE GATE-FIRST HKMG APPROACH - When forming field-effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art, which may overcome this problem. However, formation of a fully silicided gate is hindered by the fact that silicidation of the source and drain regions and of the gate electrode are normally performed simultaneously. The claimed method proposes two consecutive silicidation processes which are decoupled with respect to each other. During the first silicidation process, a metal silicide is formed forming an interface with the source and drain regions and without affecting the gate electrode. During the second silicidation, a metal silicide layer having an interface with the gate electrode is formed, without affecting the transistor source and drain regions. | 02-19-2015 |
20150054072 | LATE IN-SITU DOPED SIGE JUNCTIONS FOR PMOS DEVICES ON 28 NM LOW POWER/HIGH PERFORMANCE TECHNOLOGIES USING A SILICON OXIDE ENCAPSULATION, EARLY HALO AND EXTENSION IMPLANTATIONS - A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side of each HKMG gate stack, performing halo/extension implants at each side of each HKMG gate stack, forming an oxide liner and nitride spacers on the oxide spacers of each HKMG gate stack, forming deep source/drain regions at opposite sides of the second HKMG gate stack, forming an oxide hardmask over the second HKMG gate stack, forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack, and removing the oxide hardmask. | 02-26-2015 |
20150076618 | INTEGRATED CIRCUITS WITH A CORRUGATED GATE, AND METHODS FOR PRODUCING THE SAME - Methods and apparatus are provided for an integrated circuit. The method includes forming a corrugation mask on a substrate, and forming a channel corrugation on the substrate. The corrugation mask is removed from the substrate, and a gate insulator is formed overlying the channel corrugation on the substrate. A gate is formed overlying the channel gate insulator. | 03-19-2015 |