Patent application number | Description | Published |
20100332805 | Remapping source Registers to aid instruction scheduling within a processor - An out-of-order renaming processor is provided with a register file within which aliasing between registers of different sizes may occur. In this way a program instruction having a source register of a double precision size may alias with two single precision registers being used as destinations of one or more preceding program instructions. In order to track this data dependency the double precision register may be remapped into a micro-operation specifying two single precision registers as its source register. In this way, scheduling circuitry may use its existing hazard detection and management mechanisms to handle potential data hazards and dependencies. Not all program instructions having such data hazards between registers of different sizes are handled by this source register remapping. For these other program instructions a slower mechanism for dealing with the data dependency hazard is provided. This slower mechanism may, for example, be to drain all the preceding micro-operations from the execution pipelines before issuing the micro-operation having the data hazard. | 12-30-2010 |
20110016338 | Storage of system configuration data on a processor - A processor is disclosed having a plurality of general purpose registers for storing data for processing by the processor; a set of system configuration registers for storing data indicative of a current configuration of the processor; the system configuration registers being located together in a register file; and at least some of the set of system configuration registers having a shadow register for storing a duplicate value remote from the register file, the shadow register being located close to a component that the shadow register stores a configuration value for. | 01-20-2011 |
20110208950 | PROCESSES, CIRCUITS, DEVICES, AND SYSTEMS FOR SCOREBOARD AND OTHER PROCESSOR IMPROVEMENTS - A method of instruction issue ( | 08-25-2011 |
20120124301 | Buffer store with a main store and an auxiliary store - A loop buffer is provided with a main store | 05-17-2012 |
20120124337 | Size mis-match hazard detection - An out-of-order processor | 05-17-2012 |
20120124340 | Retirement serialisation of status register access operations - A processor | 05-17-2012 |
20120124346 | Decoding conditional program instructions - A processor | 05-17-2012 |
20130145126 | REGISTER MAPPING WITH MULTIPLE INSTRUCTION SETS - A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file | 06-06-2013 |
20130145127 | ZERO VALUE PREFIXES FOR OPERANDS OF DIFFERING BIT-WIDTHS - A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural register value has a fixed bit width irrespective of the bit width of the destination operand being written thereto. Instead of adding these zero values everywhere in the data path, they are instead represented by zero flags in at least the physical registers utilised for register renaming operations and in the result queue prior to results being written to the architectural register file. This saves circuitry resources and reduces energy consumption. | 06-06-2013 |
20150082007 | REGISTER MAPPING WITH MULTIPLE INSTRUCTION SETS - A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file | 03-19-2015 |