Patent application number | Description | Published |
20100052059 | FINFET PROCESS COMPATIBLE NATIVE TRANSISTOR - Provided is a top-channel only finFET device. The methods and devices described herein may provide a native device that is compatible with a finFET process flow. A gate may be formed on the top of a fin providing the channel region of the device. In an embodiment, the gate is provided only on one side of the channel, for example, on the top of the fin. The sidewalls of the fin including channel may abut an isolation structure. In an embodiment, isolation structures are formed between the fins to provide a planar surface for the formation of a gate. | 03-04-2010 |
20100103570 | Circuit and Method for Power Clamp Triggered Dual SCR ESD Protection - Circuit and method for RC power clamp triggered dual SCR ESD protection. In an integrated circuit, a protected pad is coupled to an upper SCR circuit and a lower SCR circuit; and both are coupled to the RC power clamp circuit, which is coupled between the positive voltage supply and the ground voltage supply. A structure for ESD protection is disclosed having a first well of a first conductivity type adjacent to a second well of a second conductivity type, the boundary forming a p-n junction, and a pad contact diffusion region in each well electrically coupled to a pad terminal; additional diffusions are provided proximate to and electrically isolated from the pad contact diffusion regions, the diffusion regions and first and second wells form two SCR devices. These SCR devices are triggered, during an ESD event, by current injected into the respective wells by an RC power clamp circuit. | 04-29-2010 |
20100155776 | Forming ESD Diodes and BJTs Using FinFET Compatible Processes - A method of forming an electrostatic discharging (ESD) device includes forming a first and a second semiconductor fin over a substrate and adjacent to each other; epitaxially growing a semiconductor material on the first and the second semiconductor fins, wherein a first portion of the semiconductor material grown from the first semiconductor fin joins a second portion of the semiconductor material grown from the second semiconductor fin; and implanting a first end and a second end of the semiconductor material and first end portions of the first and the second semiconductor fins to form a first and a second implant region, respectively. A P-N junction is formed between the first end and the second end of the semiconductor material. The P-N junction is a junction of an ESD diode, or a junction in an NPN or a PNP BJT. | 06-24-2010 |
20100202184 | One-Time Programmable Fuse with Ultra Low Programming Current - A method of operating a FinFET fuse includes providing the FinFET fuse including a drain, a gate, a source, and a channel between the drain and the source; and applying a program voltage to one of the source and the drain of the FinFET fuse to cause a punch-through in the channel of the FinFET fuse. The method further includes determining a program state of the FinFET fuse. | 08-12-2010 |
20100296213 | ESD Protection for FinFETs - An embodiment is a semiconductor device comprising a receiver circuit comprising fin field effect transistors (FinFETs), a transceiver circuit comprising FinFETs, and a transmit bus electrically coupling the receiver circuit and the transceiver circuit, wherein the receiver circuit and the transceiver circuit each further comprises an electrostatic discharge protection circuit comprising planar transistors electrically coupled to the transmit bus. Other embodiments may further comprise a power clamp electrically coupling a first power bus and a first ground bus, a power clamp electrically coupling a second power bus and a second ground bus, or at least two diodes electrically cross-coupling the first ground bus and the second ground bus. Also, the planar transistors of the transceiver circuit and the receiver circuit may each comprise a planar PMOS transistor and a planar NMOS transistor. | 11-25-2010 |
20120037956 | Circuit and Method for Power Clamp Triggered Dual SCR ESD Protection - Circuit and method for RC power clamp triggered dual SCR ESD protection. In an integrated circuit, a protected pad is coupled to an upper SCR circuit and a lower SCR circuit; and both are coupled to the RC power clamp circuit, which is coupled between the positive voltage supply and the ground voltage supply. A structure for ESD protection is disclosed having a first well of a first conductivity type adjacent to a second well of a second conductivity type, the boundary forming a p-n junction, and a pad contact diffusion region in each well electrically coupled to a pad terminal; additional diffusions are provided proximate to and electrically isolated from the pad contact diffusion regions, the diffusion regions and first and second wells form two SCR devices. These SCR devices are triggered, during an ESD event, by current injected into the respective wells by an RC power clamp circuit. | 02-16-2012 |
20120126329 | FINFET PROCESS COMPATIBLE NATIVE TRANSISTOR - Provided is a top-channel only finFET device. The devices described herein may provide a native device that is compatible with a finFET process flow. A gate may be formed on the top of a fin providing the channel region of the device. In an embodiment, the gate is provided only on one side of the channel, for example, on the top of the fin. The sidewalls of the fin including channel may abut an isolation structure. In an embodiment, isolation structures are formed between the fins to provide a planar surface for the formation of a gate. | 05-24-2012 |
20120168906 | ESD Protection Device with Tunable Design Windows - An electrostatic discharge (ESD) device includes a high-voltage well (HVW) region of a first conductivity type; a first heavily doped region of a second conductivity type opposite the first conductivity type over the HVW region; and a doped region of the first conductivity type contacting the first heavily doped region and the HVW region. The doped region is under the first heavily doped region and over the HVW region. The doped region has a first impurity concentration higher than a second impurity concentration of the HVW region and lower than a third impurity concentration of the first heavily doped region. The ESD device further includes a second heavily doped region of the second conductivity type over the HVW region; and a third heavily doped region of the first conductivity type over and contacting the HVW region. | 07-05-2012 |
20120211869 | Low Leakage Diodes - A diode includes an anode of a first conductivity type; a first cathode of the first conductivity type; and a second cathode of a second conductivity type opposite the first conductivity type. A lightly-doped region of the first conductivity type is under and vertically overlaps the anode and the first and the second cathodes. The portion of the lightly-doped region directly under the second cathode is fully depleted at a state when no bias voltage is applied between the anode and the second cathode. | 08-23-2012 |
20130009204 | BIDIRECTIONAL DUAL-SCR CIRCUIT FOR ESD PROTECTION - An ESD protection circuit includes a pad of an IC, circuitry coupled to the pad for buffering data, an RC power clamp on the IC, and first and second silicon controlled rectifier (SCR) circuits. The RC power clamp is coupled between a positive power supply terminal and a ground terminal. The first SCR circuit is coupled between the pad and the positive power supply terminal. The first SCR circuit has a first trigger input coupled to the RC power clamp circuit. The second SCR circuit is coupled between the pad and the ground terminal. The second SCR circuit has a second trigger input coupled to the RC power clamp circuit. At least one of the SCR circuits includes a gated diode configured to selectively provide a short or relatively conductive electrical path between the pad and one of the positive power supply terminal and the ground terminal. | 01-10-2013 |
20130075854 | High Voltage ESD Protection Apparatus - An ESD protection apparatus comprises a metal contact formed on the emitter of a transistor. The metal contact has a different conductivity type from the emitter. In addition, the metal contact and the emitter of the transistor form a diode connected in series with the transistor. The diode connected in series with the transistor provides extra headroom for the breakdown voltage of the ESD protection apparatus. | 03-28-2013 |
20130075863 | ESD Protection Apparatus - An ESD protection apparatus comprises a substrate, a low voltage p-type well and a low voltage n-type well formed on the substrate. The ESD protection device further comprises a first P+ region formed on the low voltage p-type well and a second P+ region formed on the low voltage n-type well. The first P+ region and the second P+ region are separated by a first isolation region. The breakdown voltage of the ESD protection apparatus is tunable by adjusting the length of the first isolation region. | 03-28-2013 |
20130083438 | ESD Protection for FinFETs - An embodiment is a semiconductor device comprising a receiver circuit comprising fin field effect transistors (FinFETs), a transceiver circuit comprising FinFETs, and a transmit bus electrically coupling the receiver circuit and the transceiver circuit, wherein the receiver circuit and the transceiver circuit each further comprises an electrostatic discharge protection circuit comprising planar transistors electrically coupled to the transmit bus. Other embodiments may further comprise a power clamp electrically coupling a first power bus and a first ground bus, a power clamp electrically coupling a second power bus and a second ground bus, or at least two diodes electrically cross-coupling the first ground bus and the second ground bus. Also, the planar transistors of the transceiver circuit and the receiver circuit may each comprise a planar PMOS transistor and a planar NMOS transistor. | 04-04-2013 |
20130093010 | High-Voltage Mosfets Having Current Diversion Region in Substrate Near Fieldplate - To limit or prevent current crowding, various HV-MOSFET embodiments include a current diversion region disposed near a drain region of an HV-MOSFET and near an upper surface of the semiconductor substrate. In some embodiments, the current diversion region is disposed near a field plate of the HV-MOSFET, wherein the field plate can also help to reduce or “smooth” electric fields near the drain to help limit current crowding. In some embodiments, the current diversion region is a p-doped, n-doped, or intrinsic region that is at a floating voltage potential. This current diversion region can push current deeper into the substrate of the HV-MOSFET (relative to conventional HV-MOSFETs), thereby reducing current crowding during ESD events. By reducing current crowding, the current diversion region makes the HV-MOSFETs disclosed herein more impervious to ESD events and, therefore, more reliable in real-world applications. | 04-18-2013 |
20130093038 | Schottky Diode - An embodiment is a semiconductor structure. The semiconductor structure comprises a p-type region in a substrate; a first n-type well in the p-type region; a first p-type well in the p-type region; and a second p-type well in the first p-type well. A concentration of a p-type impurity in the first p-type well is less than a concentration of a p-type impurity in the second p-type well. Additional embodiments further comprise further n-type and p-type wells in the substrate. A method for forming a semiconductor structure is also disclosed. | 04-18-2013 |
20130277745 | ELECTROSTATIC DISCHARGE (ESD) GUARD RING PROTECTIVE STRUCTURE - An ESD protection circuit includes a MOS transistor of a first type, a MOS transistor of a second type, an I/O pad, and first, second, and third guard rings of the first, second, and first types, respectively. The MOS transistor of the first type has a source coupled to a first node having a first voltage, and a drain coupled to a second node. The MOS transistor of the second type has a drain coupled to the second node, and a source coupled to a third node having a second voltage lower than the first voltage. The I/O pad is coupled to the second node. The first, second, and third guard rings are positioned around the MOS transistor of the second type. | 10-24-2013 |
20130285112 | HIGH-TRIGGER CURRENT SCR - An SCR includes a first doped region of a first type having a first doping concentration. A first well of the first type and a first well of a second type are disposed in upper areas of the first doped region of the first type such that the first well of the second type is laterally spaced from the first well of the first type by a non-zero distance. A second doped region of the first type has a second doping concentration that is greater than the first doping concentration and is disposed in the first well of the second type to form an anode of the SCR. A first doped region of the second type is disposed in the first well of the first type and forms a cathode of the SCR. | 10-31-2013 |
20130285209 | Low Leakage Diodes - A diode includes an anode of a first conductivity type; a first cathode of the first conductivity type; and a second cathode of a second conductivity type opposite the first conductivity type. A lightly-doped region of the first conductivity type is under and vertically overlaps the anode and the first and the second cathodes. The portion of the lightly-doped region directly under the second cathode is fully depleted at a state when no bias voltage is applied between the anode and the second cathode. | 10-31-2013 |
20130307080 | SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INTERCONNECTS - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant. | 11-21-2013 |
20130334648 | Methods and Apparatus for High Voltage Diodes - High voltage diodes are disclosed. A semiconductor device is provided having a P well region; an N well region adjacent to the P well region and forming a p-n junction with the P well region; a P+ region forming an anode at the upper surface of the semiconductor substrate in the P well region; an N+ region forming a cathode at the upper surface of the semiconductor substrate in the N well region; and an isolation structure formed over the upper surface of the semiconductor substrate between the anode and the cathode and electrically isolating the anode and cathode including a first dielectric layer overlying a portion of the upper surface of the semiconductor substrate, and a second dielectric layer overlying a portion of the first dielectric layer and a portion of the upper surface of the semiconductor substrate. Methods for forming the devices are disclosed. | 12-19-2013 |
20130341676 | Methods and Apparatus for Increased Holding Voltage in Silicon Controlled Rectifiers for ESD Protection - Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed. | 12-26-2013 |
20140035039 | ELECTROSTATIC DISCHARGE (ESD) GUARD RING PROTECTIVE STRUCTURE - An electrostatic discharge (ESD) protection circuit structure includes several diffusion regions and a MOS transistor. The circuit structure includes a first diffusion region of a first type (e.g., P-type or N-type) formed in a first well of the first type, a second diffusion region of the first type formed in the first well of the first type, and a first diffusion region of a second type (e.g., N-type or P-type) formed in a first well of the second type. The first well of the second type is formed in the first well of the first type. The MOS transistor is of the second type and includes a drain formed by a second diffusion region of the second type formed in a second well of the second type bordering the first well of the first type. | 02-06-2014 |
20140061848 | Schottky Isolated NMOS for Latch-Up Prevention - An integrated circuit structure includes a substrate, a semiconductor device supported by the substrate, and a guard ring structure disposed around the semiconductor device, the guard ring structure forming a Schottky junction. In an embodiment, the Schottky junction is formed from a p-type metal contact and an n-type guard ring. In an embodiment, the guard ring structure is electrically coupled to a positive or negative supply voltage. | 03-06-2014 |
20140062580 | Diode Formed of PMOSFET and Schottky Diodes - A P-type Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) includes a gate, a first source/drain region connected to the gate, and a second source/drain region on an opposite side of the gate than the first source/drain region. A first Schottky diode includes a first anode connected to the first source/drain region, and a first cathode connected to a body of the PMOSFET. A second Schottky diode includes a second anode connected to the second source/drain region, and a second cathode connected to the body of the PMOSFET. | 03-06-2014 |
20140094009 | SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INTERCONNECTS - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant. | 04-03-2014 |
20140131765 | ESD Devices Comprising Semiconductor Fins - A device includes a semiconductor substrate, and an insulation region extending from a top surface of the semiconductor substrate into the semiconductor substrate. The device further includes a first node and a second node, and an Electro-Static Discharge (ESD) device coupled between the first node and the second node. The ESD device includes a semiconductor fin adjacent to and over a top surface of the insulation region. The ESD device is configured to, in response to an ESD transient on the first node, conduct a current from the first node to the second node. | 05-15-2014 |
20140145249 | Diode Structure Compatible with FinFET Process - An embodiment integrated circuit (e.g., diode) and method of making the same. The embodiment integrated circuit includes a well having a first doping type formed over a substrate having the first doping type, the well including a fin, a source formed over the well on a first side of the fin, the source having a second doping type, a drain formed over the well on a second side of the fin, the drain having the first doping type, and a gate oxide formed over the fin, the gate oxide laterally spaced apart from the source by a back off region of the fin. The integrated circuit is compatible with a FinFET fabrication process. | 05-29-2014 |
20140183518 | N-TYPE METAL OXIDE SEMICONDUCTOR (NMOS) TRANSISTOR FOR ELECTROSTATIC DISCHARGE (ESD) - One or more techniques or systems for forming an n-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD) are provided herein. In some embodiments, the NMOS transistor includes a first region, a first n-type plus (NP) region, a first p-type plus (PP) region, a second NP region, a second PP region, a shallow trench isolation (STI) region, and a gate stack. In some embodiments, the first PP region is between the first NP region and the second NP region. In some embodiments, the second NP region is between the first PP region and the second PP region, the gate stack is between the first PP region and the second NP region, the STI region is between the second NP region and the second PP region. Accordingly, the first PP region enables ESD current to discharge based on a low trigger voltage for the NMOS transistor. | 07-03-2014 |
20140183610 | Decoupling Capacitor for FinFET Compatible Process - A decoupling capacitor formed from a fin field-effect transistor (FinFET) and method of using the same are provided. An embodiment decoupling capacitor includes a fin field-effect transistor (FinFET) having a semiconductor substrate supporting a gate stack, a source, and a drain, a first terminal coupled to the semiconductor substrate and to the gate stack, the first terminal configured to couple with a first power rail, and a second terminal coupled to the source and to the drain, the second terminal configured to couple with a second power rail having a higher potential than the first power rail. | 07-03-2014 |
20140184277 | MULTI-GATE HIGH VOLTAGE DEVICE - A high voltage semiconductor device, particularly a device including a number of high breakdown voltage transistors having a common drain, first well, and insulating structure between the gate and the drain as well as method for using the same is provided in this disclosure. The high breakdown voltage transistors in the device together are in an elliptical shape. A second well region, gate structure, and a source region are partially overlapping discontinuous elliptical rings having at least two discontinuities or openings in a top view. The respective discontinuities or openings define each of the high breakdown voltage transistors. | 07-03-2014 |
20140193959 | FinFET Body Contact and Method of Making Same - A semiconductor device may include body contacts on a finFET device for ESD protection. The semiconductor device comprises a semiconductor fin, a source/drain region and a body contact. The source/drain region and the body contact are in the semiconductor fin. A portion of the fin is laterally between the source/drain region and the body contact. The semiconductor fin is on a substrate. | 07-10-2014 |
20140217461 | BIDIRECTIONAL DUAL-SCR CIRTCUIT FOR ESD PROTECTION - An ESD protection circuit includes at least a first and a second silicon controlled rectifier (SCR) circuits. The first SCR circuit is coupled between the pad and the positive power supply terminal. The second SCR circuit is coupled between the pad and the ground terminal. At least one of the SCR circuits is configured to selectively provide a short or relatively conductive electrical path between the pad and one of the positive power supply terminal and the ground terminal. | 08-07-2014 |
20140264604 | FinFET Having Source-Drain Sidewall Spacers with Reduced Heights - An integrated circuit device includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, and a semiconductor fin protruding above the insulation regions. The insulation regions include a first portion and a second portion, with the first portion and the second portion on opposite sides of the semiconductor fin. The semiconductor fin has a first height. A gate stack is overlying a middle portion of the semiconductor fin. A fin spacer is on a sidewall of an end portion of the semiconductor fin. The fin spacer has a second height, wherein the first height is greater than about two times the second height. | 09-18-2014 |
20140367829 | ESD Protection Apparatus - An ESD protection apparatus comprises an n-type substrate with a first doping density, a low voltage n-type well in the substrate, a low voltage p-type well in the substrate, a first n-type semiconductor region over the low voltage n-type well and a second n-type semiconductor region over the low voltage p-type well, wherein the first semiconductor region and the second semiconductor region are separated by a first isolation region. | 12-18-2014 |
20140376133 | ESD PROTECTION CIRCUIT CELL - A device includes a first bidirectional PNP circuit coupled to a first output of an communication circuit, and a second bidirectional PNP circuit coupling to a second output of the communication circuit. The first and second bi-direction PNP circuits have coupled outputs and a first breakdown voltage. A third bidirectional PNP circuit is coupled to ground via the coupled outputs of the first bidirectional PNP circuit and of the second bidirectional PNP circuit. The third bidirectional PNP circuit has a second breakdown voltage. In some arrangements, a sum of the first breakdown voltage and the second breakdown voltage exceeds 60 volts. The communication circuit can be an automotive application circuit for a serial automotive communication application. The first and second bidirectional transistor circuits can form a part of a cell of an integrated circuit having an isolation structure to sustain high voltage. | 12-25-2014 |
20150069520 | Backside Contacts for Integrated Circuit Devices - A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a transistor formed at a front side of the semiconductor substrate. A source/drain region of the transistor is disposed in the well region. A well pickup region is disposed in the well region, wherein the well pickup region is at a back side of the semiconductor substrate. A through-via penetrates through the semiconductor substrate, wherein the through-via electrically inter-couples the well pickup region and the source/drain region. | 03-12-2015 |