Patent application number | Description | Published |
20110145485 | METHOD FOR MANAGING ADDRESS MAPPING TABLE AND A MEMORY DEVICE USING THE METHOD - An address mapping table includes arrays each being allocated to a logical address and in which a physical address mapping the logical address is stored. In the case where the physical address mapped to the logical address is changed, a value of a difference between a pre-changed physical address and a physical address to be changed is stored in the address mapping table. When the logical address is mapped to the physical address, the mapped physical address is calculated by adding up the logical address and values stored in the arrays allocated to the logical address. The address mapping table is managed to decrease the number of erase counts of a memory device in which the address mapping table is stored. | 06-16-2011 |
20120327711 | NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM COMPRISING SAME, AND METHOD OF OPERATING SAME - A method of operating a nonvolatile memory device comprises receiving a read command from a memory controller, determining a read mode of the nonvolatile memory device, selecting a read voltage based on the read mode, and performing a read operation on memory cells of a selected page of the nonvolatile memory device using the selected read voltage. | 12-27-2012 |
20120331210 | NON-VOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A nonvolatile memory device comprises a cell array connected to a plurality of bit lines in an all bit line structure, a page buffer circuit connected to the plurality of bit lines, and control logic configured to control the page buffer circuit. The control logic controls the page buffer circuit to sense memory cells corresponding to both even-numbered and odd-numbered columns of a selected page in a first read mode and to sense memory cells corresponding to one of the even-numbered and odd-numbered columns of the selected page in a second read mode. A sensing operation is performed at least twice in the first read mode and once in the second read mode. | 12-27-2012 |
20130021852 | NONVOLATILE MEMORY AND METHOD OF CONTROLLING THEREOF - A memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a memory cell array storing setup data and reference data, and first and second latch units respectively configured to store the setup data and the reference data sensed from the memory cell array upon a power-up of the memory system. The controller is configured to control a sensing operation of the nonvolatile memory. An operating environment of the nonvolatile memory is determined by the setup data stored in the first latch unit, and the controller controls the nonvolatile memory to re-store the setup data of the memory cell array in the first latch unit when the reference data of the second latch unit is changed. | 01-24-2013 |
20130117634 | MEMORY SYSTEM AND DATA STORAGE METHOD - A memory system comprises a nonvolatile memory device comprising a memory cell array comprising first and second memory blocks, and a memory controller configured to control the nonvolatile memory device to read data from the first memory block, selectively determine an error correction operation to be performed on the data after it is read from the first memory block based on a state of at least one of the first and second memory blocks, and then store the data in the second memory block. | 05-09-2013 |
20130135934 | NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF - Disclosed is a method of operating a nonvolatile memory device which includes a first memory area and a second memory area, the number of pages being stored in each word line of the first memory area being smaller than the number of pages being stored in each word line of the second memory area, and the first memory area being configured to buffer data to be written in the second memory area. The method includes sensing pages stored in the first memory area to store the sensed pages in a page buffer; receiving an address for storing pages stored in the page buffer in the second memory area; and randomizing the pages stored in the page buffer based on the address. | 05-30-2013 |
20130138870 | MEMORY SYSTEM, DATA STORAGE DEVICE, MEMORY CARD, AND SSD INCLUDING WEAR LEVEL CONTROL LOGIC - Disclosed is a memory system which includes a nonvolatile memory having a user area and a buffer area; and wear level control logic managing a mode change operation in which memory blocks of the user area are partially changed into the buffer area, based on wear level information of the nonvolatile memory. | 05-30-2013 |
20130219109 | MEMORY SYSTEM AND PROGRAM METHOD THEREOF - A memory system includes a nonvolatile memory device having a first data area storing M-bit data using a buffer program operation and a second data area storing N-bit data (N being an integer larger than M) using a main program operation and a memory controller configured to control the nonvolatile memory device. When a main program operation using data stored at the first and second data areas is required, the memory controller calculates values indicating a performance of the required main program operation to be executed according to a plurality of main program manners, selects one of the plurality of main program manners based on the calculated values, and controls the nonvolatile memory device to perform the required main program operation according to the selected main program manner. | 08-22-2013 |
20140153330 | METHOD FOR OPERATING NON-VOLATILE MEMORY DEVICE AND MEMORY CONTROLLER - An operating method for a non-volatile memory device includes applying first and second read voltages to a first word line to perform a read operation; counting first memory cells each having a threshold voltage belonging to a first voltage range between the first read voltage and the second read voltage; applying a third read voltage to the first word line sequentially after applying the second read voltage to count second memory cells each having a second threshold voltage belonging to a voltage range between the second read voltage and the third read voltage; comparing the number of first memory cells counted and the number of second memory cells counted; determining a fourth read voltage based on a result of the comparing; and applying the fourth read voltage to the first word line sequentially after applying the third read voltage. | 06-05-2014 |
20140369124 | MEMORY SYSTEMS INCLUDING NONVOLATILE MEMORY DEVICES AND DYNAMIC ACCESS METHODS THEREOF - A method of operating a memory device includes: determining an erase mode based on a number of erase cycles performed on a memory block and an erase voltage utilized to perform each erase cycle; and setting an erase voltage level for executing an erase operation on the memory block based on the determined erase mode. | 12-18-2014 |