Patent application number | Description | Published |
20080259903 | Error control method, medium access control (MAC) frame designing method, and terminal registration method in wireless communication system, and recording medium - The MAC frame in a wireless communication system includes a terminal ID allocated to each of multiple terminals. At least one connection ID is allocated to each terminal having the terminal ID, and sub-carrier allocation information is allocated to each connection having the connection ID. The sub-carrier allocation information includes a sub-carrier allocation status for each sub-carrier, and the number of allocated information bits for each sub-carrier. The sub-carrier allocation status and the number of allocated information bits for each sub-carrier can be allocated, by sub-carriers, to the sub-carrier allocation information using a same number of bits; or the information on the sub-carrier allocation status is first allocated to the sub-carrier allocation information and the number of allocated information bits for each sub-carrier is allocated. | 10-23-2008 |
20080316967 | Error control method, medium access control (MAC) frame designing method, and terminal registration method in wireless communication system, and recording medium - The MAC frame in a wireless communication system includes a terminal ID allocated to each of multiple terminals. At least one connection ID is allocated to each terminal having the terminal ID, and sub-carrier allocation information is allocated to each connection having the connection ID. The sub-carrier allocation information includes a sub-carrier allocation status for each sub-carrier, and the number of allocated information bits for each sub-carrier. The sub-carrier allocation status and the number of allocated information bits for each sub-carrier can be allocated, by sub-carriers, to the sub-carrier allocation information using a same number of bits; or the information on the sub-carrier allocation status is first allocated to the sub-carrier allocation information and the number of allocated information bits for each sub-carrier is allocated. | 12-25-2008 |
20090010149 | VIRTUAL MULTI-ANTENNA METHOD FOR OFDM SYSTEM AND OFDM-BASED CELLULAR SYSTEM - Provided are a virtual multi-antenna method for an orthogonal frequency division multiplexing (OFDM) system and an OFDM-based cellular system. The virtual multi-antenna method includes grouping sub-carriers in a frequency domain of an OFDM symbol and generating at least one group including G sub-carriers; and regarding the G sub-carriers included in the at least one group as multiple channels used in a multi-antenna technique and virtually applying the multi-antenna technique to the transmission and reception of the OFDM symbol. The virtual multi-antenna method can effectively reduce an interference signal and obtain the effects of a spatial division multiple access (SDMA) technique without physically using multiple antennas. | 01-08-2009 |
20090116425 | ERROR CONTROL METHOD, MEDIUM ACCESS CONTROL (MAC) FRAME DESIGNING METHOD, AND TERMINAL REGISTRATION METHOD IN WIRELESS COMMUNICATION SYSTEM, AND RECORDING MEDIUM - In a method of registering with an access point in a terminal of a wireless communication system, a frame includes a downlink sub-frame including a broadcast interval and a first management connection interval, and an uplink sub-frame including an access interval and a second management connection interval, the broadcast interval being used for transmitting a map message, the method includes: sending a first ranging request message to the access point using the access interval; receiving allocation information of a ranging slot from the access point using the map message; performing ranging through the ranging slot; sending a registration request message to the access point using the second management connection interval; and receiving information on whether to permit the registering from the access point using the first management connection interval. | 05-07-2009 |
20100146610 | NODE AUTHENTICATION AND NODE OPERATION METHODS WITHIN SERVICE AND ACCESS NETWORKS IN NGN ENVIRONMENT - Provided are node authentication and node operation methods within service and access networks for bundle authentication between the service and access networks in a next generation network (NGN). A method of authentication processing of a node (S-CSC-FE/I-CSC-FE (Serving Call Session Control Functional Entity/Interrogating Call Session Control Functional Entity)) within a service network for bundle authentication between service and access networks, the method including: receiving first authentication information about access authentication of a terminal from a first node within the service networks; requesting to receive second authentication information from a second node within the service network based on the first authentication information; and comparing the first authentication information with the second authentication information to authenticate the terminal. | 06-10-2010 |
20110002465 | INTEGRATED HANDOVER AUTHENTICATING METHOD FOR NEXT GENERATION NETWORK (NGN) WITH WIRELESS ACCESS TECHNOLOGIES AND MOBILE IP BASED MOBILITY CONTROL - Integrated handover authentication technology for a next generation network (NGN) environment to which wire-less access technology and mobile IP based mobility control technology are applied is provided. In a method of operating a mobile terminal MN in order to perform the integrated handover authentication in the NGN environment including an access router PAR, a target router NAR, and an authentication(AAA) server. First, a handover authentication key HK | 01-06-2011 |
20120140722 | ERROR CONTROL METHOD, MEDIUM ACCESS CONTROL (MAC) FRAME DESIGNING METHOD, AND TERMINAL REGISTRATION METHOD IN WIRELESS COMMUNICATION SYSTEM, AND RECORDING MEDIUM - The MAC frame in a wireless communication system includes a terminal ID allocated to each of multiple terminals. At least one connection ID is allocated to each terminal having the terminal ID, and sub-carrier allocation information is allocated to each connection having the connection ID. The sub-carrier allocation information includes a sub-carrier allocation status for each sub-carrier, and the number of allocated information bits for each sub-carrier. The sub-carrier allocation status and the number of allocated information bits for each sub-carrier can be allocated, by sub-carriers, to the sub-carrier allocation information using a same number of bits; or the information on the sub-carrier allocation status is first allocated to the sub-carrier allocation information and the number of allocated information bits for each sub-carrier is allocated. | 06-07-2012 |
20140112296 | ADAPTIVE TRANSMISSION DEVICE USING LIMITED FEEDBACK INFORMATION IN A MOBILE COMMUNICATION SYSTEM, AND A METHOD THEREOF - The present invention relates to an adaptive transmitting device using limited feedback information in a mobile communication system, and a method thereof. According to an exemplary embodiment of the present invention, when the base station transmits a pilot signal to the terminal, the terminal generates channel information by using the pilot signal, generates additional channel information from the channel information, and transmits the channel information and the additional channel information to the base station. The base station determines band allocation, power allocation, and modulation methods for each use by using received feedback information, and transmits modulated traffic data to the terminal according to the determined methods. | 04-24-2014 |
20140376508 | ERROR CONTROL METHOD, MEDIUM ACCESS CONTROL (MAC) FRAME DESIGNING METHOD, AND TERMINAL REGISTRATION METHOD IN WIRELESS COMMUNICATION SYSTEM, AND RECORDING MEDIUM - The MAC frame in a wireless communication system includes a terminal ID allocated to each of multiple terminals. At least one connection ID is allocated to each terminal having the terminal ID, and sub-carrier allocation information is allocated to each connection having the connection ID. The sub-carrier allocation information includes a sub-carrier allocation status for each sub-carrier, and the number of allocated information bits for each sub-carrier. The sub-carrier allocation status and the number of allocated information bits for each sub-carrier can be allocated, by sub-carriers, to the sub-carrier allocation information using a same number of bits; or the information on the sub-carrier allocation status is first allocated to the sub-carrier allocation information and the number of allocated information bits for each sub-carrier is allocated. | 12-25-2014 |
Patent application number | Description | Published |
20100117141 | Memory cell transistors having limited charge spreading, non-volatile memory devices including such transistors, and methods of formation thereof - In one aspect, a transistor comprises: a substrate body; a tunnel oxide layer on the body; a charge trapping layer on the tunnel oxide layer; a blocking layer on the charge trapping layer; a control gate on the blocking layer, the control gate having first and second sidewalls, the first and second sidewalls being spaced apart from each other by a first distance; and charge confinement features on the body, the charge confinement features being spaced apart from each other by a second distance that is greater than or substantially equal to the first distance, the charge confinement features suppressing or preventing migration of charge present in the charge trapping layer. | 05-13-2010 |
20100210116 | METHODS OF FORMING VAPOR THIN FILMS AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES INCLUDING THE SAME - A method of forming a vapor thin film is provided, which includes loading a substrate into a chamber, adsorbing a source gas on the substrate by supplying the source gas into the chamber, and forming the thin film on the substrate by supplying a reaction gas into the chamber, wherein the forming of the thin film on the substrate is proceeded under an electric field formed in one direction on the substrate by applying a bias to the substrate. | 08-19-2010 |
20100240207 | METHODS OF MANUFACTURING CHARGE TRAP TYPE MEMORY DEVICES - Manufacturing of a charge trap type memory device can include forming a tunnel insulating layer on a substrate. A charge-trapping layer can be formed on the tunnel insulating layer. A blocking layer can be formed on the charge-trapping layer. Gate electrodes can be formed on the blocking layer and divided by a trench. A portion of the charge-trapping layer aligned with the trench may be converted into a charge-blocking pattern with a vertical side profile by an anisotropic oxidation process. | 09-23-2010 |
20100248465 | METHODS OF FABRICATING SILICON OXIDE LAYERS USING INORGANIC SILICON PRECURSORS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES INCLUDING THE SAME - Methods of fabricating a silicon oxide layer using an inorganic silicon precursor and methods of fabricating a semiconductor device using the same are provided. The methods of fabricating a semiconductor device include forming a tunnel insulating layer and a charge storage layer on a substrate; forming a dielectric layer structure on the charge storage layer using an atomic layer deposition (ALD) method, the dielectric layer structure including a first dielectric layer formed of silicon oxide, a second dielectric layer on the first dielectric layer formed of a material different from the material forming the first dielectric layer, and a third dielectric layer formed of the silicon oxide on the second dielectric layer; and forming a control gate on the dielectric layer structure. The first and third dielectric layers formed of the silicon oxide are formed using a first gas including an inorganic silicon precursor, a second gas including hydrogen gas or a hydrogen component, and a third gas including an oxide gas. | 09-30-2010 |
20120001264 | ETCHANTS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES USING THE SAME - Provided according to embodiments of the present invention are methods of fabricating semiconductor devices using an etchant. In some embodiments, the etchant may be highly selective and may act to reduce interference between wordlines in the semiconductor device. In some embodiments of the invention, provided are methods of fabricating a semiconductor device that include forming a plurality of gate patterns on a substrate; forming first insulation layers between the gate patterns; wet-etching the first insulation layers to form first insulation layer residues; and forming air gaps between the plurality of gate patterns. Related etchant solutions and semiconductor devices are also provided. | 01-05-2012 |
20120064707 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A semiconductor device includes gate structures including a tunnel insulating layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially disposed on a substrate. The control gate includes an impurity doped polysilicon layer pattern and a metal layer pattern. The gate structures are spaced apart from each other on the substrate. A capping layer pattern is disposed on a sidewall portion of the metal layer pattern and includes a metal oxide. An insulating layer covers the gate structures and the capping layer pattern. The insulating layer is formed on the substrate and includes an air-gap therein. | 03-15-2012 |
20120104482 | SEMICONDUCTOR DEVICES HAVING A CONTROL GATE ELECTRODE INCLUDING A METAL LAYER FILLING A GAP BETWEEN ADJACENT FLOATING GATES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a device isolation layer defining a plurality of active regions of a semiconductor substrate, floating gates and a control gate electrode in which the lowermost part of the electrode is constituted by a metal layer. The control gate electrode crosses over the active regions. The floating gates are disposed between the control gate electrode and the active regions. The tops of the floating gates are disposed at a level above the level of the top of the device isolation layer such that a gap is defined between adjacent ones of the floating gates. A region of the gap is filled with the metal layer of the control gate electrode. | 05-03-2012 |
20120276702 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a channel region, forming a buffer layer on the channel region, and heat-treating the channel region by using a gas containing halogen atoms. | 11-01-2012 |
20130032878 | SEMICONDUCTOR DEVICE - According to example embodiments, a semiconductor device includes horizontal patterns stacked on a substrate. The horizontal patterns define an opening through the horizontal patterns. A first core pattern is in the opening. A second core pattern is in the opening on the first core pattern. A first active pattern is between the first core pattern and the horizontal patterns. A second active pattern containing a first element is between the second core pattern and the horizontal patterns. The second active pattern contains the first element at a higher concentration than a concentration of the first element in the second core pattern. | 02-07-2013 |
20130270631 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a channel region extending in a vertical direction perpendicular to a substrate and having a nitrogen concentration distribution, a plurality of gate electrodes arranged on a side wall of the channel region and separated from each other in a vertical direction, and a gate dielectric layer disposed between the channel region and the gate electrodes. The nitrogen concentration distribution has a first concentration near an interface between the channel region and the gate dielectric layer. | 10-17-2013 |
20130270643 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A three-dimensional (3D) semiconductor memory device includes an electrode separation pattern, a stack structure, a data storage layer, and a channel structure. The electrode separation pattern is disposed on a substrate. A stack structure is disposed on a sidewall of the electrode separation pattern. The stack structure includes a corrugated sidewall opposite to the sidewall of the electrode separation pattern. The sidewall of the electrode separation pattern is vertical to the substrate. A data storage layer is disposed on the corrugated sidewall. A channel structure is disposed on the charge storage layer. | 10-17-2013 |
20140024189 | Vertical Memory Devices and Methods of Manufacturing the Same - Methods of fabricating vertical memory devices are provided including forming a plurality of alternating insulating layers and sacrificial layers on a substrate; patterning and etching the plurality of insulating layer and sacrificial layers to define an opening that exposes at least a portion of a surface of the substrate; forming a charge trapping pattern and a tunnel insulating pattern on a side wall of the opening; forming a channel layer on the tunnel insulating layer on the sidewall of the opening, the channel layer including N-type impurity doped polysilicon; forming a buried insulating pattern on the channel layer in the opening; and forming a blocking dielectric layer and a control gate on the charge trapping pattern of one side wall of the channel layer. | 01-23-2014 |
20140054676 | VERTICAL TYPE SEMICONDUCTOR DEVICES INCLUDING OXIDATION TARGET LAYERS - A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps. | 02-27-2014 |
20140239375 | MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A vertical memory device includes a channel array, a charge storage layer structure, multiple gate electrodes and a dummy pattern array. The channel array includes multiple channels, each of which is formed on a first region of a substrate and is formed to extend in a first direction substantially perpendicular to a top surface of the substrate. The charge storage layer structure includes a tunnel insulation layer pattern, a charge storage layer pattern and a blocking layer pattern, which are sequentially formed on a sidewall of each channel in the second direction substantially parallel to the top surface of the substrate. The gate electrodes arranged on a sidewall of the charge storage layer structure and spaced apart from each other in the first direction. The dummy pattern array includes multiple dummy patterns, each of which is formed on a second region adjacent the first region of the substrate and is formed to extend in the first direction. | 08-28-2014 |
20140322832 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes: forming a preliminary stack structure, the preliminary stack structure defining a through hole; forming a protection layer and a dielectric layer in the through hole; forming a channel pattern, a gapfill pattern, and a contact pattern in the through hole; forming an offset oxide on the preliminary stack structure; measuring thickness data of the offset oxide; and scanning the offset oxide using a reactive gas cluster ion beam. The scanning the offset oxide includes setting a scan speed based on the measured thickness data of the offset oxide, and forming a gas cluster. | 10-30-2014 |