Patent application number | Description | Published |
20090168580 | FUSE MONITORING CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE - A fuse monitoring circuit for a semiconductor device includes a repair fuse unit including a number of fuses to which a repair address is programmed, and configured to output fuse state signals corresponding to the connection states of the respective fuses in response to a fuse initialization signal. A serial fuse monitoring unit is configured to output a fuse state monitoring signal corresponding to each fuse state signal selected by an applied address in response to a serial monitoring test mode signal. Also, a parallel fuse monitoring unit is configured to output a repair monitoring signal by comparing an applied address and the repair address in response to a parallel monitoring test mode signal. An output unit is configured to output the fuse state monitoring signal and the repair monitoring signal to an output pad in response to an output control signal. | 07-02-2009 |
20100103748 | CLOCK PATH CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME - A clock path control circuit includes a clock control signal generating unit configured to generate a clock control signal having an activation period corresponding to an activation period of a data input buffer; and a clock transfer unit configured to provide a clock signal to a write clock path in response to the clock control signal during the activation period of the clock control signal. | 04-29-2010 |
20100110811 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first data input circuit configured to align data inputted to a first data pad in parallel for transferring the aligned data to a first global bus and for transferring the aligned data to a second global bus in a test mode; and a second data input circuit configured to align data inputted to a second data pad in parallel for transferring the aligned data to the second global bus and to not receive data in the test mode. | 05-06-2010 |
20100142308 | PIPE LATCH CIRCUIT AND DRIVING METHOD THEREOF - A pipe latch circuit includes a pipe input unit configured to receive a plurality of data in an order corresponding to address information, a control signal generator configured to generate first and second control clock signals by using the address information, where the first and second control clock signals correspond to a synchronization clock signal, and a pipe output unit configured to synchronize an output signal of the pipe input unit with the first and second control clock signals and output the synchronized output signal. | 06-10-2010 |
20100250994 | DATA PATTERN DETECTING CIRCUIT AND OUTPUT DRIVER INCLUDING THE SAME - Disclosed is an output driver capable of solving problems that occur when outputting the same data successively by using a data pattern detecting circuit. The data pattern detecting circuit includes a first data storage unit configured to receive data of a first line and store the received data until a next data is inputted through the first line, a second data storage unit configured to receive data of a second line and store the received data until a next data is inputted through the second line, and a detection signal output unit configured to activate a pattern detection signal when data stored in the first data storage unit and data stored in the second data storage unit have the same logic level. | 09-30-2010 |
20110062391 | MANUFACTURING METHOD OF COMPOUND SEMICONDUCTOR MATERIAL, AND COMPOUND SEMICONDUCTOR MATERIAL USING THE SAME - The present invention provides a manufacturing method of group III-V compound semiconductor material including a step of making a metal oxide nano-particle of a group III metal element reductively react to a group-V-element-containing compound in order to manufacture compound semiconductor material comprised of two or more element compounds. | 03-17-2011 |
20110158033 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a burst pulse generation unit configured to store a burst length information signal in response to a first control signal and output the burst length information signal as a burst pulse signal in response to a second control signal; and an input/output(I/O) control unit configured to generate the first and second control signals in response to a read pulse signal and a latency signal, respectively. | 06-30-2011 |
20120221750 | DATA TRANSFER CIRCUIT AND MEMORY DEVICE HAVING THE SAME - A data transfer circuit includes a serial-to-parallel converter configured to convert multi-bit data inputted in series into parallel data by controlling the number of bits of the parallel data and a conversion timing based on an operation mode, and a data transmission unit configured to transfer the parallel data to a first data path or a second data path based on the operation mode. | 08-30-2012 |
20120254528 | MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A memory device includes a first bank group, a second bank group, where the first and second bank groups are each configured to output multi-bit data in parallel in response to a read command, a data transferor configured to receive the multi-bit data outputted in parallel from the first bank group or the second bank group and output the multi-bit data at a time interval corresponding to an operation mode, first global data buses configured to transfer the multi-bit data outputted from the first bank group to the data transferor, second global data buses configured to transfer the multi-bit data outputted from the second bank group to the data transferor, and a parallel-to-serial converter configured to convert the multi-bit data outputted from the data transferor into serial data according to the operation mode. | 10-04-2012 |
20120269016 | LATENCY CONTROL CIRCUIT, LATENCY CONTROL METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A latency control circuit of a semiconductor device includes a phase detection unit configured to generate phase information regarding a phase difference between an external clock and an internal clock, a delay amount deciding unit configured to decide a latency delay amount based on path information of an input signal, a latency value of the input signal, and the phase information, and a latency delay unit configured to generate a latency signal by delaying the input signal according to the latency delay amount and the phase information to produce a delayed input signal and by synchronizing the delayed input signal with the internal clock. | 10-25-2012 |
20130216017 | COUNTING CIRCUIT, DELAY VALUE QUANTIZATION CIRCUIT, AND LATENCY CONTROL CIRCUIT - A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio. | 08-22-2013 |
20150043702 | COUNTING CIRCUIT, DELAY VALUE QUANTIZATION CIRCUIT, AND LATENCY CONTROL CIRCUIT - A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio. | 02-12-2015 |