Patent application number | Description | Published |
20090168580 | FUSE MONITORING CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE - A fuse monitoring circuit for a semiconductor device includes a repair fuse unit including a number of fuses to which a repair address is programmed, and configured to output fuse state signals corresponding to the connection states of the respective fuses in response to a fuse initialization signal. A serial fuse monitoring unit is configured to output a fuse state monitoring signal corresponding to each fuse state signal selected by an applied address in response to a serial monitoring test mode signal. Also, a parallel fuse monitoring unit is configured to output a repair monitoring signal by comparing an applied address and the repair address in response to a parallel monitoring test mode signal. An output unit is configured to output the fuse state monitoring signal and the repair monitoring signal to an output pad in response to an output control signal. | 07-02-2009 |
20100103748 | CLOCK PATH CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME - A clock path control circuit includes a clock control signal generating unit configured to generate a clock control signal having an activation period corresponding to an activation period of a data input buffer; and a clock transfer unit configured to provide a clock signal to a write clock path in response to the clock control signal during the activation period of the clock control signal. | 04-29-2010 |
20100110811 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first data input circuit configured to align data inputted to a first data pad in parallel for transferring the aligned data to a first global bus and for transferring the aligned data to a second global bus in a test mode; and a second data input circuit configured to align data inputted to a second data pad in parallel for transferring the aligned data to the second global bus and to not receive data in the test mode. | 05-06-2010 |
20100142308 | PIPE LATCH CIRCUIT AND DRIVING METHOD THEREOF - A pipe latch circuit includes a pipe input unit configured to receive a plurality of data in an order corresponding to address information, a control signal generator configured to generate first and second control clock signals by using the address information, where the first and second control clock signals correspond to a synchronization clock signal, and a pipe output unit configured to synchronize an output signal of the pipe input unit with the first and second control clock signals and output the synchronized output signal. | 06-10-2010 |
20100250994 | DATA PATTERN DETECTING CIRCUIT AND OUTPUT DRIVER INCLUDING THE SAME - Disclosed is an output driver capable of solving problems that occur when outputting the same data successively by using a data pattern detecting circuit. The data pattern detecting circuit includes a first data storage unit configured to receive data of a first line and store the received data until a next data is inputted through the first line, a second data storage unit configured to receive data of a second line and store the received data until a next data is inputted through the second line, and a detection signal output unit configured to activate a pattern detection signal when data stored in the first data storage unit and data stored in the second data storage unit have the same logic level. | 09-30-2010 |
20110062391 | MANUFACTURING METHOD OF COMPOUND SEMICONDUCTOR MATERIAL, AND COMPOUND SEMICONDUCTOR MATERIAL USING THE SAME - The present invention provides a manufacturing method of group III-V compound semiconductor material including a step of making a metal oxide nano-particle of a group III metal element reductively react to a group-V-element-containing compound in order to manufacture compound semiconductor material comprised of two or more element compounds. | 03-17-2011 |
20110158033 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a burst pulse generation unit configured to store a burst length information signal in response to a first control signal and output the burst length information signal as a burst pulse signal in response to a second control signal; and an input/output(I/O) control unit configured to generate the first and second control signals in response to a read pulse signal and a latency signal, respectively. | 06-30-2011 |
20120221750 | DATA TRANSFER CIRCUIT AND MEMORY DEVICE HAVING THE SAME - A data transfer circuit includes a serial-to-parallel converter configured to convert multi-bit data inputted in series into parallel data by controlling the number of bits of the parallel data and a conversion timing based on an operation mode, and a data transmission unit configured to transfer the parallel data to a first data path or a second data path based on the operation mode. | 08-30-2012 |
20120254528 | MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A memory device includes a first bank group, a second bank group, where the first and second bank groups are each configured to output multi-bit data in parallel in response to a read command, a data transferor configured to receive the multi-bit data outputted in parallel from the first bank group or the second bank group and output the multi-bit data at a time interval corresponding to an operation mode, first global data buses configured to transfer the multi-bit data outputted from the first bank group to the data transferor, second global data buses configured to transfer the multi-bit data outputted from the second bank group to the data transferor, and a parallel-to-serial converter configured to convert the multi-bit data outputted from the data transferor into serial data according to the operation mode. | 10-04-2012 |
20120269016 | LATENCY CONTROL CIRCUIT, LATENCY CONTROL METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A latency control circuit of a semiconductor device includes a phase detection unit configured to generate phase information regarding a phase difference between an external clock and an internal clock, a delay amount deciding unit configured to decide a latency delay amount based on path information of an input signal, a latency value of the input signal, and the phase information, and a latency delay unit configured to generate a latency signal by delaying the input signal according to the latency delay amount and the phase information to produce a delayed input signal and by synchronizing the delayed input signal with the internal clock. | 10-25-2012 |
20130216017 | COUNTING CIRCUIT, DELAY VALUE QUANTIZATION CIRCUIT, AND LATENCY CONTROL CIRCUIT - A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio. | 08-22-2013 |
20150043702 | COUNTING CIRCUIT, DELAY VALUE QUANTIZATION CIRCUIT, AND LATENCY CONTROL CIRCUIT - A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio. | 02-12-2015 |
20150155861 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes a first pad suitable for receiving a first clock that is inputted from an exterior, a second pad suitable for receiving a second clock that is inputted from the exterior, a differential clock recognition unit suitable for recognizing between the first clock and the second clock as a positive clock of differential clocks and recognizing the other as a negative clock of the differential clocks in response to a mirror function signal which represents whether a mirror function is enabled or not, an output unit suitable for outputting an internal signal as an output signal in response to the differential clocks and controlling an output moment of the output signal in response to the mirror function signal and an output moment control signal, and a third pad suitable for supplying the output signal to the exterior. | 06-04-2015 |
20150162071 | ADDRESS STORAGE CIRCUIT AND MEMORY AND MEMORY SYSTEM INCLUDING THE SAME - A memory including a plurality of word lines to which one or more memory cells are coupled, an address storage unit suitable for storing an input address corresponding to a first external signal that is inputted at a random time, and a control unit suitable for activating a word line corresponding to the input address of the plurality of word lines in response to an active command and refreshing one or more target word lines selected using an address stored in the address storage unit when performing a refresh operation. | 06-11-2015 |
20150256183 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes a dock division block suitable for dividing a frequency of a source clock and generating first and second internal clocks; a strobe division block suitable for dividing a frequency of a strobe signal, and generating first and second internal strobe signals; and a phase difference detection block suitable for generating and alternately outputting first and second detection information as a detection result information. | 09-10-2015 |
20150256184 | SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME, AND METHOD OF OPERATING THE SAME - A semiconductor apparatus includes a clock division block suitable for generating a first internal dock and a second internal clock having a first phase difference at which active sections of the first internal clock and the second internal clock overlap with each other by dividing a phase of a source clock at a predetermined rate, and a phase detection block suitable for outputting detection result information generated by combining a result obtained by detecting a phase of the first internal clock at a predetermined edge of a strobe signal and a result obtained by detecting a phase of the second internal clock at the predetermined edge of the strobe signal. | 09-10-2015 |
20150294701 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first buffer suitable for receiving and buffering data, a second buffer suitable for receiving and buffering a data strobe signal, a strobe line suitable for transferring the data strobe signal; a plurality of data transfer lines suitable for transferring data inputted at corresponding turns among data inputted in series through the first buffer, a latch signal generation block suitable for generating a plurality of latch signals which are sequentially activated, based on the data strobe signal transferred through the strobe line, a data latch block suitable for latching and aligning in parallel the data inputted in series through the first buffer, based on the latch signals, and a data transfer block suitable for transferring the data latched by the data latch block to the plurality of data transfer lines, according to a correspondence relationship determined based on an input start signal that is activated at a time when the input of data corresponding to the data input command is started. | 10-15-2015 |
Patent application number | Description | Published |
20100051898 | QUANTUM DOT-WAVELENGTH CONVERTER, MANUFACTURING METHOD OF THE SAME AND LIGHT EMITTING DEVICE INCLUDING THE SAME - There is provided a quantum dot wavelength converter including a quantum dot, which is optically stable without any change in an emission wavelength and improved in emission capability. The quantum dot wavelength converter includes: a wavelength converting part including a quantum dot wavelength-converting excitation light and generating a wavelength-converted light and a dispersive medium dispersing the quantum dot; and a sealer sealing the wavelength converting part. | 03-04-2010 |
20100053930 | WAVELENGTH CONVERSION PLATE AND LIGHT EMITTING DEVICE USING THE SAME - Provided is a wavelength conversion plate having excellent luminous efficiency of a wavelength-converted light. The wavelength conversion plate includes a dielectric layer with nano pattern, a metal layer formed inside the nano pattern, and a wavelength conversion layer formed on the metal layer and having quantum dot or phosphor which wavelength-converts an excitation light to generate a wavelength-converted light. | 03-04-2010 |
20100084629 | QUANTUM DOT-METAL OXIDE COMPLEX, METHOD OF PREPARING THE SAME, AND LIGHT-EMITTING DEVICE COMPRISING THE SAME - Provided is a quantum dot-metal oxide complex including a quantum dot and a metal oxide forming a 3-dimensional network with the quantum dot. In the quantum dot-metal oxide complex, the quantum dot is optically stable without a change in emission wavelength band and its light-emitting performance is enhanced. | 04-08-2010 |
20110240960 | QUANTUM DOT-WAVELENGTH CONVERTER, MANUFACTURING METHOD OF THE SAME AND LIGHT EMITTING DEVICE INCLUDING THE SAME - There is provided a quantum dot wavelength converter including a quantum dot, which is optically stable without any change in an emission wavelength and improved in emission capability. The quantum dot wavelength converter includes: a wavelength converting part including a quantum dot wavelength-converting excitation light and generating a wavelength-converted light and a dispersive medium dispersing the quantum dot; and a sealer sealing the wavelength converting part. | 10-06-2011 |
20120193604 | WAVELENGTH CONVERSION PLATE AND LIGHT EMITTING DEVICE USING THE SAME - Provided is a wavelength conversion plate having excellent luminous efficiency of a wavelength-converted light. The wavelength conversion plate includes a dielectric layer with nano pattern, a metal layer formed inside the nano pattern, and a wavelength conversion layer formed on the metal layer and having quantum dot or phosphor which wavelength-converts an excitation light to generate a wavelength-converted light. | 08-02-2012 |
20140230992 | QUANTUM DOT-WAVELENGTH CONVERTER, MANUFACTURING METHOD OF THE SAME AND LIGHT EMITTING DEVICE INCLUDING THE SAME - There is provided a quantum dot wavelength converter including a quantum dot, which is optically stable without any change in an emission wavelength and improved in emission capability. The quantum dot wavelength converter includes: a wavelength converting part including a quantum dot wavelength-converting excitation light and generating a wavelength-converted light and a dispersive medium dispersing the quantum dot; and a sealer sealing the wavelength converting part. | 08-21-2014 |
Patent application number | Description | Published |
20110195010 | Method of forming InP quantum dot and InP quantum dot formed by the same - Disclosed herein is a method of forming a spherical InP quantum dot, including: providing a compound containing indium (In); dissolving the compound in alcohol to form a solution; and introducing a compound containing phosphorus (P) into the solution. The method is advantageous because a spherical InP quantum dot can be formed, the method is environment-friendly because alcohol is used as a solvent, because InP quantum dots can be produced in large quantities because the InP quantum dots can be formed while putting all reactants into a reactor and slowly heating the reactants, and because the desired InP quantum dots can be easily recovered by decreasing the temperature of a reactor or by performing centrifugal separation at low speed. | 08-11-2011 |
20110298729 | TOUCH PANEL AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a touch panel including: a transparent substrate | 12-08-2011 |
20110298747 | CAPACITIVE TOUCH PANEL - Disclosed herein is a capacitive touch panel | 12-08-2011 |
20110308929 | TOUCH PANEL AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a touch panel | 12-22-2011 |
20120007825 | OPERATING MODULE OF HYBRID TOUCH PANEL AND METHOD OF OPERATING THE SAME - Disclosed herein is an operating module of a hybrid touch panel, including: an input unit | 01-12-2012 |
20120013549 | TOUCH SCREEN - Disclosed herein is a touch screen, including: a pair of base members that are spaced apart from each other by a spacer having an opening formed inside thereof and have resistive films formed on the opposite surfaces thereof; grooves that are each formed in outer regions of the resistive films formed on the pair of base members to intersect with each other and are extended from the upper surfaces of the resistive films to the base members in a thickness direction; and sensing electrodes that are formed in the outer regions of the resistive films to cover the grooves and are filled in the grooves. | 01-19-2012 |
20120032910 | TOUCH PANEL AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a touch panel, including: a transparent substrate; a transparent electrode made of a conductive polymer and formed on one surface of the transparent substrate; an anisotropic conductive adhesion layer formed on an edge of the transparent electrode; and an electrode formed on the anisotropic conductive adhesion layer and electrically connected with the transparent electrode by the anisotropic conductive adhesion layer. The touch panel is advantageous in that the anisotropic conductive adhesion layer is disposed between the transparent electrode and the electrode, so that the chemical reaction between the transparent electrode and the electrode can be prevented, with the result that the resistance between the transparent electrode and the electrode can be maintained constant and the change in physical properties of the transparent electrode can be prevented. | 02-09-2012 |
20120032927 | TOUCH PANEL - Disclosed herein is a touch panel. The touch panel | 02-09-2012 |
20120056843 | RESISTIVE TOUCH PANEL - Disclosed herein is a resistive touch panel, including: a transparent substrate; a transparent electrode formed on the transparent substrate and including a conductive polymer; and a curing agent applied to the transparent electrode, the curing agent undergoing a hydrolysis reaction with the conductive polymer to cure the transparent electrode. The resistive touch panel is advantageous in that, even when a transparent electrode is formed using a conductive polymer having low hardness, the hardness of the transparent electrode is improved by the application of the curing agent, so that it is possible to prevent the contact resistance between the transparent electrodes facing each other from changing in relation to the pressure intensity of input means, thereby improving the touch sensitivity and performance of the resistive touch panel. | 03-08-2012 |
20120056844 | CAPACITIVE TOUCH SCREEN - Disclosed herein is a capacitive touch screen. The capacitive touch screen includes: a base member including an active region through which an image generated in a display passes and an inactive region which extends from the active region and is formed to be stepwise; a plurality of electrode patterns which intersects with the top and the bottom of the base member and are disposed in the active region; electrode wirings which are connected to the electrode patterns disposed in the active region and extend to the inactive region; and a window formed on the top of the base member. | 03-08-2012 |
20120092274 | TOUCH SCREEN - Disclosed herein is a touch screen, including: a first transparent electrode formed on one surface of a first transparent substrate; a second transparent electrode formed on one surface of a second transparent substrate; a first adhesive layer configured to adhere the first transparent substrate and the second transparent substrate to each other; a window plate adhered to the first transparent substrate; and hardness dots formed on one surface of the window plate or the other surface of the first transparent substrate. The present invention has been made in an effort to provide a touch screen which can lower the operational load of a transparent electrode. | 04-19-2012 |
20120098781 | CAPACITIVE TOUCH SCREEN AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a capacitive touch screen and a method for manufacturing the same. The capacitive touch screen includes: a base member on which a plurality of electrode patterns are formed; conductive adhesive members formed at ends of the electrode patterns; a window disposed over the base member and having a plurality of electrode wirings formed in an outer region thereof, the plurality of electrode wirings being opposite to the electrode patterns; and auxiliary electrodes formed at one of the ends of the electrode wirings to conduct the electrode patterns with the electrode wirings by the conductive adhesive members. | 04-26-2012 |
20120118606 | CONDUCTIVE FILM AND MANUFACTURING METHOD THEREOF - Disclosed herein are conductive film including: a base member; N transparent electrodes formed on one surface of the base member, the N transparent electrodes being arranged in a second direction of the base member, while being extended in a first direction of the base member; and electrode wirings each correspondingly connected to one end or both ends of the N transparent electrodes and including wiring portions configured of a plurality of wirings extended in a third direction of the base member and bent and extended in the second direction of the base member and insulating portions having the wiring portions impregnated therein and formed on an upper surface of one side or both sides of the transparent electrode and a manufacturing method thereof. Accordingly, the plurality of wirings are formed in a three-dimensional shape vertically in the insulating portion rather than a plane of the base member, making it possible to reduce the area of a non-display region due to the electrode wirings. | 05-17-2012 |
20120133609 | RESISTIVE TYPE TOUCH PANEL AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a resistive type touch panel according to a preferred embodiment of the present invention. The resistive type touch panel includes a transparent substrate; a transparent electrode formed on one surface of the transparent substrate and made of a conductive polymer; and a plurality of conductive balls formed on the transparent electrode and having conductivity. According to the present invention, the conductive balls are included in the transparent electrode made of the conductive polymer to improve the conductivity of the transparent electrode and the conductive balls are formed on the transparent electrode at a predetermined interval, thereby making it possible to constantly maintain the thickness of the transparent electrode. Further, the conductive balls are formed on the transparent electrode to reduce the contact resistance value generated when the resistive type touch panel is touched, thereby making it possible to improve the reliability of the operation of the touch panel. | 05-31-2012 |
20120194482 | TOUCH PANEL - Disclosed herein is a touch panel | 08-02-2012 |
20120200516 | TOUCH PANEL AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a touch panel and a method for manufacturing the same. A touch panel | 08-09-2012 |
20120206405 | OPERATING MODULE OF DISPLAY DEVICE WITH TOUCH PANEL AND OPERATING METHOD THEREOF - Disclosed herein is an operating module of a display device with a touch panel. The operating module includes a touch input unit for a user to input a value through a touch unit; a pattern input unit to which the same pattern image as patterns of a transparent electrode formed on the touch panel having the touch input unit is input; a control unit coupling each image signal into a single image signal according to an output value having a complementary pattern image value with the pattern image value input to the pattern input unit and an output value according to the input of the touch input unit; and an output unit outputting an image signal by the control unit. | 08-16-2012 |
20130068506 | PLATING SYSTEM AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are a plating pattern and a method of manufacturing the same. The plating pattern includes: a base substrate; a conductive polymer formed on the base substrate and patterned to be selectively deactivated by having a deactivator added thereto; and a plating layer formed on portions of the conductive polymer except for the deactivated portions. | 03-21-2013 |
Patent application number | Description | Published |
20130064020 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a first data input/output line configured to transmit data from a first memory bank; a second data input/output line configured to transmit the data from the first memory bank; a first data output section configured to align and output data transmitted through the first data input/output line based on an input/output mode; and a second data output section configured to align and output either data transmitted through the first input/output line or the second data input/output line based on the input/output mode and an address signal. | 03-14-2013 |
20130265101 | ANTI-FUSE CIRCUIT - An anti-fuse circuit includes: an anti-fuse unit including an anti-fuse capable of being programmed in response to a rupture signal and configured to generate a fuse signal corresponding to a state of the anti-fuse; a dummy fuse unit including a dummy fuse and configured to generate a dummy fuse signal corresponding to a state of the dummy fuse; and a blocking unit configured to output the fuse signal as a fuse output signal in response to a state of the dummy fuse signal. | 10-10-2013 |
20130314149 | ANTI-FUSE CIRCUIT - An anti-fuse circuit includes: a rupture unit including an anti-fuse programmed in response to an input rupture signal during a program mode, and configured to generate an output rupture signal corresponding to a state of the anti-fuse to output the generated output rupture signal to a transmission node, a voltage clamp unit configured to generate a clamp voltage proportional to an external voltage level to generate the clamp voltage having a constant voltage level when the external voltage level rises to a predetermined level or more, and a fuse signal generation unit configured to reset the transmission node to the clamp voltage at the initial stage of the program mode to generate a fuse signal in response to the voltage level of the transmission node during an output mode. | 11-28-2013 |
20130315007 | TEST CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus including a test circuit configured for generating compressed data by comparing and compressing data stored in a plurality of memory cells inside a memory bank during a first test mode, and configured for outputting the compressed data as test data to an input/output pad through one selected global line during the first test mode, and the test circuit is configured for transmitting the compressed data to a plurality of global lines during a second test mode, combining the compressed data loaded in the respective global lines during the second test mode, and outputting the combination result as the test data to the input/output pad during the second test mode. | 11-28-2013 |
20130315023 | COLUMN SELECT SIGNAL GENERATION CIRCUIT - A column select signal generation circuit includes: a first current controller configured to control the level of a pre-column select signal in response to a bank active signal, a driver configured to generate an amplified column select signal in response to the pre-column select signal, and a second current controller configured to generate an output signal of the driver as a column select signal in response to the bank active signal. | 11-28-2013 |
20140043926 | DATA OUTPUT CIRCUIT OF SEMICONDUCTOR DEVICE - A data output circuit of a semiconductor device includes: a pattern data generation unit configured to generate pattern data in response to a bank selection signal, a variable delay unit configured to delay a source signal, which is generated in response to the bank selection signal, by a delay time corresponding to a delay control signal, a pattern control signal generation unit configured to generate a pattern control signal in response to an output signal of the variable delay unit, and a delay time control block configured to generate the delay control signal in response to the phases of the pattern control signal and the pattern data. | 02-13-2014 |
20140177357 | DATA WRITE CIRCUIT OF SEMICONDUCTOR APPARATUS - A data write circuit of a semiconductor apparatus includes a data path configured to receive a pattern signal and generate a first delayed pattern signal; a data strobe signal path configured to receive the pattern signal and generate a second delayed pattern signal; a data latch block configured to latch the first delayed pattern signal in response to the second delayed pattern signal, and output a resultant signal; and a control block configured to generate the pattern signal, and vary a delay time of the data path according to a result of comparing phases of a latched signal of the data latch block and the pattern signal. | 06-26-2014 |
20140184286 | DATA OUTPUT CIRCUIT - A data output circuit according to one embodiment of the present invention includes: a delay control block configured to generate a clock delay signal in response to a power-up signal and a reset signal; a first delay block configured to correct a duty ratio of a rising clock according to the clock delay signal and output the corrected rising clock; and a second delay block configured to correct a duty ratio of a falling clock according to the clock delay signal and output the corrected falling clock. | 07-03-2014 |
20140340968 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a latch unit configured to latch data in response to an input control signal; and a latch control unit configured to determine whether or not any one of first and second memory areas is successively accessed, and adjust timing of the input control signal. | 11-20-2014 |
20140347939 | SEMICONDUCTOR DEVICES INCLUDING PIPE LATCH UNITS AND SYSTEM INCLUDING THE SAME - The semiconductor device includes a pre-signal generator and a data output portion. The pre-signal generator generates a pre-input control signal and a pre-output control signal. The pre-signal generator also generates a pre-latch pulse signal by detecting when the pre-input control signal and the pre-output control signal are generated. The data output portion receives an input control signal, a latch pulse signal, and a first output control signal. The data output portion receives an input clock signal in response to the input control signal and the latch pulse signal to generate a shift clock signal, and the data output portion also shifts the first output control signal in response to the shift clock signal to generate a second output control signal. | 11-27-2014 |
20150124535 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit may include: a memory block partitioned into a first region and a second region; a data latch unit configured to latch data outputted from the memory block in response to a control signal; and a control circuit configured to generate a source signal separated into an odd order and an even order in response to a column access signal consecutively inputted to access the first region or the second region, and to generate the control signal in response to the source signal. | 05-07-2015 |
20150187438 | SEMICONDUCTOR MEMORY APPARATUS AND TEST METHOD USING THE SAME - A semiconductor memory apparatus includes first data outputted from a first data storage region; second data outputted from a second data storage region; a data comparison block configured to perform a comparison to determine whether the first data and the second data are the same, and generate a comparison result signal; a timing control block configured to latch the comparison result signal in response to a clock and a latency signal, and output a comparison signal; and a data output block configured to receive a test signal and invert the first data in response to the comparison signal and output data. | 07-02-2015 |
Patent application number | Description | Published |
20140140151 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a data alignment control signal generation unit configured to output a data alignment control signal by generating a pulse when a tuning mode signal is enabled, and generate the data alignment control signal as a count pulse is inputted after the data alignment control signal generated by the tuning mode signal is outputted; a timing control block configured to determine a delay amount according to delay codes, generate a delay control signal by delaying the data alignment control signal, and output a timing control signal by latching the delay control signal at an enable timing of a data output control signal; a delay time control block configured to generate the delay codes; and a data alignment unit configured to convert parallel data into serial data, and change a data sequence of the serial data in response to the timing control signal. | 05-22-2014 |
20150227417 | SEMICONDUCTOR MEMORY APPARATUS AND OPERATING METHOD THEREOF - A semiconductor memory apparatus may include an error check and correction circuit block configured to receive a plurality of cell data, and output error-checked data and error data discrimination signals after receiving an error check enable signal; and a data bus inversion circuit block configured to receive the plurality of cell data, and output the plurality of cell data by inverting or non-inverting the cell data after receiving a read data bus inversion enable signal, the error check enable signal and the error data discrimination signals. | 08-13-2015 |
20150294699 | SEMICONDUCTOR DEVICES INCLUDING PIPE LATCH UNITS AND SYSTEM INCLUDING THE SAME - The semiconductor device includes a pre-signal generator and a data output portion. The pre-signal generator generates a pre-input control signal and a pre-output control signal. The pre-signal generator also generates a pre-latch pulse signal by detecting when the pre-input control signal and the pre-output control signal are generated. The data output portion receives an input control signal, a latch pulse signal, and a first output control signal. The data output portion receives an input clock signal in response to the input control signal and the latch pulse signal to generate a shift clock signal, and the data output portion also shifts the first output control signal in response to the shift clock signal to generate a second output control signal. | 10-15-2015 |
20150332742 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus may include a data conversion control block configured to control the number of pipe input control signals and the number of pipe output control signals which are enabled, in response to a training control signal. The semiconductor memory apparatus may also include a data conversion block configured to receive parallel data and output serial data, in response to the pipe input control signals and the pipe output control signals. | 11-19-2015 |