Patent application number | Description | Published |
20110276812 | System On Chip, Devices Having The Same, and Method For Power Control of the SOC - Disclosed is an integrated circuit device including a plurality of power domain blocks, which includes a core power domain block. A power control circuit is configured to control power supplied to each of the plurality of power domain blocks independently responsive to control communication from the core power domain block. The power control circuit includes a plurality of power clusters corresponding to the plurality of power domain blocks, respectively. The plurality of power clusters control power supplied to the plurality of power domain blocks, respectively, independently responsive to the control communication from the core power domain block. | 11-10-2011 |
20120072743 | Hierarchical Power Management Circuit, Power Management Method Using the Same, and System on Chip Including the Hierarchical Power Management Circuit - A hierarchical power management circuit includes N power management circuits respectively included in N power domains each including at least one intellectual property (IP), wherein N is a natural number greater than one. The i-th (1 | 03-22-2012 |
20130138848 | ASYNCHRONOUS BRIDGE - An asynchronous bridge includes a transmission unit and a receiving unit. The transmission unit receives a write valid signal and input data from a master circuit, outputs write addresses increment under control of the write valid signal, sequentially stores the input data in memory cells, as directed by write addresses, and then sequentially outputs the stored input data, as directed by read addresses. The receiving unit receives a read ready signal from a slave circuit, determines whether memory cells are valid, based on the write addresses and the read addresses, and then outputs a read valid signal and the input data, based on the determination. | 05-30-2013 |
20130198545 | METHODS OF SPREADING PLURALITY OF INTERRUPTS, INTERRUPT REQUEST SIGNAL SPREADER CIRCUITS, AND SYSTEMS-ON-CHIPS HAVING THE SAME - In a method of power control for a system-on-chip, output of at least one of a first wakeup request signal and a second wakeup request signal is controlled such that a time interval between the output of the first wakeup request signal and the output of the second wakeup request signal is greater than or equal to a time interval threshold. The first wakeup request signal and the second wakeup request signal are one of concurrent and consecutive wakeup request signals. | 08-01-2013 |
20140075224 | METHOD OF PERFORMING DYNAMIC VOLTAGE AND FREQUENCY SCALING OPERATION, APPLICATION PROCESSOR PERFORMING METHOD, AND MOBILE DEVICE COMPRISING APPLICATION PROCESSOR - A method of performing a dynamic voltage and frequency scaling operation comprises controlling a clock management unit (CMU) to predict an operating state of a central processing unit (CPU) and to provide operating frequency information to a power management integrated circuit (PMIC) based on the predicted operating state of the CPU, the operating frequency information indicating a change of an operating frequency of an application processor, and controlling the PMIC to change an operating voltage of the application processor based on the operating frequency information provided from the clock management unit. | 03-13-2014 |
20140266401 | DATA-RETAINED POWER-GATING CIRCUIT AND DEVICES INCLUDING THE SAME - A power-gating circuit and devices including the same are provided. The power-gating circuit includes a flip-flop configured to receive a first power supply voltage and a gated clock signal to operate and a switch circuit connected between a first power supply voltage source configured to supply the first power supply voltage and a second power supply voltage source configured to supply a second power supply voltage. The switch circuit includes a first switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to a clock enable signal and a second switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to the first power supply voltage. | 09-18-2014 |
20160026498 | POWER MANAGEMENT SYSTEM, SYSTEM-ON-CHIP INCLUDING THE SAME AND MOBILE DEVICE INCLUDING THE SAME - A power management system controlling power for a plurality of functional blocks included in a system-on-chip includes a plurality of programmable nano controllers, an instruction memory and a signal map memory. The instruction memory is shared by the nano controllers and stores a plurality of instructions that are used by the nano controllers. The signal map memory is shared by the nano controllers and stores a plurality of signals that are provided to the functional blocks and are controlled by the nano controllers. A first nano controller among the plurality of nano controllers is programmed as a central sequencer. Second through n-th nano controllers among the plurality of nano controllers are programmed as first sub-sequencers that are dependent on the first nano controller. | 01-28-2016 |
20160062437 | APPLICATION PROCESSOR FOR ADJUSTING CLOCK SIGNAL USING HARDWARE POWER MANAGEMENT UNIT AND DEVICES INCLUDING THE SAME - An application processor includes a central processing unit (CPU), intellectual properties (IPs), a hardware power management unit (PMU) configured to determine whether the application processor is in system idle based on a first idle signal output from the CPU and output control signals as a result of the determination, and a clock signal supply control circuit configured to change an output signal supplied to the CPU and the IPs from clock signals to an oscillation clock signal, based on the control signals. The oscillation clock signal has a frequency lower than that of the clock signals. | 03-03-2016 |
20160094337 | SYSTEM-ON-CHIP TO SUPPORT FULL HANDSHAKE AND MOBILE DEVICE HAVING THE SAME - A system-on-chip (SoC) comprises a clock management unit (CMU) including a first clock generator and a second clock generator, the first and second clock generators being configured to generate clock signals. The SoC comprises at least one logic block configured to request the clock signals from the CMU according to a full handshake method and receive the clock signals from the CMU in response to the request. The first clock generator and the second clock generator are configured to communicate according to the full handshake method. | 03-31-2016 |