Patent application number | Description | Published |
20120249229 | SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor integrated circuit includes a plurality of semiconductor chips respectively selected in response to a plurality of chip selection signals, and a chip selection signal generator configured to generate the chip selection signals in response to one first control signal for deciding whether to drive the semiconductor chips and at least one second control signal for selecting at least one semiconductor chip from among the semiconductor chips. | 10-04-2012 |
20130162287 | SEMICONDUCTOR PACKAGE INCLUDING MULTIPLE CHIPS AND MEMORY SYSTEM HAVING THE SAME - A package includes a master chip including a storage circuit configured to store an impedance setting of the master chip and an impedance setting of a slave chip, and a termination circuit for an impedance matching with an outside of the package, and the slave chip connected to the master chip, wherein if a termination operation for the slave chip is activated, the termination circuit of the master chip performs an impedance matching operation using the impedance setting for the slave chip. | 06-27-2013 |
20130321074 | SEMICONDUCTOR INTEGRAGED CIRCUIT HAVING COMPATIBLE MODE SELECTION CIRCUIT - A semiconductor integrated circuit includes a semiconductor chip or a plurality of semiconductor chip stacked therein, wherein each semiconductor chip includes, a compatible mode selection unit configured to select a chip allocation signal allocated to the semiconductor chip, among a plurality of chip allocation signals inputted through a plurality of pads, in response to a stack package information, and an internal circuit configured to perform a given operation in response to the chip allocation signal selected by the compatible mode selection unit. | 12-05-2013 |
20140064013 | INTEGRATED CIRCUIT - An integrated circuit includes a plurality of mode register set (MRS) setting blocks configured to generate a plurality of additive latency (AL) codes in response to an MRS signal, and a decoding unit configured to decoding the plurality of AL codes in response to a stack information signal to generate a plurality of AL setting signals. | 03-06-2014 |
20140306748 | MULTI-CHIP PACKAGE - A multi-chip package having a plurality of slice chips coupled through a through-via, at least one slice chip may include an input unit suitable for receiving a slice activation signal, and outputting the slice activation signal to the through-via in response to a slice identification corresponding to the slice chip, a first output unit suitable for outputting the activation signal transferred through the through-via to an internal circuit of the slice chip in response to the corresponding slice identification, and a second output unit suitable for selectively outputting the activation signal transferred through the through-via to the internal circuit of the slice chip in a predetermined activation mode for the multi-chip package. | 10-16-2014 |
20140313845 | SEMICONDUCTOR CHIP, SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SEMICONDUCTOR CHIP, SEMICONDUCTOR SYSTEM INCLUDING THE SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DRIVING THE SEMICONDUCTOR SYSTEM - A semiconductor system including a semiconductor integrated circuit or a semiconductor chip, and a method of driving the semiconductor system are described. The semiconductor integrated circuit includes a plurality of semiconductor chips, at least one first chip through via suitable for penetrating through the plurality of semiconductor chips and interfacing a source ID code between the plurality of semiconductor chips, a plurality of second chip through vias suitable for penetrating through the plurality of semiconductor chips and interfacing a plurality of chip selection signals between the plurality of semiconductor chips, wherein the semiconductor chip uses one of chip selection signals as an internal chip selection signal in response to a chip ID code by selecting one of a unique ID code for the semiconductor chip and an alternative ID code for a preset semiconductor chip when the semiconductor chip fails. | 10-23-2014 |
20150098281 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME - A semiconductor chip includes an internal voltage generation circuit suitable for generating an internal voltage having a predetermined level, a target internal circuit suitable for performing a predetermined operation using the internal voltage, and a control circuit suitable for checking operating speed of the target internal circuit based on an operation result signal generated from the target internal circuit, and generating the control signal based on the checked operating speed, wherein a voltage level of the internal voltage for target internal circuit is controlled based on the control signal. | 04-09-2015 |
20150098293 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a plurality of semiconductor chips. Each of the plurality of semiconductor chips includes a chip selection unit suitable for generating an internal chip selection signal in response to one or more selective chip selection signals and transferring the selective chip selection signals to an adjacent semiconductor chip of the plurality of semiconductor chips, a selective setting unit suitable for generating a selective internal signal, selectively activated in each semiconductor chip, in response to the internal chip selection signal and an external setting signal, and a common setting unit suitable for generating a common internal signal, activated in common in the plurality of semiconductor chips, in response to the setting signal and an external common chip selection signal. | 04-09-2015 |