Patent application number | Description | Published |
20120126857 | COMMAND BUFFER CIRCUIT OF SEMICONDUCTOR APPARATUS - A command buffer circuit of a semiconductor apparatus includes a first buffer configured to receive a first command signal and generate a first command control signal, a second buffer configured to receive a second command signal and generate a second command control signal, a second block configured to select and output the first command control signal or the second command control signal in response to a rank control signal, and a control signal generation block configured to generate the rank control signal in response to a single rank signal and a chip select signal. | 05-24-2012 |
20120243350 | ADDRESS DELAY CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - An address delay circuit of a semiconductor memory apparatus includes a first group control pulse generation unit configured to generate a first control pulse after input of a first group column address strobe pulse and passage of a time corresponding to a first set multiple of one cycle of a clock, a second group control pulse generation unit configured to generate a second control pulse after input of a second group column strobe address pulse and passage of a time corresponding to a second set multiple of the one cycle of the clock, a first address storage unit configured to receive and store a first group external address in response to the first control pulse, and output a first group internal address, and a second address storage unit configured to receive and store a second group external address in response to the second control pulse, and output a second group internal address. | 09-27-2012 |
20120249222 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a plurality of dies, wherein each of the dies is configured to enable a power circuit provided therein according to a power control signal, in a state in which the die was determined to be a good die or a fail die. | 10-04-2012 |
20130151176 | SEMICONDUCTOR APPARATUS AND CHIP SELECTING METHOD THEREOF - A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating code of different values; an individual chip activation block configured to enable an individual chip activation signal among a plurality of individual chip activation signals, which corresponds to individual chip designating code, when the individual chip designating code matches the individual chip control code; and a control block configured to set the individual chip control code or output chip selection address as the individual chip control code in response to chip selection fuse signals and test fuse signals. | 06-13-2013 |
20140003171 | SEMICONDUCTOR MEMORY APPARATUS | 01-02-2014 |
Patent application number | Description | Published |
20110085405 | SEMICONDUCTOR MEMORY DEVICE HAVING ADVANCED TAG BLOCK - A semiconductor memory device includes a row decoding block for decoding an inputted address to thereby generate a logical unit cell block address and a decoded word line address; a tag block for converting the logical unit cell block address into a physical unit cell block address; a decoded address latching block for latching the decoded word line address to thereby output the decoded word line address as a word line activation signal in response to the physical unit cell block; and a cell area for outputting a data, which is stored therein, in response to the word line activation signal. | 04-14-2011 |
20110169542 | DELAY CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR DELAYING - A delay circuit of a semiconductor memory apparatus includes a decoding unit configured to decode a plurality of test signals and enable one of a plurality of control signals; a bias voltage generation unit configured to generate a first bias voltage and a second bias voltage depending upon the control signal enabled among the plurality of control signals; and a delay unit configured to determine a delay time depending upon levels of the first and second bias voltages, delay an input signal by the determined delay time, and output a resultant signal as an output signal. | 07-14-2011 |
20110204950 | DELAY CIRCUIT AND METHOD FOR DELAYING SIGNAL - A delay circuit includes: a delay unit configured to receive a clock signal, delay an input signal sequentially by a predetermined time interval, and output a plurality of first delayed signals; and an option unit configured to select one of the plurality of first delayed signals based on one or more select signals, and output a second delayed signal. | 08-25-2011 |
20110210780 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a plurality of chips configured to receive an external voltage. Each one of the chips detects a signal delay characteristic of the one of the chips to generate an internal voltage having a level corresponding to the signal delay characteristic. | 09-01-2011 |
20110211405 | EXTERNAL SIGNAL INPUT CIRCUIT OF SEMICONDUCTOR MEMORY - In one embodiment, an external signal input circuit of a semiconductor memory may include: an input block configured to receive a plurality of external signals and to generate a plurality of internal signals; and a control block configured to output one or more internal signals of the plurality of internal signals that correspond to a rank configuration of the semiconductor memory and to block output of one or more internal signals of the plurality of internal signals that do not correspond to the rank configuration. | 09-01-2011 |
20110211406 | ADDRESS DELAY CIRCUIT - An address delay circuit of a semiconductor memory apparatus includes a control clock delay block configured to receive a clock as a first control clock in response to a first input control signal, and output external address as the first delayed address; a control clock input selecting delay block configured to receive the clock as a second control clock in response to a second input control signal, select whether to receive the external address or the first delayed address in response to the first input control signal, and output the selected address as the second delayed address; and a control clock input/output selecting delay block configured to receive the clock, select whether to receive the external address or the second delayed address in response to the second input control signal, and output the selected address as an internal address. | 09-01-2011 |
20110241763 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating codes which have different code values or at least two of which have the same code value, in response to a plurality of chip fuse signals; and an individual chip activation block configured to compare the plurality of individual chip designating codes with chip selection address in response to the plurality of chip fuse signals, and enable one of a plurality of individual chip activation signals based on a result of the comparison. | 10-06-2011 |
20110242911 | COLUMN COMMAND BUFFER AND LATENCY CIRCUIT INCLUDING THE SAME - A column command buffer includes a variable delay section configured to determine a delay time based on a frequency of a clock, and output a column command after delaying it by the delay time; and a buffering section configured to receive an output of the variable delay section and generate internal column commands. | 10-06-2011 |
20110242928 | ADDRESS DELAY CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - An address delay circuit of a semiconductor memory apparatus includes a control pulse generation unit configured to generate a control pulse following a time corresponding to a predetermined multiple of cycles of a clock after a read write pulse is inputted; and a delay unit configured to output internal addresses when the control pulse is inputted, wherein the internal addresses are input as external addresses. | 10-06-2011 |
20110246104 | SEMICONDUCTOR APPARATUS AND CHIP SELECTING METHOD THEREOF - A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating code of different values; an individual chip activation block configured to enable an individual chip activation signal among a plurality of individual chip activation signals, which corresponds to individual chip designating code, when the individual chip designating code matches the individual chip control code; and a control block configured to set the individual chip control code or output chip selection address as the individual chip control code in response to chip selection fuse signals and test fuse signals. | 10-06-2011 |
20110286287 | SEMICONDUCTOR MEMORY DEVICE WITH OPTIMUM REFRESH CYCLE ACCORDING TO TEMPERATURE VARIATION - Methods for generating a refresh signal in a semiconductor device and methods for performing a refresh operation in a semiconductor memory device are disclosed. A method for generating a refresh signal includes measuring a temperature of the semiconductor memory device, generating a temperature controlled voltage based on the measured temperature, generating an N-bit digital signal based on the temperature controlled voltage, and generating a refresh signal whose frequency is determined by the N-bit digital signal. The generation of the temperature controlled voltage includes generating a first current that is increased when the measured temperature is decreased and is decreased with the measured temperature is increased, and generating the temperature controlled voltage. | 11-24-2011 |
20120127809 | PRECHARGE SIGNAL GENERATION CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A precharge signal generation circuit of a semiconductor memory apparatus may comprise a read/write precharge command generation section configured to delay a precharge command by a first delay time set in response to a control signal to generate one of a read precharge command and a write precharge command; and a read/write bank precharge address generation section configured to delay a bank column address strobe signal by a second delay time set in response to the precharge command delayed in the read/write precharge command generation section, and generate one of a read bank precharge address and a write bank precharge address. | 05-24-2012 |
20120224441 | SEMICONDUCTOR MEMORY APPARATUS - Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, a semiconductor memory apparatus may include a page size control unit configured to generate first and second block enable signals having a level corresponding to one of a plurality of row selection signals or one of a plurality of column selection signals based on a page size control signal; a first page block configured to enable a plurality of first memory cells selected by the plurality of row selection signals in response to the first block enable signal, and activate data access of memory cells selected among the plurality of selected first memory cells by the plurality of column selection signals and the option column selection signal; and a second page block configured to enable a plurality of second memory cells selected by the plurality of row selection signals in response to the second block enable signal, and activate data access of memory cells selected among the plurality of selected second memory cells by the plurality of column selection signals and the option column selection signal. | 09-06-2012 |
Patent application number | Description | Published |
20130019109 | METHOD AND APPARATUS FOR USING NON-VOLATILE STORAGE DEVICEAANM KANG; Bo-GyeongAACI Suwon-siAACO KRAAGP KANG; Bo-Gyeong Suwon-si KRAANM Kwon; Moon-SangAACI SeoulAACO KRAAGP Kwon; Moon-Sang Seoul KRAANM Lee; Byung-RaeAACI SeoulAACO KRAAGP Lee; Byung-Rae Seoul KRAANM Lee; Jae-BumAACI Yongin-siAACO KRAAGP Lee; Jae-Bum Yongin-si KR - A method and apparatus for using a non-volatile storage device includes reading device identification information from the non-volatile storage device, application identification information corresponding to a content application related to a type of content to be protected or utilized among a plurality of content applications is acquired, usage identification information is generated using the device identification information and the application identification information, and protecting or utilizing content using the usage identification information. | 01-17-2013 |
20130151761 | DATA STORAGE DEVICE STORING PARTITIONED FILE BETWEEN DIFFERENT STORAGE MEDIUMS AND DATA MANAGEMENT METHOD - A data management method for a data storage device includes receiving a write request; partitioning the file into first and second portions; encrypting the first portion, and storing the encrypted first portion in a first storage medium and the second portion in a second storage medium. | 06-13-2013 |
20130156195 | METHOD OF OBTAINING A MAIN KEY FROM A MEMORY DEVICE, METHOD OF GENERATING AUTHENTICATION INFORMATION FOR A MEMORY DEVICE, AN EXTERNAL DEVICE AND SYSTEM ICLUDING THE EXTERNAL DEVICE - In one embodiment, the method includes obtaining, at the external device, an encrypted main key and an encrypted first decryption key from the memory device. The encrypted first decryption key is an encrypted version of a first decryption key. The encrypted main key is an encrypted version of the main key. The external device is unable to read the main key from the memory device. The method further includes decrypting, at the external device, the encrypted first decryption key using a second decryption key to obtain the first decryption key; and decrypting, at the external device, the encrypted main key of the memory device using the first decryption key to obtain the main key. | 06-20-2013 |
20130159655 | STORAGE SYSTEM FOR SUPPORTING USE OF MULTIPLE KEYS - A storage system that enables the use of a plurality of keys respectively stored in a plurality of storage units of a storage device is provided. The storage system includes a storage device including a first storage unit and a second storage unit that are recognized as a single storage device, wherein the first storage unit is configured to store a first key, the second storage unit is configured to store a second key different from the first key, and a controller is configured to transmit to the storage device one of a first key-read control signal that includes information about the first storage unit and a second key-read control signal that includes information about the second storage unit and receive the first key and the second key as identification information of the storage device in response to the first key-read control signal and the second key-read control signal, respectively. | 06-20-2013 |
20130159733 | MEMORY DEVICE WHICH PROTECTS SECURE DATA, METHOD OF OPERATING THE MEMORY DEVICE, AND METHOD OF GENERATING AUTHENTICATION INFORMATION - In one embodiment, the memory device includes a first memory area and a second memory area. The first memory area stores secure data. The first memory area is inaccessible by an external device. The second memory area is configured to store encrypted secure data. The second memory area is accessible by the external device, and the encrypted secure data is an encrypted version of the secure data in the first memory area. | 06-20-2013 |
Patent application number | Description | Published |
20100263655 | BURNER AND COOKING DEVICE - A cooking device is provided. The cooking device includes a cavity and a burner. The cavity provides a cooking chamber. The burner is in the cavity and heats food in the cooking chamber. The burner includes a supply part and a combustion part. The supply part supplies a gaseous fuel mixed with air. The combustion part burns the mixed gaseous fuel and has an open curve shape. | 10-21-2010 |
20100263656 | BURNER AND COOKING DEVICE - A cooking device is provided. The cooking device includes a cavity and a burner. The cavity provides a cooking chamber. The burner is at the cooking chamber in the cavity and heats food in the cooking chamber. The burner includes a supply part and a combustion unit. A gaseous fuel mixed with air flows in the supply part. The combustion unit is connected to the supply part to receive the mixed gaseous fuel and to burn the received mixed gaseous fuel flowing within the combustion unit. The combustion unit has a single loop shape. | 10-21-2010 |
20100263657 | GAS COOKER - A gas cooker is provided. First and second front burners are disposed on the left and the right of a front upper surface of a top plate at an interval in a row. Lower ignition parts of the first and second front burners are disposed at a distance from an imaginary straight line passing through central points of the first and second front burners in parallel with the front end of the top plate, toward a front end of the top plate. | 10-21-2010 |
20100263658 | GAS COOKER - Provided is a gas cooker. When foods are cooked using a top burner, inclinations of main flame holes defined in the top burner are different according to positions of the main flame holes to prevent textile disposed adjacent to a front end of a top plate from burning. Thus, a user may further safely cook the foods. | 10-21-2010 |
20110011389 | TOP-BURNER AND COOKER COMPRISING THE SAME - The present invention relates to a top burner and a cooker including the top burner. The present invention includes: an outer burner installed on a top surface of a top plate, and provided with a plurality of flame holes to form flames through combusting gas mixture at a perimeter thereof; an inner burner installed on a top surface of the outer burner, and provided with a plurality of flame holes to form flames through combusting gas mixture at a perimeter thereof disposed inward to the perimeter of the outer burner; a plurality of first mixing tubes supplying gas mixture mixed with air inside the outer burner; a second mixing tube supplying gas mixture mixed with air inside the inner burner; and a passage formed through the outer tube, and in which air supplied to combust gas mixture at the flame holes of the inner burner flows. Thus, according to the present invention, the advantages of heating food more efficiently while reducing incomplete combustion of gas mixture can be realized. | 01-20-2011 |
20110120444 | TOP-BURNER AND COOKER COMPRISING THE SAME - A top burner and a cooker having the top burner are provided. A flame transfer slit for guiding the flame formed by the combustion of the mixed gas at an outer burner to an inner burner. A shielding member is provided to shield the flame transfer slit. Therefore, the object to be heated is uniformly heated and the flame transfer from the outer burner to the inner burner can be effectively realized. | 05-26-2011 |
Patent application number | Description | Published |
20090002754 | IMAGE FORMING APPARATUS MANAGEMENT SERVER, SERVICE CONTINUITY SCORE (SCS) CALCULATING METHOD OF MANAGEMENT SERVER, AND IMAGE FORMING APPARATUS MANAGEMENT SYSTEM - An image forming apparatus management server, a Service Continuity Score (SCS) calculating method of the management server, and an image forming apparatus management system. A setup manager sets a priority with respect to items required to calculate an SCS indicative of a normal operation time of an image forming apparatus, an incident manager registers and manages an incident related to the image forming apparatus, and an SCS manager calculates the SCS using the registered incident and the priority set for the items. | 01-01-2009 |
20100006851 | Thin film transistor and method of manufacturing the same - A thin film transistor comprises a substrate; a semiconductor layer disposed on the substrate, the semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region; a gate insulating layer disposed on the semiconductor layer and on the substrate; a gate electrode disposed on the insulating layer over the channel region; an passivation layer disposed on the gate electrode and the gate insulating layer; a source electrode disposed in contact with upper, lower and side surfaces of the source region via a first contact hole through passivation layer, the gate insulating layer and the semiconductor layer; and a drain electrode disposed in contact with upper, lower and side surfaces of the drain region via a second contact hole through the passivation layer, the gate insulating layer and the semiconductor layer. | 01-14-2010 |
20100006852 | Thin film transistor and method of fabricating the same - A thin film transistor includes a substrate; a semiconductor layer disposed on the substrate, the semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region; a gate insulating layer disposed on the semiconductor layer and on the substrate; and a gate electrode disposed on the insulating layer over the channel region, wherein the semiconductor layer includes tapered edge portions with a taper angle defined between the tapered edge portions and a surface of the substrate is less than about 30 degrees. | 01-14-2010 |
20110129968 | THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A thin film transistor comprises a substrate; a semiconductor layer disposed on the substrate, the semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region; a gate insulating layer disposed on the semiconductor layer and on the substrate; a gate electrode disposed on the insulating layer over the channel region; an passivation layer disposed on the gate electrode and the gate insulating layer; a source electrode disposed in contact with upper, lower and side surfaces of the source region via a first contact hole through passivation layer, the gate insulating layer and the semiconductor layer; and a drain electrode disposed in contact with upper, lower and side surfaces of the drain region via a second contact hole through the passivation layer, the gate insulating layer and the semiconductor layer. | 06-02-2011 |
20110198604 | FILM TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating a thin film transistor and a thin film transistor includes a polycrystalline silicon layer formed by irradiating an amorphous silicon layer with a laser beam through an organic layer formed on the amorphous silicon layer and removing the organic layer. | 08-18-2011 |
Patent application number | Description | Published |
20130144023 | ACRYLIC COPOLYMER WITH HIGH HEAT RESISTANCE AND HIGH STRENGTH, AND OPTICAL FILM COMPRISING THE SAME - The present invention relates to an acrylic copolymer having high heat resistance and high strength, and an optical film comprising the same, and more particularly, to an acrylic copolymer for optical films in which alkyl (meth)acrylate monomers; (meth)acrylate monomers comprising aromatic rings and/or aliphatic rings; and (meth)acrylamide monomers are included and polymerized. An acrylic copolymer according to the present invention is excellent in heat resistance while maintaining transparency. Further, an optical film comprising a compound resin including the acrylic copolymer has superior transparency and heat resistance and is excellent in formability, adhesion, retardation properties, and durability. | 06-06-2013 |
20130150546 | HIGHLY HEAT RESISTANT AND HIGHLY STRONG ACRYLIC COPOLYMER, A RESIN COMPOSITION COMPRISING THE SAME AND AN OPTICAL FILM AND AN IPS MODE LIQUID CRYSTAL DISPLAY DEVICE COMPRISING THE SAME - Provided is an acrylic copolymer comprising; an alkyl (meth)acrylate monomer; a monomer comprising a cyclic pendant structure; and a tert-butyl (meth)acrylate monomer and/or (meth)acrylamide monomer. Also provided is a resin composition comprising the same and an optical film and an IPS mode liquid crystal display device using the same. | 06-13-2013 |
20130190451 | RESIN COMPOSITION FOR OPTICAL FILM, AND POLARIZER PROTECTIVE FILM AND LIQUID CRYSTAL DISPLAY INCLUDING THE SAME - Provided are a resin composition including an acryl-based copolymer resin including an alkyl(meth)acrylate-based monomer and an imide-based monomer, additionally copolymerizable with a styrene-based monomer, and a polycarbonate-based resin having a melt index (MI) of 30 g/10 min or more under conditions of a load of 1.2 kg and a temperature of 300° C., a polarizer protective film including the resin composition, and a liquid crystal display including the polarizer protective film. The polarizer protective film according to the present invention has excellent heat resistance, transparency, and optical properties. | 07-25-2013 |
20130314785 | RESIN COMPOSITION AND OPTICAL FILM FORMED BY USING THE SAME - Provided are a resin composition and an optical film formed by using the same, and more particularly, a resin composition including 85 to 95 parts by weight of a matrix copolymer resin including an alkyl(meth)acrylate-based unit, an acryl-based unit containing a benzene ring, and a (meth)acrylic acid unit, and 5 to 15 parts by weight of a polymer resin having a molecular weight range of 150,000 to 1,000,000 and an optical film formed by using the composition. A resin composition according to the present invention may provide a protective film for a polarizing plate having excellent heat resistance and toughness as well as excellent optical properties, and thus, an optical film formed by using the resin composition of the present invention may be used in information electronic devices such as display devices for various applications. | 11-28-2013 |
20140000801 | METHOD OF PREPARING RESIN COMPOSITION FOR OPTICAL FILM BY USING CONTINUOUS BULK POLYMERIZATION AND METHODS OF PREPARING OPTICAL FILM AND POLARIZING PLATE USING THE RESIN COMPOSITION | 01-02-2014 |
20140015152 | METHOD FOR PREPARING ACRYLIC COPOLYMER RESIN FOR OPTICAL FILM AND METHOD FOR FABRICATING OPTICAL FILM USING THE SAME - There is provided a method for preparing an acrylic copolymer resin for an optical film includes: suspension-polymerizing an acrylic monomer containing a benzene ring, an alkyl(meth)acrylate monomer, and a (meth)acrylic acid monomer to prepare a copolymer; and thermally treating the copolymer at a temperature ranging from 240° C. to 300° C. As the method for preparing an acrylic copolymer of the present invention, a resin having an effectively lowered CTE can be manufactured by inducing the formation of a glutaric anhydride structure by using suspension polymerization that facilitates adjustment of the molecular weight of a resin. | 01-16-2014 |
20140036363 | RESIN COMPOSITION FOR OPTICAL FILM AND OPTICAL FILM USING THE SAME - Provided are a resin composition for an optical film including an alkyl(meth)acrylate unit, a benzyl(meth)acrylate unit, a (meth)acrylic acid unit, and a unit expressed by Chemical Formula I, an optical film, a polarizing plate, and an image display device using the resin composition. | 02-06-2014 |