Patent application number | Description | Published |
20100012808 | FLEXURE MOUNT FOR AN OPTICAL ASSEMBLY - A flexure mount for economically producing pure translational motion with no arcuate or error motion in the vertical direction utilizing alignment pins and parts reducing structures including monolithic springs. A low profile embodiment utilizes a compound monolithic spring. The flexure mount may be used to translate a mirror or retroreflector in a purely linear direction of precisely controlled and known distance, useful in myriad interferometer applications including spectroscopy. | 01-21-2010 |
20100033728 | MONOLITHIC INTERFEROMETER WITH OPTICS OF DIFFERENT MATERIAL - A monolithic frame for optics used in interferometers where the material of the monolithic frame may have a substantially different coefficient of thermal expansion from the beamsplitter and compensator without warping, bending or distorting the optics. This is accomplished through providing a securing apparatus holding the optics in place while isolating the expansion thereof from the expansion of the frame. Stability in optical alignment is therefore achieved without requiring a single material or materials of essentially identical coefficients of thermal expansion. The present invention provides stability in situations where it is not possible to utilize a single material for every component of the interferometer. | 02-11-2010 |
20110273778 | OPTICAL ASSEMBLY, METHOD FOR ASSEMBLING AN OPTICAL ASSEMBLY, SYSTEM FOR SECURING OPTICAL ELEMENTS OF AN OPTICAL ASSEMBLY AND A SPRING FOR SECURING OPTICAL ELEMENTS OF AN OPTICAL ASSEMBLY - A monolithic frame for optics used in interferometers where the material of the monolithic frame may have a substantially different coefficient of thermal expansion from the beamsplitter and compensator without warping, bending or distorting the optics. This is accomplished through providing a securing apparatus holding the optics in place while isolating the expansion thereof from the expansion of the frame. Stability in optical alignment is therefore achieved without requiring a single material or materials of essentially identical coefficients of thermal expansion. The present invention provides stability in situations where it is not possible to utilize a single material for every component of the interferometer. | 11-10-2011 |
20120091310 | FLEXURE MOUNT FOR AN OPTICAL ASSEMBLY - A flexure mount for economically producing pure translational motion with no arcuate or error motion in the vertical direction utilizing alignment pins and parts reducing structures including monolithic springs. A low profile embodiment utilizes a compound monolithic spring. The flexure mount may be used to translate a mirror or retroreflector in a purely linear direction of precisely controlled and known distance, useful in myriad interferometer applications including spectroscopy. | 04-19-2012 |
20120113522 | OPTICAL ASSEMBLY, METHOD FOR ASSEMBLING AN OPTICAL ASSEMBLY, SYSTEM FOR SECURING OPTICAL ELEMENTS OF AN OPTICAL ASSEMBLY AND A SPRING FOR SECURING OPTICAL ELEMENTS OF AN OPTICAL ASSEMBLY - A monolithic frame for optics used in interferometers where the material of the monolithic frame may have a substantially different coefficient of thermal expansion from the beamsplitter and compensator without warping, bending or distorting the optics. This is accomplished through providing a securing apparatus holding the optics in place while isolating the expansion thereof from the expansion of the frame. Stability in optical alignment is therefore achieved without requiring a single material or materials of essentially identical coefficients of thermal expansion. The present invention provides stability in situations where it is not possible to utilize a single material for every component of the interferometer. | 05-10-2012 |
20130135026 | QUASI-TRANSLATOR, FOURIER MODULATOR, FOURIER SPECTROMETER, MOTION CONTROL SYSTEM AND METHODS FOR CONTROLLING SAME, AND SIGNAL PROCESSOR CIRCUIT - A quasi-translator for economically producing pure, smooth translational motion with broad arcuate or error-free motion regardless of orientation, which is useful in numerous interferometer applications including spectroscopy, a Fourier modulator and a Fourier spectrometer are provided. The quasi-translator utilizes a support, an arm including a driving magnet on a first end and a driven element on a second end, an axis for rotation of the arm, a bearing system that controls the rotation of the arm about the axis, a drive coil and a drive amplifier to drive the arm in the arcuate motion. The quasi-translator may be employed in a Fourier modulator to change the optical path difference of the interferometer/quasi-translator at a substantially constant rate of change. The quasi-translator and/or Fourier modulator may be used in a Fourier spectrometer to create an optical spectrum from a light beam and/or electrical signal created from the light beam. | 05-30-2013 |
20130135622 | QUASI-TRANSLATOR, FOURIER MODULATOR, FOURIER SPECTROMETER, MOTION CONTROL SYSTEM AND METHODS FOR CONTROLLING SAME, AND SIGNAL PROCESSOR CIRCUIT - A quasi-translator for economically producing pure, smooth translational motion with broad arcuate or error-free motion regardless of orientation, which is useful in numerous interferometer applications including spectroscopy, a Fourier modulator and a Fourier spectrometer are provided. The quasi-translator utilizes a support, an arm including a driving magnet on a first end and a driven element on a second end, an axis for rotation of the arm, a bearing system that controls the rotation of the arm about the axis, a drive coil and a drive amplifier to drive the arm in the arcuate motion. The quasi-translator may be employed in a Fourier modulator to change the optical path difference of the interferometer/quasi-translator at a substantially constant rate of change. The quasi-translator and/or Fourier modulator may be used in a Fourier spectrometer to create an optical spectrum from a light beam and/or electrical signal created from the light beam. | 05-30-2013 |
20130138226 | QUASI-TRANSLATOR, FOURIER MODULATOR, FOURIER SPECTROMETER, MOTION CONTROL SYSTEM AND METHODS FOR CONTROLLING SAME, AND SIGNAL PROCESSOR CIRCUIT - A quasi-translator for economically producing pure, smooth translational motion with broad arcuate or error-free motion regardless of orientation, which is useful in numerous interferometer applications including spectroscopy, a Fourier modulator and a Fourier spectrometer are provided. The quasi-translator utilizes a support, an arm including a driving magnet on a first end and a driven element on a second end, an axis for rotation of the arm, a bearing system that controls the rotation of the arm about the axis, a drive coil and a drive amplifier to drive the arm in the arcuate motion. The quasi-translator may be employed in a Fourier modulator to change the optical path difference of the interferometer/quasi-translator at a substantially constant rate of change. The quasi-translator and/or Fourier modulator may be used in a Fourier spectrometer to create an optical spectrum from a light beam and/or electrical signal created from the light beam. | 05-30-2013 |
20140029009 | INTERFEROMETER, OPTICAL ASSEMBLY AND METHOD OF MOUNTING SAME - A frame for optics used in interferometers that may include different materials having substantially similar, identical, or as close as practicable coefficients of thermal expansion from the material(s) used to make the beamsplitter and/or compensator without warping, bending, tilting or distorting the optics. The beamsplitter and/or compensator are mounted onto the frame of the interferometer using a three-point method of mounting, preferably using three pins for each component. Preferably, the pins are made of the same material as the beamsplitter and compensator, and all three components are made of Potassium Bromide (“KBr”) or Calcium Fluoride (“CaF | 01-30-2014 |
20140029010 | INTERFEROMETER, OPTICAL ASSEMBLY AND METHOD OF MOUNTING SAME - A frame for optics used in interferometers that may include different materials having substantially similar, identical, or as close as practicable coefficients of thermal expansion from the material(s) used to make the beamsplitter and/or compensator without warping, bending, tilting or distorting the optics. The beamsplitter and/or compensator are mounted onto the frame of the interferometer using a three-point method of mounting, preferably using three pins for each component. Preferably, the pins are made of the same material as the beamsplitter and compensator, and all three components are made of Potassium Bromide (“KBr”) or Calcium Fluoride (“CaF | 01-30-2014 |
Patent application number | Description | Published |
20090089602 | METHOD AND SYSTEM OF PEAK POWER ENFORCEMENT VIA AUTONOMOUS TOKEN-BASED CONTROL AND MANAGEMENT - A method of power management of a system of connected components includes initializing a token allocation map across the connected components, wherein each component is assigned a power budget as determined by a number of allocated tokens in the token allocation map, monitoring utilization sensor inputs and command state vector inputs, determining, at first periodic time intervals, a current performance level, a current power consumption level and an assigned power budget for the system based on the utilization sensor inputs and the command state vector inputs, and determining, at second periodic time intervals, a token re-allocation map based on the current performance level, the current power consumption level and the assigned power budget for the system, according to a re-assigned power budget of at least one of the connected components, while enforcing a power consumption limit based on a total number of allocated tokens in the system. | 04-02-2009 |
20090198970 | METHOD AND STRUCTURE FOR ASYNCHRONOUS SKIP-AHEAD IN SYNCHRONOUS PIPELINES - An electronic apparatus includes a plurality of stages serially interconnected as a pipeline to perform sequential processings on input operands. A shortening circuit associated with at least one stage of the pipeline recognizes when one or more of input operands for the stage has been predetermined as appropriate for shortening and execute the shortening when appropriate. | 08-06-2009 |
20150076908 | EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any circuits to a common voltage source. A powered off circuit is disconnected from the common voltage source. A first capacitor and a second capacitor are configured to supply wakeup electrical charge to a given circuit of the circuits. The first capacitor and the second capacitor are connectable to the given circuit and the powered off circuit. A controller is configured to controllably connect the first capacitor and/or the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, when the powered off circuit was previously connected to the first capacitor and/or the second capacitor. | 03-19-2015 |
20150077170 | EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any circuits to a common voltage source. A powered off circuit is disconnected from the common voltage source. A first capacitor and a second capacitor are configured to supply wakeup electrical charge to a given circuit of the circuits. The first capacitor and the second capacitor are connectable to the given circuit and the powered off circuit. A controller is configured to controllably connect the first capacitor and/or the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, when the powered off circuit was previously connected to the first capacitor and/or the second capacitor. | 03-19-2015 |
20150081123 | PREDICTIVELY TURNING OFF A CHARGE PUMP SUPPLYING VOLTAGE FOR OVERDRIVING GATES OF THE POWER SWITCH HEADER IN A MICROPROCESSOR WITH POWER GATING - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect a circuit to a common voltage source. The circuit is powered off circuit when disconnected. A multiplexer selectably connects a charge pump or common voltage source to a gate terminal of the power header switch. The charge pump provides a higher voltage to the gate terminal than the common voltage source. A controller is configured to control a selection of the multiplexer to the charge pump and the common voltage source. The controller is configured to disconnect the charge pump from the gate terminal and connect the common voltage source to the gate terminal of the power header switch in response to conditions: a prediction of a demand core power-up request, an increase in a gate leakage current, and/or a reduction in temperature of the powered off circuit. | 03-19-2015 |
20150081125 | PREDICTIVELY TURNING OFF A CHARGE PUMP SUPPLYING VOLTAGE FOR OVERDRIVING GATES OF THE POWER SWITCH HEADER IN A MICROPROCESSOR WITH POWER GATING - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect a circuit to a common voltage source. The circuit is powered off circuit when disconnected. A multiplexer selectably connects a charge pump or common voltage source to a gate terminal of the power header switch. The charge pump provides a higher voltage to the gate terminal than the common voltage source. A controller is configured to control a selection of the multiplexer to the charge pump and the common voltage source. The controller is configured to disconnect the charge pump from the gate terminal and connect the common voltage source to the gate terminal of the power header switch in response to conditions: a prediction of a demand core power-up request, an increase in a gate leakage current, and/or a reduction in temperature of the powered off circuit. | 03-19-2015 |
20150082065 | ACCELERATING MICROPROCESSOR CORE WAKE UP VIA CHARGE FROM CAPACITANCE TANK WITHOUT INTRODUCING NOISE ON POWER GRID OF RUNNING MICROPROCESSOR CORES - A mechanism is provided for an integrated circuit with power gating. A power switch is configured to connect and disconnect circuits to a common voltage source. A capacitor tank is configured to supply wakeup charge to a given circuit. A controllable element is connected to the given circuit and to the capacitor tank. The controllable element is configured to controllably connect and disconnect the capacitor tank to the given circuit in order to supply the wakeup charge to the given circuit. The controllable element is configured to, responsive to the power switch disconnecting the given circuit from the common voltage source and to the given circuit being turned on to wakeup, supply the wakeup charge to the given circuit being turned on by transferring the wakeup charge from the capacitor tank to the given circuit. This reduces the electrical charge transferred from the circuits connected to the common voltage source. | 03-19-2015 |
20150082066 | ACCELERATING THE MICROPROCESSOR CORE WAKEUP BY PREDICTIVELY EXECUTING A SUBSET OF THE POWER-UP SEQUENCE - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any one of multiple circuits to a common voltage source, where a powered off circuit is disconnected from the common voltage source. A power-up sequencer includes an initial stages power-up component and a final stages power-up component. The final stages power-up component is configured to execute final stages of a power-up process for the powered off circuit, and the initial stages power-up component is configured to execute initial stages of the power-up process for the powered off circuit. The initial stages power-up component is activated in response to a predictive power-up request. | 03-19-2015 |
20150082069 | ACCELERATING MICROPROCESSOR CORE WAKE UP VIA CHARGE FROM CAPACITANCE TANK WITHOUT INTRODUCING NOISE ON POWER GRID OF RUNNING MICROPROCESSOR CORES - A mechanism is provided for an integrated circuit with power gating. A power switch is configured to connect and disconnect circuits to a common voltage source. A capacitor tank is configured to supply wakeup charge to a given circuit. A controllable element is connected to the given circuit and to the capacitor tank. The controllable element is configured to controllably connect and disconnect the capacitor tank to the given circuit in order to supply the wakeup charge to the given circuit. The controllable element is configured to, responsive to the power switch disconnecting the given circuit from the common voltage source and to the given circuit being turned on to wakeup, supply the wakeup charge to the given circuit being turned on by transferring the wakeup charge from the capacitor tank to the given circuit. This reduces the electrical charge transferred from the circuits connected to the common voltage source. | 03-19-2015 |
20150082070 | ACCELERATING THE MICROPROCESSOR CORE WAKEUP BY PREDICTIVELY EXECUTING A SUBSET OF THE POWER-UP SEQUENCE - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any one of multiple circuits to a common voltage source, where a powered off circuit is disconnected from the common voltage source. A power-up sequencer includes an initial stages power-up component and a final stages power-up component. The final stages power-up component is configured to execute final stages of a power-up process for the powered off circuit, and the initial stages power-up component is configured to execute initial stages of the power-up process for the powered off circuit. The initial stages power-up component is activated in response to a predictive power-up request. | 03-19-2015 |
20150162898 | EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any circuits to a common voltage source. A powered off circuit is disconnected from the common voltage source. A first capacitor and a second capacitor are configured to supply wakeup electrical charge to a given circuit of the circuits. The first capacitor and the second capacitor are connectable to the given circuit and the powered off circuit. A controller is configured to controllably connect the first capacitor and/or the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, when the powered off circuit was previously connected to the first capacitor and/or the second capacitor. | 06-11-2015 |
20150162899 | EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any circuits to a common voltage source. A powered off circuit is disconnected from the common voltage source. A first capacitor and a second capacitor are configured to supply wakeup electrical charge to a given circuit of the circuits. The first capacitor and the second capacitor are connectable to the given circuit and the powered off circuit. A controller is configured to controllably connect the first capacitor and/or the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, when the powered off circuit was previously connected to the first capacitor and/or the second capacitor. | 06-11-2015 |
20150162903 | EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any circuits to a common voltage source. A powered off circuit is disconnected from the common voltage source. A first capacitor and a second capacitor are configured to supply wakeup electrical charge to a given circuit of the circuits. The first capacitor and the second capacitor are connectable to the given circuit and the powered off circuit. A controller is configured to controllably connect the first capacitor and/or the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, when the powered off circuit was previously connected to the first capacitor and/or the second capacitor. | 06-11-2015 |
20150162904 | EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING - A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any circuits to a common voltage source. A powered off circuit is disconnected from the common voltage source. A first capacitor and a second capacitor are configured to supply wakeup electrical charge to a given circuit of the circuits. The first capacitor and the second capacitor are connectable to the given circuit and the powered off circuit. A controller is configured to controllably connect the first capacitor and/or the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, when the powered off circuit was previously connected to the first capacitor and/or the second capacitor. | 06-11-2015 |
Patent application number | Description | Published |
20140040592 | ACTIVE BUFFERED MEMORY - According to one embodiment of the present invention, a method for operating a memory device that includes memory and a processing element includes receiving, in the processing element, a command from a requestor, loading, in the processing element, a program based on the command, the program comprising a load instruction loaded from a first memory location in the memory, and performing, by the processing element, the program, the performing including loading data in the processing element from a second memory location in the memory. The method also includes generating, by the processing element, a virtual address of the second memory location based on the load instruction and translating, by the processing element, the virtual address into a real address. | 02-06-2014 |
20140040596 | PACKED LOAD/STORE WITH GATHER/SCATTER - Embodiments relate to packed loading and storing of data. An aspect includes a method for packed loading and storing of data distributed in a system that includes memory and a processing element. The method includes fetching and decoding an instruction for execution by the processing element. The processing element gathers a plurality of individually addressable data elements from non-contiguous locations in the memory which are narrower than a nominal width of register file elements in the processing element based on the instruction. The data elements are packed and loaded into register file elements of a register file entry by the processing element based on the instruction, such that at least two of the data elements gathered from the non-contiguous locations in the memory are packed and loaded into a single register file element of the register file entry. | 02-06-2014 |
20140040597 | PREDICATION IN A VECTOR PROCESSOR - Embodiments relate to vector processor predication in an active memory device. An aspect includes a system for vector processor predication in an active memory device. The system includes memory in the active memory device and a processing element in the active memory device. The processing element is configured to perform a method including decoding an instruction with a plurality of sub-instructions to execute in parallel. One or more mask bits are accessed from a vector mask register in the processing element. The one or more mask bits are applied by the processing element to predicate operation of a unit in the processing element associated with at least one of the sub-instructions. | 02-06-2014 |
20140040598 | VECTOR PROCESSING IN AN ACTIVE MEMORY DEVICE - Embodiments relate to vector processing in an active memory device. An aspect includes a system for vector processing in an active memory device. The system includes memory in the active memory device and a processing element in the active memory device. The processing element is configured to perform a method including decoding an instruction with a plurality of sub-instructions to execute in parallel. An iteration count to repeat execution of the sub-instructions in parallel is determined. Execution of the sub-instructions is repeated in parallel for multiple iterations, by the processing element, based on the iteration count. Multiple locations in the memory are accessed in parallel based on the execution of the sub-instructions. | 02-06-2014 |
20140040599 | PACKED LOAD/STORE WITH GATHER/SCATTER - Embodiments relate to packed loading and storing of data. An aspect includes a system for packed loading and storing of distributed data. The system includes memory and a processing element configured to communicate with the memory. The processing element is configured to perform a method including fetching and decoding an instruction for execution by the processing element. A plurality of individually addressable data elements is gathered from non-contiguous locations in the memory which are narrower than a nominal width of register file elements in the processing element based on the instruction. The processing element packs and loads the data elements into register file elements of a register file entry based on the instruction, such that at least two of the data elements gathered from the non-contiguous locations in the memory are packed and loaded into a single register file element of the register file entry. | 02-06-2014 |
20140040601 | PREDICATION IN A VECTOR PROCESSOR - Embodiments relate to vector processor predication in an active memory device. An aspect includes a method for vector processor predication in an active memory device that includes memory and a processing element. The method includes decoding, in the processing element, an instruction including a plurality of sub-instructions to execute in parallel. One or more mask bits are accessed from a vector mask register in the processing element. The one or more mask bits are applied by the processing element to predicate operation of a unit in the processing element associated with at least one of the sub-instructions. | 02-06-2014 |
20140040603 | VECTOR PROCESSING IN AN ACTIVE MEMORY DEVICE - Embodiments relate to vector processing in an active memory device. An aspect includes a method for vector processing in an active memory device that includes memory and a processing element. The method includes decoding, in the processing element, an instruction including a plurality of sub-instructions to execute in parallel. An iteration count to repeat execution of the sub-instructions in parallel is determined. Based on the iteration count, execution of the sub-instructions in parallel is repeated for multiple iterations by the processing element. Multiple locations in the memory are accessed in parallel based on the execution of the sub-instructions. | 02-06-2014 |
20140047211 | VECTOR REGISTER FILE - An aspect includes accessing a vector register in a vector register file. The vector register file includes a plurality of vector registers and each vector register includes a plurality of elements. A read command is received at a read port of the vector register file. The read command specifies a vector register address. The vector register address is decoded by an address decoder to determine a selected vector register of the vector register file. An element address is determined for one of the plurality of elements associated with the selected vector register based on a read element counter of the selected vector register. A word is selected in a memory array of the selected vector register as read data based on the element address. The read data is output from the selected vector register based on the decoding of the vector register address by the address decoder. | 02-13-2014 |
20140047214 | VECTOR REGISTER FILE - An aspect includes accessing a vector register in a vector register file. The vector register file includes a plurality of vector registers and each vector register includes a plurality of elements. A read command is received at a read port of the vector register file. The read command specifies a vector register address. The vector register address is decoded by an address decoder to determine a selected vector register of the vector register file. An element address is determined for one of the plurality of elements associated with the selected vector register based on a read element counter of the selected vector register. A word is selected in a memory array of the selected vector register as read data based on the element address. The read data is output from the selected vector register based on the decoding of the vector register address by the address decoder. | 02-13-2014 |
20140115294 | MEMORY PAGE MANAGEMENT - According to one embodiment, a method for operating a memory device includes receiving a first request from a requestor, wherein the first request includes accessing data at a first memory location in a memory bank, opening a first page in the memory bank, wherein opening the first page includes loading a row including the first memory location into a buffer, the row being loaded from a row location in the memory bank and transmitting the data from the first memory location to the requestor. The method also includes determining, by a memory controller, whether to close the first page following execution of the first request based on information relating to a likelihood that a subsequent request will access the first page. | 04-24-2014 |
20140129799 | ADDRESS GENERATION IN AN ACTIVE MEMORY DEVICE - Embodiments relate to address generation in an active memory device that includes memory and a processing element. An aspect includes a method for address generation in the active memory device. The method includes reading a base address value and an offset address value from a register file group of the processing element. The processing element determines a virtual address based on the base address value and the offset address value. The processing element translates the virtual address into a physical address and accesses a location in the memory based on the physical address. | 05-08-2014 |
20140130050 | MAIN PROCESSOR SUPPORT OF TASKS PERFORMED IN MEMORY - According to one embodiment of the present invention, a method for operating a computer system including a main processor, a processing element and memory is provided. The method includes receiving, at the processing element, a task from the main processor, performing, by the processing element, an instruction specified by the task, determining, by the processing element, that a function is to be executed on the main processor, the function being part of the task, sending, by the processing element, a request to the main processor for execution, the request comprising execution of the function and receiving, at the processing element, an indication that the main processor has completed execution of the function specified by the request. | 05-08-2014 |
20140130051 | MAIN PROCESSOR SUPPORT OF TASKS PERFORMED IN MEMORY - According to one embodiment of the present invention, a computer system for executing a task includes a main processor, a processing element and memory. The computer system is configured to perform a method including receiving, at the processing element, the task from the main processor, performing, by the processing element, an instruction specified by the task, determining, by the processing element, that a function is to be executed on the main processor, the function being part of the task, sending, by the processing element, a request to the main processor for execution, the request including execution of the function and receiving, at the processing element, an indication that the main processor has completed execution of the function specified by the request. | 05-08-2014 |
20140136811 | ACTIVE MEMORY DEVICE GATHER, SCATTER, AND FILTER - Embodiments relate to loading and storing of data. An aspect includes a method for transferring data in an active memory device that includes memory and a processing element. An instruction is fetched and decoded for execution by the processing element. Based on determining that the instruction is a gather instruction, the processing element determines a plurality of source addresses in the memory from which to gather data elements and a destination address in the memory. One or more gathered data elements are transferred from the source addresses to contiguous locations in the memory starting at the destination address. Based on determining that the instruction is a scatter instruction, a source address in the memory from which to read data elements at contiguous locations and one or more destination addresses in the memory to store the data elements at non-contiguous locations are determined, and the data elements are transferred. | 05-15-2014 |
20140136857 | POWER-CONSTRAINED COMPILER CODE GENERATION AND SCHEDULING OF WORK IN A HETEROGENEOUS PROCESSING SYSTEM - A heterogeneous processing system includes a compiler for performing power-constrained code generation and scheduling of work in the heterogeneous processing system. The compiler produces source code that is executable by a computer. The compiler performs a method. The method includes dividing a power budget for the heterogeneous processing system into a discrete number of power tokens. Each of the power tokens has an equal value of units of power. The method also includes determining a power requirement for executing a code segment on a processing element of the heterogeneous processing system. The determining is based on characteristics of the processing element and the code segment. The method further includes allocating, to the processing element at runtime, at least one of the power tokens to satisfy the power requirement. | 05-15-2014 |
20140136858 | POWER-CONSTRAINED COMPILER CODE GENERATION AND SCHEDULING OF WORK IN A HETEROGENEOUS PROCESSING SYSTEM - An active memory system includes a computer and an active memory device including layers of memory forming a three-dimensional memory device and individual columns of chips forming vaults in communication with a processing element and logic. The processing element is configured to communicate to the chips and other processing elements. The active memory system also includes a compiler configured to implement a method. The method includes dividing a power budget for the active memory device into a discrete number of power tokens, each of the power tokens having an equal value of units of power. The method also includes determining a power requirement for executing a code segment on the processing element of the active memory device based on characteristics of the processing element and the code segment. The method further includes allocating, to the processing element at runtime, one or more power tokens to satisfy the power requirement. | 05-15-2014 |
20140136894 | EXPOSED-PIPELINE PROCESSING ELEMENT WITH ROLLBACK - An aspect includes providing rollback support in an exposed-pipeline processing element. A method for providing rollback support in an exposed-pipeline processing element includes detecting, by rollback support logic, an error associated with execution of an instruction in the exposed-pipeline processing element. The rollback support logic determines whether the exposed-pipeline processing element supports replay of the instruction for a predetermined number of cycles. Based on determining that the exposed-pipeline processing element supports replay of the instruction, a rollback action is performed in the exposed-pipeline processing element to attempt recovery from the error. | 05-15-2014 |
20140136895 | EXPOSED-PIPELINE PROCESSING ELEMENT WITH ROLLBACK - An aspect includes providing rollback support in an exposed-pipeline processing element. A system includes the exposed-pipeline processing element with rollback support logic. The rollback support logic is configured to detect an error associated with execution of an instruction in the exposed-pipeline processing element. The rollback support logic determines whether the exposed-pipeline processing element supports replay of the instruction for a predetermined number of cycles. Based on determining that the exposed-pipeline processing element supports replay of the instruction, a rollback action is performed in the exposed-pipeline processing element to attempt recovery from the error. | 05-15-2014 |
20140148927 | DYNAMIC POWER DISTRIBUTION - According to one embodiment, a method for dynamically sharing power grids of a device includes providing power from a first power supply to a first power grid in a first component of the device. The method also includes providing power from a second power supply to a second power grid in a second component of the device and dynamically changing, by a controller, a state of a first switch that controls a sharing of power between the first power grid and the second power grid during a runtime of the device. | 05-29-2014 |
20140148961 | DYNAMIC POWER DISTRIBUTION - According to one embodiment, a method for dynamically sharing power grids of a device includes providing power from a first power supply to a first power grid in a first component of the device. The method also includes providing power from a second power supply to a second power grid in a second component of the device and dynamically changing, by a controller, a state of a first switch that controls a sharing of power between the first power grid and the second power grid during a runtime of the device. | 05-29-2014 |
20140149673 | LOW LATENCY DATA EXCHANGE - According to one embodiment, a method for exchanging data in a system that includes a main processor in communication with an active memory device is provided. The method includes a processing element in the active memory device receiving an instruction from the main processor and receiving a store request from a thread running on the main processor, the store request specifying a memory address associated with the processing element. The method also includes storing a value provided in the store request in a queue in the processing element and the processing element performing the instruction using the value from the queue. | 05-29-2014 |
20140149680 | LOW LATENCY DATA EXCHANGE - According to one embodiment, a method for exchanging data in a system that includes a main processor in communication with an active memory device is provided. The method includes a processing element in the active memory device receiving an instruction from the main processor and receiving a store request from a thread running on the main processor, the store request specifying a memory address associated with the processing element. The method also includes storing a value provided in the store request in a queue in the processing element and the processing element performing the instruction using the value from the queue. | 05-29-2014 |
20140173224 | SEQUENTIAL LOCATION ACCESSES IN AN ACTIVE MEMORY DEVICE - Embodiments relate to sequential location accesses in an active memory device that includes memory and a processing element. An aspect includes a method for sequential location accesses that includes receiving from the memory a first group of data values associated with a queue entry at the processing element. A tag value associated with the queue entry and specifying a position from which to extract a first subset of the data values is read. The queue entry is populated with the first subset of the data values starting at the position specified by the tag value. The processing element determines whether a second subset of the data values in the first group of data values is associated with a subsequent queue entry, and populates a portion of the subsequent queue entry with the second subset of the data values. | 06-19-2014 |
20140195743 | ON-CHIP TRAFFIC PRIORITIZATION IN MEMORY - According to one embodiment, a method for traffic prioritization in a memory device includes sending a memory access request including a priority value from a processing element in the memory device to a crossbar interconnect in the memory device. The memory access request is routed through the crossbar interconnect to a memory controller in the memory device associated with the memory access request. The memory access request is received at the memory controller. The priority value of the memory access request is compared to priority values of a plurality of memory access requests stored in a queue of the memory controller to determine a highest priority memory access request. A next memory access request is performed by the memory controller based on the highest priority memory access request. | 07-10-2014 |
20140195744 | ON-CHIP TRAFFIC PRIORITIZATION IN MEMORY - According to one embodiment, a memory device is provided. The memory device includes a processing element coupled to a crossbar interconnect. The processing element is configured to send a memory access request, including a priority value, to the crossbar interconnect. The crossbar interconnect is configured to route the memory access request to a memory controller associated with the memory access request. The memory controller is coupled to memory and to the crossbar interconnect. The memory controller includes a queue and is configured to compare the priority value of the memory access request to priority values of a plurality of memory access requests stored in the queue of the memory controller to determine a highest priority memory access request and perform a next memory access request based on the highest priority memory access request. | 07-10-2014 |
20140281084 | LOCAL BYPASS FOR IN MEMORY COMPUTING - Embodiments include a method for bypassing data in an active memory device. The method includes a requestor determining a number of transfers to a grantor that have not been communicated to the grantor, requesting to the interconnect network that the bypass path be used for the transfers based on the number of transfers meeting a threshold and communicating the transfers via the bypass path to the grantor based on the request, the interconnect network granting control of the grantor in response to the request. The method also includes the interconnect network requesting control of the grantor based on an event and communicating delayed transfers via the interconnect network from other requestors, the delayed transfers being delayed due to the grantor being previously controlled by the requestor, the communicating based on the control of the grantor being changed back to the interconnect network. | 09-18-2014 |
20140281100 | LOCAL BYPASS FOR IN MEMORY COMPUTING - Embodiments include a method for bypassing data in an active memory device. The method includes a requestor determining a number of transfers to a grantor that have not been communicated to the grantor, requesting to the interconnect network that the bypass path be used for the transfers based on the number of transfers meeting a threshold and communicating the transfers via the bypass path to the grantor based on the request, the interconnect network granting control of the grantor in response to the request. The method also includes the interconnect network requesting control of the grantor based on an event and communicating delayed transfers via the interconnect network from other requestors, the delayed transfers being delayed due to the grantor being previously controlled by the requestor, the communicating based on the control of the grantor being changed back to the interconnect network. | 09-18-2014 |
20140281386 | CHAINING BETWEEN EXPOSED VECTOR PIPELINES - Embodiments include a method for chaining data in an exposed-pipeline processing element. The method includes separating a multiple instruction word into a first sub-instruction and a second sub-instruction, receiving the first sub-instruction and the second sub-instruction in the exposed-pipeline processing element. The method also includes issuing the first sub-instruction at a first time, issuing the second sub-instruction at a second time different than the first time, the second time being offset to account for a dependency of the second sub-instruction on a first result from the first sub-instruction, the first pipeline performing the first sub-instruction at a first clock cycle and communicating the first result from performing the first sub-instruction to a chaining bus coupled to the first pipeline and a second pipeline, the communicating at a second clock cycle subsequent to the first clock cycle that corresponds to a total number of latch pipeline stages in the first pipeline. | 09-18-2014 |
20140281402 | PROCESSOR WITH HYBRID PIPELINE CAPABLE OF OPERATING IN OUT-OF-ORDER AND IN-ORDER MODES - A method and circuit arrangement provide support for a hybrid pipeline that dynamically switches between out-of-order and in-order modes. The hybrid pipeline may selectively execute instructions from at least one instruction stream that require the high performance capabilities provided by out-of-order processing in the out-of-order mode. The hybrid pipeline may also execute instructions that have strict power requirements in the in-order mode where the in-order mode conserves more power compared to the out-of-order mode. Each stage in the hybrid pipeline may be activated and fully functional when the hybrid pipeline is in the out-of-order mode. However, stages in the hybrid pipeline not used for the in-order mode may be deactivated and bypassed by the instructions when the hybrid pipeline dynamically switches from the out-of-order mode to the in-order mode. The deactivated stages may then be reactivated when the hybrid pipeline dynamically switches from the in-order mode to the out-of-order mode. | 09-18-2014 |
20140281403 | CHAINING BETWEEN EXPOSED VECTOR PIPELINES - Embodiments include a method for chaining data in an exposed-pipeline processing element. The method includes separating a multiple instruction word into a first sub-instruction and a second sub-instruction, receiving the first sub-instruction and the second sub-instruction in the exposed-pipeline processing element. The method also includes issuing the first sub-instruction at a first time, issuing the second sub-instruction at a second time different than the first time, the second time being offset to account for a dependency of the second sub-instruction on a first result from the first sub-instruction, the first pipeline performing the first sub-instruction at a first clock cycle and communicating the first result from performing the first sub-instruction to a chaining bus coupled to the first pipeline and a second pipeline, the communicating at a second clock cycle subsequent to the first clock cycle that corresponds to a total number of latch pipeline stages in the first pipeline. | 09-18-2014 |
20140281605 | POWER MANAGEMENT FOR A COMPUTER SYSTEM - Embodiments include a method for managing power in a computer system including a main processor and an active memory device including powered units, the active memory device in communication with the main processor by a memory link, the powered units including a processing element. The method includes the main processor executing a program on a program thread, encountering a first section of code to be executed by the active memory device, changing, by a first command, a power state of a powered unit on the active memory device based on the main processor encountering the first section of code, the first command including a store command. The method also includes the processing element executing the first section of code at a second time, changing a power state of the main processor from a power use state to a power saving state based on the processing element executing the first section. | 09-18-2014 |
20140281629 | POWER MANAGEMENT FOR A COMPUTER SYSTEM - Embodiments include a method for managing power in a computer system including a main processor and an active memory device including powered units, the active memory device in communication with the main processor by a memory link, the powered units including a processing element. The method includes the main processor executing a program on a program thread, encountering a first section of code to be executed by the active memory device, changing, by a first command, a power state of a powered unit on the active memory device based on the main processor encountering the first section of code, the first command including a store command. The method also includes the processing element executing the first section of code at a second time, changing a power state of the main processor from a power use state to a power saving state based on the processing element executing the first section. | 09-18-2014 |
20150177796 | ROTATING VOLTAGE CONTROL - According to one embodiment, a system is provided that includes at least one power gated component and two or more power switch transistors configured to provide one or more conductive paths between a common power supply rail, the at least one power gated component, and a ground. The two or more power switch transistors each include a source terminal, a drain terminal, and a gate terminal configured to control current flow between the source and drain terminals. The system also includes a rotating voltage control coupled to the gate terminals and configured to apply a sequence of control signals rotating between an on-state and an off-state to each of the gate terminals while the at least one power gated component is turned on. A switch activation ratio level is programmable to set a number of power switch transistors in the on-state relative to a total number of power switch transistors. | 06-25-2015 |
20150177811 | POWER MANAGEMENT FOR IN-MEMORY COMPUTER SYSTEMS - According to one embodiment, a method for power management of a compute node including at least two power-consuming components is provided. A power capping control system compares power consumption level of the compute node to a power cap. Based on determining that the power consumption level is greater than the power cap, actions are performed including: reducing power provided to a first power-consuming component based on determining that it has an activity level below a first threshold and that power can be reduced to the first power-consuming component. Power provided to a second power-consuming component is reduced based on determining that it has an activity level below a second threshold and that power can be reduced to the second power-consuming component. Power reduction is forced in the compute node based on determining that power cannot be reduced in either of the first or second power-consuming component. | 06-25-2015 |
Patent application number | Description | Published |
20090043073 | Alpha-fetoprotein peptides and uses for imaging - The invention provides diagnostic procedures wherein the presence or absence of a cell-proliferating disorder, e.g., a breast cancer, may be determined. The imaging agents of the invention include alpha-fetoprotein hydrophilic analogs which have been determined to target cancers, e.g., breast cancer, and are also anti-cell proliferating in nature. These modulators contain amino acid structures which are arranged as a hydrophilic analog of an alpha-fetoprotein. The modulator may be a peptide; a peptidomimetic; or may be in the form of a pharmaceutically acceptable scaffold, such as a polycyclic hydrocarbon to which is attached the necessary amino acid structures. The imaging agents of the invention further comprise an imaging moiety that allows for the imaging of the area targeted by the imaging agent. | 02-12-2009 |
20100249040 | Alpha-fetoprotein peptides and uses thereof - Therapeutic compounds which are cell proliferation modulators, preferably inhibitors. These modulators contain amino acid structures that are arranged as a hydrophilic analog of an alpha-fetoprotein. The modulator may be a peptide itself, e.g., an octapeptide like that of SEQ ID NO: 5; a peptidomimetic; or may be in the form of a pharmaceutically acceptable scaffold, such as a polycyclic hydrocarbon to which is attached the necessary amino acid structures for biological and/or chemical activity. The modulators of the invention are distinguished in one aspect over previous compounds in that they are orally active, and therefore do not have to be injected into the patient. The compositions and methods are useful for reducing estrogen-dependent and estrogen-independent growth of cells, and treating or preventing cancer, such as breast cancer, brain cancer, head-and-neck cancer, thyroid cancer, lung cancer, colon cancer, ovarian cancer, prostate cancer, cervical cancer, and skin cancer. The treatment or prevention methods can include the use of tamoxifen therapy in combination with the peptide therapy. | 09-30-2010 |
20110269692 | ALPHA-FETOPROTEIN PEPTIDES AND USES THEREOF - Therapeutic compounds which are cell proliferation modulators, preferably inhibitors. These modulators contain amino acid structures that are arranged as a hydrophilic analog of an alpha-fetoprotein. The modulator may be a peptide itself, e.g., an octapeptide like that of SEQ ID NO: 5; a peptidomimetic; or may be in the form of a pharmaceutically acceptable scaffold, such as a polycyclic hydrocarbon to which is attached the necessary amino acid structures for biological and/or chemical activity. The modulators of the invention are distinguished in one aspect over previous compounds in that they are orally active, and therefore do not have to be injected into the patient. The compositions and methods are useful for reducing estrogen-dependent and estrogen-independent growth of cells, and treating or preventing cancer, such as breast cancer, brain cancer, head-and-neck cancer, thyroid cancer, lung cancer, colon cancer, ovarian cancer, prostate cancer, cervical cancer, and skin cancer. The treatment or prevention methods can include the use of tamoxifen therapy in combination with the peptide therapy. | 11-03-2011 |
20130059794 | ALPHA-FETOPROTEIN "RING AND TAIL" PEPTIDES - The invention relates to compounds that are analogs of a cyclic peptide, cyclo[EKTOVNOGN], AFPep, that has anti-estrotrophic activity. The analogs of the invention include peptides and peptidomimetics that inhibit estrogen receptor-dependent cell proliferation. The compounds of the invention are useful for treating cell proliferative disorders or physiological conditions characterized by undesirable or unwanted estrogen induced cell proliferation, including breast cancer. | 03-07-2013 |
Patent application number | Description | Published |
20090305265 | INTERLEUKIN-33 (IL-33) FOR THE DIAGNOSIS AND PROGNOSIS OF CARDIOVASCULAR DISEASE - The present invention includes methods for the use of interleukin-33 (IL-33) in the diagnosis of cardiovascular conditions including acute coronary syndrome (ACS), myocardial infarction, and/or heart failure, angina, cardiac hypertrophy, arteriosclerosis, myocarditis, pancarditis, endocarditis, stroke and/or pulmonary embolism and the determination of the severity of such conditions (prognosis). | 12-10-2009 |
20100009356 | DIAGNOSIS OF CARDIOVASCULAR DISEASE - This invention relates to methods for the detection of cardiovascular disease, e.g., acute coronary syndrome, heart failure and/or pulmonary embolism, in high body mass index (BMI) individuals, e.g., with a BMI of 25-29, or 30 or above, and those with impaired renal function. | 01-14-2010 |
20100055683 | DIAGNOSIS OF PULMONARY AND/OR CARDIOVASCULAR DISEASE - Described are methods and kits for determining the likelihood of the presence of cardiovascular disease (CVD) or pulmonary disease (PD) in a subject using ST2/Interleukin 1 Receptor Like 1 (IL1RL1) and/or Interleukin 33 (IL-33), and a biomarker for CVD, e.g., a natriuretic peptide, e.g., brain natriuretic peptide (BNP), prohormone BNP (proBNP), N-Terminal proBNP (NT-proBNP), atrial natriuretic peptide (ANP), proANP, or NT-proANP. | 03-04-2010 |
20100273886 | FORMULATIONS AND METHODS FOR LYOPHILIZATION AND LYOPHILATES PROVIDED THEREBY - The present invention provides compositions, methods for lyophilizing compounds and making pharmaceutical compositions, and kits providing solutions and lyophilized formulations of compounds. The compositions, methods, and kits are particularly useful in pharmaceutical applications involving therapeutic agents that have low solubility at low pH and medium pH values. Certain embodiments provide methods for lyophilizing compounds in liquid solutions, which include the steps of: a) preparing aqueous solutions of a compound of interest in the absence of buffer; b) adjusting the pH to high values of pH in order to increase the solubility of the compound of interest; and c) freeze-drying the solution to provide a lyophilized solid composition. Aqueous solutions including buffer are also disclosed. Lyophilized formulations, including micronized and non-micronized powders, are provided. | 10-28-2010 |
20110034560 | LIQUID FORMULATIONS OF COMPOUNDS ACTIVE AT SULFONYLUREA RECEPTORS - The invention provides liquid formulations of compounds that act at sulfonylurea receptors that are suitable for intra-venous and intra-arterial infusion. Compounds active at a sulfonylurea receptor include glibenclamide, tolbutamide, repaglinide, nateglinide, meglitinide, midaglizole, LY397364, LY389382, glyclazide, and glimepiride. Liquid formulations may be concentrated solutions suitable for storage; may be diluted (e.g., dilution of 1:1 or 1:1.2) suitable for bolus injections, and may be further diluted (e.g., dilution of 1:10 or 1:20 or more) for intravenous and intra-arterial infusion over an extended period of time. For example, a liquid formulation may include at least about 0.05 mg/ml glibenclamide in a water-based solution including 40% polyethylene glycol 300, 10% Ethanol, 50% water, at about pH 9. The solution may include a buffer, and is suitable for storage in refrigerator or at room temperature. This solution may be diluted 1:1, or more (e.g., 1:20) without precipitation of the glibenclamide. | 02-10-2011 |
20110053170 | Interleukin-33 (IL-33) for the Diagnosis and Prognosis of Cardiovascular Disease - The present invention includes methods for the use of interleukin-33 (IL-33) in the diagnosis of cardiovascular conditions including acute coronary syndrome (ACS), myocardial infarction, and/or heart failure, angina, cardiac hypertrophy, arteriosclerosis, myocarditis, pericarditis, endocarditis, stroke and/or pulmonary embolism and the determination of the severity of such conditions (prognosis). | 03-03-2011 |
20110262941 | PREDICTING MORTALITY AND DETECTING SEVERE DISEASE - Measurement of circulating ST2 and/or IL-33 concentrations is useful for the prognostic evaluation of subjects, in particular for the prediction of adverse clinical outcomes, e.g., mortality, and the detection of severe disease. | 10-27-2011 |
20120040381 | PREDICTING MORTALITY AND DETECTING SEVERE DISEASE - Measurement of circulating ST2 and/or IL-33 concentrations is useful for the prognostic evaluation of subjects, in particular for the prediction of adverse clinical outcomes, e.g., mortality, and the detection of severe disease. | 02-16-2012 |
20130245069 | FORMULATIONS AND METHODS FOR LYOPHILIZATION AND LYOPHILATES PROVIDED THEREBY - The present invention provides compositions, methods for lyophilizing compounds and making pharmaceutical compositions, and kits providing solutions and lyophilized formulations of compounds. The compositions, methods, and kits are particularly useful in pharmaceutical applications involving therapeutic agents that have low solubility at low pH and medium pH values. Certain embodiments provide methods for lyophilizing compounds in liquid solutions, which include the steps of: a) preparing aqueous solutions of a compound of interest in the absence of buffer; b) adjusting the pH to high values of pH in order to increase the solubility of the compound of interest; and c) freeze-drying the solution to provide a lyophilized solid composition. Aqueous solutions including buffer are also disclosed. Lyophilized formulations, including micronized and non-micronized powders, are provided. | 09-19-2013 |
20140045200 | PREDICTING MORTALITY AND DETECTING SEVERE DISEASE - Measurement of circulating ST2 and/or IL-33 concentrations is useful for the prognostic evaluation of subjects, in particular for the prediction of adverse clinical outcomes, e.g., mortality, and the detection of severe disease. | 02-13-2014 |
20140058743 | Multimarker Risk Stratification - Measurement of circulating ST2 and natriuretic peptide (e.g., NT-proBNP) concentrations is useful for the prognostic evaluation of subjects, in particular for the prediction of adverse clinical outcomes, e.g., mortality, transplantation, and heart failure. | 02-27-2014 |
20140302536 | DIAGNOSIS OF PULMONARY AND/OR CARDIOVASCULAR DISEASE - Described are methods and kits for determining the likelihood of the presence of cardiovascular disease (CVD) or pulmonary disease (PD) in a subject using ST2/Interleukin 1 Receptor Like 1 (IL1RL1) and/or Interleukin 33 (IL-33), and a biomarker for CVD, e.g., a natriuretic peptide, e.g., brain natriuretic peptide (BNP), prohormone BNP (proBNP), N-Terminal proBNP (NT-proBNP), atrial natriuretic peptide (ANP), proANP, or NT-proANP. | 10-09-2014 |
20150141516 | FORMULATIONS AND METHODS FOR LYOPHILIZATION AND LYOPHILATES PROVIDED THEREBY - The present invention provides compositions, methods for lyophilizing compounds and making pharmaceutical compositions, and kits providing solutions and lyophilized formulations of compounds. The compositions, methods, and kits are particularly useful in pharmaceutical applications involving therapeutic agents that have low solubility at low pH and medium pH values. Certain embodiments provide methods for lyophilizing compounds in liquid solutions, which include the steps of: a) preparing aqueous solutions of a compound of interest in the absence of buffer; b) adjusting the pH to high values of pH in order to increase the solubility of the compound of interest; and c) freeze-drying the solution to provide a lyophilized solid composition. Aqueous solutions including buffer are also disclosed. Lyophilized formulations, including micronized and non-micronized powders, are provided. | 05-21-2015 |
Patent application number | Description | Published |
20100056444 | Treatment of Alzheimer's Disease Using Compounds that Reduce the Activity of Non Selective Ca Activated ATP- Sensitive Cation Channels Regulated by SUR1 Receptors - NSC antagonists are disclosed as useful in the treatment of dementia, in delaying the onset of dementia, and in the prevention of dementia. Dementia so treated may be, for example, Alzheimer's Disease (AD). NSC antagonists for treating dementia such as AD may be administered alone, a) in combination with other drugs used for treating dementia, b) in combination with drugs that stabilize or increase blood plasma glucose levels, or with both a) and b). Pharmaceutical compositions, dosage forms, and methods for using the same are disclosed, which include NSC antagonists, NSC antagonists combined with dementia drugs, NSC antagonists combined with glucose-level stabilizing or enhancing drugs, or combinations of these. Dosage forms may be designed to provide stable plasma levels for extended periods of time. Exemplary pharmaceutical compositions include compositions including glibenclamide and memantine; glibenclamide and donepezil; tolbutamide and memantine; tolbutamide and donepezil; and these compositions further including glucagon and/or glucose. | 03-04-2010 |
20130203853 | METHODS OF INTRAVENOUS ADMINISTRATION OF GLYBURIDE AND OTHER DRUGS - Methods of administering glyburide, or other drug, are disclosed. The novel methods disclosed herein include intravenous methods of administering glyburide, or other drug, over periods of more than an hour, preferably over periods of about 72 hours. The novel methods include administering a bolus of glyburide, or other drug, followed by a first continuous infusion administration of glyburide, or other drug; and optionally a second or further bolus administration of glyburide, or other drug, and/or a second or further continuous infusion administration of glyburide, or other drug. These methods are effective to rapidly achieve a desired level of glyburide, or other drug, and to provide a substantially steady level of glyburide, or other drug, over a desired period of time. The methods disclosed herein may be useful for treating a subject in need of treatment for, e.g., acute stroke (ischemic and hemorrhagic), traumatic brain injury (TBI), spinal cord injury (SCI), myocardial infarction (MI), shock (including hemorrhagic shock), organ ischemia, and ventricular arrhythmias. These methods provide for the rapid achievement and maintenance of therapeutic glyburide, or other drug, plasma levels over an extended period of time, and further avoid excessive levels of drug and so avoid possible drug side-effects. | 08-08-2013 |
20140080811 | Treatment of Alzheimer's Disease Using Compounds that Reduce the Activity of Non-Selective CA++ Activated ATP-Sensitive Cation Channels Regulatd by SUR1 Channels - NSC antagonists are disclosed as useful in the treatment of dementia, in delaying the onset of dementia, and in the prevention of dementia. Dementia so treated may be, for example, Alzheimer's Disease (AD). NSC antagonists for treating dementia such as AD may be administered alone, a) in combination with other drugs used for treating dementia, b) in combination with drugs that stabilize or increase blood plasma glucose levels, or with both a) and b). Pharmaceutical compositions, dosage forms, and methods for using the same are disclosed, which include NSC antagonists, NSC antagonists combined with dementia drugs, NSC antagonists combined with glucose-level stabilizing or enhancing drugs, or combinations of these. Dosage forms may be designed to provide stable plasma levels for extended periods of time. Exemplary pharmaceutical compositions include compositions including glibenclamide and memantine; glibenclamide and donepezil; tolbutamide and memantine; tolbutamide and donepezil; and these compositions further including glucagon and/or glucose. | 03-20-2014 |
20150157560 | METHODS OF INTRAVENOUS ADMINISTRATION OF GLYBURIDE - The present disclosure is drawn to a method of administering glyburide intravenously to a subject over a period of time as a first bolus administration of glyburide; a second bolus administration of glyburide, after the first bolus; and a first continuous infusion administration of glyburide, wherein the first continuous infusion is administered at a first rate of administration for a first period of time, after the second bolus administration of glyburide. | 06-11-2015 |