Patent application number | Description | Published |
20090327562 | Implementing Bus Interface Calibration for Enhanced Bus Interface Initialization Time - A method and apparatus are provided for implementing bus interface calibration to improve bus interface initialization time in a system. Bus interface calibration is performed and average calibration values are saved. At bus interface initialization time, checking for saved calibration values is performed. The saved calibration values are used and tested. When the saved calibration values pass the test, then the saved calibration values are used for system operation without performing any training steps. | 12-31-2009 |
20120278528 | IIMPLEMENTING STORAGE ADAPTER WITH ENHANCED FLASH BACKED DRAM MANAGEMENT - A method and controller for implementing enhanced flash backed dynamic random access memory (DRAM) management, and a design structure on which the subject controller circuit resides are provided. An input/output adapter (IOA) includes at least one super capacitor, a data store (DS) dynamic random access memory (DRAM), a flash memory, a non-volatile random access memory (NVRAM), and a flash backed DRAM controller. Responsive to an adapter reset, Data Store DRAM testing including restoring a DRAM image from Flash to DRAM and testing of DRAM is performed. Mirroring of RAID configuration data and RAID parity update footprints between the NVRAM and DRAM is performed. Save of DRAM contents to the flash memory is controllably enabled when super capacitors have been sufficiently recharged and the flash memory erased. | 11-01-2012 |
20120303855 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH HARDWARE ACCELERATORS OFFLOADING FIRMWARE FOR BUFFER ALLOCATION AND AUTOMATICALLY DMA - A method and controller for implementing storage adapter performance optimization with automatic chained hardware operations eliminating firmware operations, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines and a control store configured to store a plurality of control blocks. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A plurality of the control blocks is selectively arranged in a respective predefined chain to define sequences of hardware operations. An automatic hardware structure is configured to build the respective predefined chain controlling the hardware operations for a predefined hardware function. The predefined hardware function includes buffer allocation and automatic DMA data from a host system to the controller for write operations, eliminating firmware operations. | 11-29-2012 |
20120303859 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH PARITY UPDATE FOOTPRINT MIRRORING - A method and controller for implementing storage adapter performance optimization with parity update footprint mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. Each of a first controller and a second controller includes a plurality of hardware engines, a control store configured to store parity update footprint (PUFP) data; a data store; and a nonvolatile random access memory (NVRAM). One controller operates in a first initiator mode for transferring PUFP data to the other controller operating in a target mode. Respective initiator hardware engines transfers PUFP data from the initiator control store, selectively updating PUFP data, and writing PUFP data to the initiator data store and to the initiator NVRAM, and simultaneously transmitting PUFP data to the other controller. Respective target hardware engines write PUFP data to the target data store and the target NVRAM, eliminating firmware operations. | 11-29-2012 |
20120303883 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH CACHE DATA/DIRECTORY MIRRORING - A method and controller for implementing storage adapter performance optimization with cache data and cache directory mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. One of the first controller or the second controller operates in a first initiator mode includes firmware to set up an initiator write operation building a data frame for transferring data and a respective cache line (CL) for each page index to the other controller operating in a second target mode. Respective initiator hardware engines transfers data, reading CLs from an initiator control store, and writing updated CLs to an initiator data store, and simultaneously sends data and updated CLs to the other controller. Respective target hardware engines write data and updated CLs to the target data store, eliminating firmware operations of the controller operating in the second target mode. | 11-29-2012 |
20120303886 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH HARDWARE CHAINS TO SELECT PERFORMANCE PATH - A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to implement a particular performance path minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a data store configured to store a plurality of control blocks selectively arranged in one of a plurality of predefined chains. Each predefined chain defines a sequence of operations. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A resource handle structure is configured to select a predefined chain based upon a particular characteristic of the system. Each predefined chain is configured to implement a particular performance path to maximize performance. | 11-29-2012 |
20120303909 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH ENHANCED HARDWARE AND SOFTWARE INTERFACE - A method and controller for implementing storage adapter performance optimization with chained hardware operations and an enhanced hardware (HW) and firmware (FW) interface minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a processor. A data store is configured to store a plurality of control blocks. A global work queue includes a plurality of the control blocks selectively arranged in a predefined chain to define sequences of hardware operations. The global work queue includes a queue input coupled to the processor and the hardware engines and an output coupled to the hardware engines. The control blocks are arranged in respective engine work queues designed to control hardware operations of the respective hardware engines and respective control blocks are arranged in an event queue to provide completion results to the processor. | 11-29-2012 |
20120303922 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH ENHANCED RESOURCE POOL ALLOCATION - A method and controller for implementing storage adapter performance optimization with enhanced resource pool allocation, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; a processor, and a plurality of resource pools. A plurality of work queues is associated with the resource pools. The processor initializes a list of types, and the associated amount of pages for each allocate type. The hardware engines maintain a count of allocate types, specifying a type on each allocation and deallocation, and performing allocation from the resource pools for deadlock avoidance. | 11-29-2012 |
20120304001 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH CHAINED HARDWARE OPERATIONS AND ERROR RECOVERY FIRMWARE PATH - A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to minimize hardware and firmware interactions and a bridge code configured to select a firmware sequence for error recovery to complete the operations responsive to an identified error in the predefined chain, and a design structure on which the subject controller circuit resides are provided. A selected predefined chain is configured to implement a particular performance path to maximize performance. Responsive to an identified predefined error during hardware operations in the predefined hardware chain, a bridge code is configured to select a non-performance path firmware sequence for error recovery completion of remaining operations. | 11-29-2012 |
20120304198 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH CHAINED HARDWARE OPERATIONS MINIMIZING HARDWARE/FIRMWARE INTERACTIONS - A method and controller for implementing storage adapter performance optimization with chained hardware operations minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and one or more processors. An event queue is coupled to at least one processor notifying the processor of a plurality of predefined events. A control block is designed to control an operation in one of the plurality of hardware engines including the hardware engine writing an event queue entry. A plurality of the control blocks are selectively arranged in a predefined chain to minimize the hardware engine writing event queue entries to the processor. | 11-29-2012 |
20130046930 | OPTIMIZING LOCATIONS OF DATA ACCESSED BY CLIENT APPLICATIONS INTERACTING WITH A STORAGE SYSTEM - A method for optimizing locations of physical data accessed by one or more client applications interacting with a storage system, with the storage system comprising at least two redundancy groups having physical memory spaces and data bands. Each of the data bands corresponds to physical data stored on several of the physical memory spaces. A virtualized logical address space includes client data addresses utilizable by the one or more client applications. A storage controller is configured to map the client data addresses onto the data bands, such that a mapping is obtained, wherein the one or more client applications can access physical data corresponding to the data bands. | 02-21-2013 |
20130046931 | OPTIMIZING LOCATIONS OF DATA ACCESSED BY CLIENT APPLICATIONS INTERACTING WITH A STORAGE SYSTEM - A method for optimizing locations of physical data accessed by one or more client applications interacting with a storage system, with the storage system comprising at least two redundancy groups having physical memory spaces and data bands. Each of the data bands corresponds to physical data stored on several of the physical memory spaces. A virtualized logical address space includes client data addresses utilizable by the one or more client applications. A storage controller is configured to map the client data addresses onto the data bands, such that a mapping is obtained, wherein the one or more client applications can access physical data corresponding to the data bands. | 02-21-2013 |
20140101479 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE CONTROL - A method and controller for implementing storage adapter performance control, and a design structure on which the subject controller circuit resides are provided. The controller includes a performance state machine controlling the use of a performance path and a normal or error recovery path in a storage adapter firmware stack. The performance state machine determines which storage resources are allowed to use the performance path and properly transitions the running of each storage resource to and from the performance path and normal path mode of operation. | 04-10-2014 |
Patent application number | Description | Published |
20080198530 | FILTERING CAPACITOR FEEDTHROUGH ASSEMBLY - A filtering capacitor feedthrough assembly for an implantable active medical device is disclosed. The filtering capacitor feedthrough assembly includes a capacitor having an aperture, the capacitor is electrically grounded to an electrically conductive feedthrough ferrule or housing of the implantable active medical device. A terminal pin extends into the aperture and an electrically conductive continuous coil is disposed within the aperture and between the terminal pin and the capacitor. The electrically conductive continuous coil mechanically secures and electrically couples the terminal pin to the capacitor. | 08-21-2008 |
20080273287 | FILTERING CAPACITOR FEEDTHROUGH ASSEMBLY - A filtering capacitor feedthrough assembly for an implantable active medical device is disclosed. The filtering capacitor feedthrough assembly includes a capacitor having an aperture defined by an inner capacitor surface. The capacitor is electrically grounded to an electrically conductive feedthrough ferrule or housing of the implantable active medical device. A terminal pin extends into the aperture. An electrically conductive split ring sleeve is disposed within the aperture and between the terminal pin and the capacitor. The split ring sleeve includes a first end, a second end, a sleeve length therebetween. A longitudinal slit through the sleeve extends from the first end to the second end. The electrically conductive split ring sleeve mechanically securing and electrically coupling the terminal pin to the capacitor. | 11-06-2008 |
20090128987 | FILTERING CAPACITOR FEEDTHROUGH ASSEMBLY - A filtering capacitor feedthrough assembly for an implantable active medical device is disclosed. The filtering capacitor feedthrough assembly includes a capacitor having an aperture, the capacitor is electrically grounded to an electrically conductive feedthrough ferrule or housing of the implantable active medical device. A terminal pin extends into the aperture and an electrically conductive continuous coil is disposed within the aperture and between the terminal pin and the capacitor. The electrically conductive continuous coil mechanically secures and electrically couples the terminal pin to the capacitor. | 05-21-2009 |
20100192355 | METHODS OF FORMING A FILTERING CAPACITOR FEEDTHROUGH ASSEMBLY - A method of forming a filtering capacitor feedthrough assembly for an implantable active medical device includes inserting a terminal pin into an aperture of a capacitor, the capacitor configured to be electrically grounded to an electrically conductive feedthrough ferrule or housing of the implantable active medical device, then disposing an electrically conductive continuous coil within the aperture between the terminal pin and the capacitor and then fixing the continuous coil to the terminal pin or the capacitor. The continuous coil includes an inner diameter defined by a plurality of coils, the terminal pin extending through the inner diameter of the continuous coil so that the plurality of coils circumferentially surround the terminal pin. The electrically conductive continuous coil mechanically secures and electrically couples the terminal pin to the capacitor. | 08-05-2010 |
20110170230 | Filtering Capacitor Feedthrough Assembly - A filtering capacitor feedthrough assembly for an implantable active medical device is disclosed. The filtering capacitor feedthrough assembly includes a capacitor having an aperture defined by an inner capacitor surface. The capacitor is electrically grounded to an electrically conductive feedthrough ferrule or housing of the implantable active medical device. A terminal pin extends into the aperture. An electrically conductive split ring sleeve is disposed within the aperture and between the terminal pin and the capacitor. The split ring sleeve includes a first end, a second end, a sleeve length therebetween. A longitudinal slit through the sleeve extends from the first end to the second end. The electrically conductive split ring sleeve mechanically securing and electrically coupling the terminal pin to the capacitor. | 07-14-2011 |
Patent application number | Description | Published |
20110045271 | CATIONIC POLYMERIC FLUORINATED ETHER SILANE COMPOSITIONS AND METHODS OF USE - A polymer is provided comprising a first pendant group selected from at least one of a perfluorinated ether group or a perfluoroalkanesulfonamido group, a second pendant group comprising an ammonium group, wherein the second pendant group is free of silicon, and a third pendant group comprising an ammonium group and a reactive siliconcontaining group. A composition comprising the polymer is provided. The polymer and composition are useful for protecting a substrate, for example, to render the substrate oil repellent, water repellent, or both, or to provide stain repellency to the substrate. | 02-24-2011 |
20110226733 | PATTERNING PROCESS - A patterning process comprises (a) providing at least one substrate having at least one major surface; (b) providing at least one patterning composition comprising at least one functionalizing molecule that is a perfluoropolyether organosulfur compound; (c) applying the patterning composition to the major surface of the substrate in a manner so as to form at least one functionalized region and at least one unfunctionalized region of the major surface; and (d) etching at least a portion of the unfunctionalized region. | 09-22-2011 |
20110319546 | FLUORINATED COMPOSITION, METHOD OF COATING THE COMPOSITION, AND ARTICLE THEREBY - A fluorinated composition includes: a polyfluoropolyether silane represented by the formula: | 12-29-2011 |
20120259088 | COPOLYMERS WITH PERFLUOROPOLYETHER SEGMENT AND MULTIPLE AMINOOXALYLAMINO GROUPS - Copolymers containing at least one perfluoropolyether segment and multiple aminooxalylamino groups are described. Methods of making the copolymers are also described. The copolymers can be prepared by reacting an oxalylamino-containing compound and an amine compound having at least two primary amino groups, at least two secondary amino groups, or at least one primary amino group plus at least one secondary amino group. | 10-11-2012 |
20120264890 | COPOLYMERS WITH PERFLUOROPOLYETHER SEGMENT AND POLYDIORGANOSILOXANE SEGMENT - Copolymers containing at least one perfluoropolyether segment and at least one polydiorganosiloxane segments are described. The copolymers further contain multiple aminooxalylamino groups that link the various segments together. Methods of making the copolymers are also described. | 10-18-2012 |
20120289736 | PERFLUOROPOLYETHER-CONTAINING COMPOUNDS WITH OXALYLAMINO GROUPS - Compounds containing at least one perfluoropolyether segment and at least two oxalylamino groups as well as methods of making these compounds are described. The compounds can be polymeric materials or can be used in the preparation of various copolymeric materials by reaction with compounds having at least two primary or secondary amino groups. | 11-15-2012 |
20130102747 | CATIONIC POLYMERIC FLUORINATED ETHER SILANE COMPOSITIONS AND METHODS OF USE - A polymer is provided comprising a first pendant group selected from at least one of a perfluorinated ether group or a perfluoroalkanesulfonamido group, a second pendant group comprising an ammonium group, wherein the second pendant group is free of silicon, and a third pendant group comprising an ammonium group and a reactive silicon-containing group. A composition comprising the polymer is provided. The polymer and composition are useful for protecting a substrate, for example, to render the substrate oil repellent, water repellent, or both, or to provide stain repellency to the substrate. | 04-25-2013 |
20130209814 | REFLECTIVE ARTICLES AND METHODS OF MAKING THE SAME - Reflective articles and related methods of manufacture are provided. These articles include a metallic layer extending across a non-tacky base layer. The base layer includes either a block copolymer or random copolymer with at least two polymeric components, one of which has a glass transition temperature of at least 50 degrees Celsius and the other of which has a glass transition temperature no greater than 20 degrees Celsius. These articles provide excellent optical clarity, non-corrosiveness, ultraviolet light stability, and resistance to outdoor weathering conditions compared to conventional reflective films. | 08-15-2013 |
20130216820 | HYDROPHOBIC FLUORINATED COATINGS - Articles having hydrophobic fluorinated coatings are provided. More specifically, the articles include a substrate, a primer layer of acid-sintered silica nanoparticles, and a hydrophobic fluorinated layer. The hydrophobic fluorinated coatings can be used on a large variety of substrate and tend to be quite durable even when subjected to repeated rubbing and/or cleaning. | 08-22-2013 |
20130220177 | SURFACE TREATMENT PROCESS, COMPOSITION FOR USE THEREIN, AND TREATED ARTICLE - A surface treatment process comprises (a) providing at least one substrate; (b) providing a curable surface treatment composition comprising (1) at least one fluorinated organosilane compound comprising (i) a monovalent segment selected from polyfluoroalkyl, polyfluoroether, polyfluoropolyether, and combinations thereof and (ii) a monovalent endgroup comprising at least one silyl moiety comprising at least one group selected from hydrolyzable groups, hydroxyl, and combinations thereof, and (2) at least one organosilane compound comprising (i) a multivalent non-fluorinated segment and (ii) at least two monovalent endgroups, each monovalent endgroup independently comprising at least one silyl moiety comprising at least one group selected from hydroxyl, hydrolyzable groups, and combinations thereof, and/or at least one organosilazane compound; (c) applying the curable surface treatment composition to the substrate; and (d) curing the applied, curable surface treatment composition. | 08-29-2013 |
20130220682 | Method of Reducing Electromigration of Silver and Article Made Thereby - A method includes: providing a silver-containing conductive member disposed on a portion of a surface of chemically-strengthened glass, wherein the conductive member comprises silver; disposing a layer comprising a curable polysilazane onto at least a portion of the conductive member and at least a portion of the surface of the chemically-strengthened glass adjacent to the conductive member; and curing the curable polysilazane. Electronic devices prepared according to the method are also disclosed. | 08-29-2013 |
20130229378 | OPTICAL DEVICE SURFACE TREATMENT PROCESS AND SMUDGE-RESISTANT ARTICLE PRODUCED THEREBY - A surface treatment process comprises (a) providing at least one optical device; (b) providing a curable surface treatment composition comprising (1) at least one fluorinated organosilane compound comprising (i) a monovalent segment selected from polyfluoroalkyl, polyfluoroether, polyfluoropolyether, and combinations thereof and (ii) a monovalent endgroup comprising at least one silyl moiety comprising at least one group selected from hydrolyzable groups, hydroxyl, and combinations thereof, and (2) at least one fluorinated organosilane compound comprising (i) a multivalent segment selected from polyfluoroalkane, polyfluoroether, polyfluoropolyether, and combinations thereof and (ii) at least two monovalent endgroups, each independently comprising at least one silyl moiety comprising at least one group selected from hydrolyzable groups, hydroxyl, and combinations thereof; (c) applying the curable surface treatment composition to the optical device; and (d) curing the applied, curable surface treatment composition. | 09-05-2013 |
20130264276 | Filter Media Treated with Cationic Fluorinated Ether Silane Compositions - Filter media is treated with a composition comprising cationic fluorinated ether silanes to provide durable water- and/or oil-repellency properties. | 10-10-2013 |
20140022644 | ANTIREFLECTIVE FILM COMPRISING LARGE PARTICLE SIZE FUMED SILICA - Antireflective films are described comprising a light transmissive substrate and a low refractive index layer disposed on the light transmissive substrate. The low refractive index layer comprises the reaction product of polymerizable resin composition comprising at least 20 wt-% fumed silica. In one embodiment, the polymerizable resin is ethylenically unsaturated. In a favored embodiment, the low refractive index layer increases in porosity from the light transmissive substrate interface to an opposing porous surface. | 01-23-2014 |
20150051362 | AMIDE-LINKED PERFLUOROPOLYETHER THIOL COMPOUNDS AND PROCESSES FOR THEIR PREPARATION AND USE - A perfluoropolyether thiol compound comprises a perfluoropolyether segment, at least one mercapto group (—SH), and at least one intervening divalent carbonylimino moiety (—C(═O)—NR—, wherein R is hydrogen or alkyl). The compound can be produced, for example, by a ring-opening reaction of thiolactones with perfluoropolyether-substituted, primary or secondary amines. The compound can be used, for example, as a polymerization chain transfer agent, as an intermediate for the preparation of functional group-containing fluorochemical derivatives such as disulfides, and as a fluorinated surface treatment. | 02-19-2015 |
20150057428 | COPOLYMERS WITH PERFLUOROPOLYETHER SEGMENT AND MULTIPLE AMINOOXALYLAMINO GROUPS - Copolymers containing at least one perfluoropolyether segment and multiple aminooxalylamino groups are described. Methods of making the copolymers are also described. The copolymers can be prepared by reacting an oxalylamino-containing compound and an amine compound having at least two primary amino groups, at least two secondary amino groups, or at least one primary amino group plus at least one secondary amino group. | 02-26-2015 |