Patent application number | Description | Published |
20090327981 | Semiconductor device or printed wiring board design method and design support system that implements settings by using a semiconductor device model that expresses parasitic elements that occur when packaged - Correction circuit models are acquired for correcting electrical characteristic parameters that change upon mounting on a board. The correction circuit models are added to a separate model that represents a separate semiconductor device in isolation to create a semiconductor device model that represents the semiconductor device in a board-mounted state. An equivalent circuit model that represents an adjustment-object system is connected to the semiconductor device model that was created, and based on the semiconductor device model to which the equivalent circuit model is connected, adjustment-object values relating to the adjustment-object system are calculated. These adjustment-object values are compared with limit values that were determined in advance, and based on the results of comparison, a design guide is determined for adjusting the adjustment-object system. | 12-31-2009 |
20100193929 | SEMICONDUCTOR DEVICE - A semiconductor device includes a package board, first connectors, and a first multi-layered structure. The package board has first and second regions. The first connectors are in the first region. The first multi-layered structure includes a first semiconductor chip, a wiring board, and second to fifth connectors. The first semiconductor chip has first and second surfaces. The first surface covers the second region. The wiring board has third and fourth surfaces. The third surface is fixed to the second surface. The second to fourth connectors are in the center regions of the second to fourth surfaces, respectively. The fifth connectors are aligned along opposing two sides of the fourth surface. The second connectors electrically connect to the third connectors. The third connectors electrically connect to the fourth and fifth connectors. The first connectors electrically connect to the fourth and fifth connectors. | 08-05-2010 |
20100193933 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip. | 08-05-2010 |
20110084395 | Semiconductor package substrate and semiconductor device having the same - A semiconductor device includes a semiconductor chip and a package substrate on which the semiconductor chip is mounted. The package substrate has internal terminals connected to the semiconductor chip, front surface wirings connected to the internal terminals, rear surface wirings connected to external electrodes, and contacts connecting the front surface wiring and rear surface wiring. Out of the plurality of contact, some contacts included in the wirings for signal transmission are disposed near the internal terminals. Thus, a signal led out from the semiconductor chip is immediately taken away from the chip mounting surface of the package substrate. This reduces the floating capacitance between the wirings on the package substrate and chip, thereby improving the signal quality. | 04-14-2011 |
20120119387 | SEMICONDUCTOR PACKAGE WITH BONDING WIRES OF REDUCED LOOP INDUCTANCE - A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers. | 05-17-2012 |
20120200159 | SEMICONDUCTOR DEVICE - A semiconductor device includes: first and second power supply wirings VDDQ and VSSQ, respectively; an output circuit | 08-09-2012 |
20130140674 | SEMICONDUCTOR DEVICE - A semiconductor device according to this invention includes a first power line that supplies power to a first circuit, a second power line that supplies power to a second circuit, and a capacitive element that is provided between the first power line and the second power line. | 06-06-2013 |
20140035166 | SEMICONDUCTOR DEVICE STACK WITH BONDING LAYER AND WIRE RETAINING MEMBER - In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip. | 02-06-2014 |
20140103542 | SEMICONDUCTOR PACKAGE WITH BONDING WIRES OF REDUCED LOOP INDUCTANCE - A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers. | 04-17-2014 |
20150022255 | SEMICONDUCTOR DEVICE - A semiconductor device according to this invention includes a first power line that supplies power to a first circuit, a second power line that supplies power to a second circuit, and a capacitive element that is provided between the first power line and the second power line. | 01-22-2015 |
Patent application number | Description | Published |
20100181379 | RFID TAG - An RFID tag characterized in including: a dielectric substrate having a hole formed in one main surface thereof; a ground conductive pattern disposed on another main surface of this dielectric substrate; a conductive pattern disposed on the one main surface of the above-mentioned dielectric substrate in such a way as to be placed in an inner portion of the dielectric substrate at a predetermined distance from each of edges of the above-mentioned dielectric substrate, a slot being formed in this conductive pattern; and an IC chip electrically connected to the above-mentioned conductive pattern via this slot, and inserted into the above-mentioned hole of the above-mentioned dielectric substrate. | 07-22-2010 |
20120188145 | RADOME OF CANAPE STRUCTURE - A radome not having a sandwich structure but having a canape structure is formed with an object to obtain a radome of a canape structure having a satisfactory radio property, and moreover, an excellent mechanical strength by providing a matching layer to a skin layer on an interior side of a radome. The skin layer is formed of layered glass fiber cloths and resin impregnated therein. The layered glass fiber cloths can be replaced with glass fiber mats. For the matching layer, a foamed material, such as a urethane material having a low permittivity, or a core material having a resin impregnating property can be used. A radome of a canape structure can be obtained with the skin layer and the matching layer. | 07-26-2012 |
20140270276 | ELECTROMECHANICAL TRANSDUCER AND ELECTROCOUSTIC TRANSDUCER - An electromechanical transducer of the invention comprises a structural unit, an armature, and first and second elastic members. The structural unit includes at least one pair of magnets, a yoke conducting a magnetic flux generated by the magnets, and a coil supplied with an electric signal. The armature has an inner portion disposed to pass through an internal space of the structural unit and first and second outer portions protruding on both sides from the inner portion, and the armature constitutes a magnetic circuit with the structural unit via two regions through which components of the magnetic flux flow in directions opposite to each other in the inner portion. The first and second elastic members connect between the first and second outer portions of the armature and the structural unit, respectively. | 09-18-2014 |