Islam, TX
Asad Islam, Richardson, TX US
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20100045800 | Method and Device for Controlling Auto Focusing of a Video Camera by Tracking a Region-of-Interest - The invention concerns an electronic device equipped with a video imaging process capability, which device includes a camera unit arranged to produce image frames from an imaging view which includes a region-of-interest ROI, an adjustable optics arranged in connection with the camera unit in order to focus the ROI on the camera unit, an identifier unit in order to identify a ROI from the image frame, a tracking unit in order to track the ROI from the image frames during the video imaging process and an auto-focus unit arranged to analyze the ROI on the basis of the tracking results provided by the tracking unit in order to adjust the optics. The device is arranged to determine the spatial position of the ROI in the produced image frame without any estimation measures. | 02-25-2010 |
20110206287 | Compressed Domain System And Method For Compression Gains In Encoded Data - A system and method for compressed domain compression are provided for improving compression gains in an encoded image, such as a Joint Photographic Experts Group (JPEG)-encoded images, without fully decoding and re-encoding the compressed images. | 08-25-2011 |
20120013793 | VIDEO IMPORTANCE RATING BASED ON COMPRESSED DOMAIN VIDEO FEATURES - Systems and methods are provided for identifying important video frames and segments in multimedia content such as a segmented compressed domain video. Video frames in a segment are analyzed to determine intensity, contrast, and motion values for the frames and their segments. The values among frames and segments are compared to identify one or more video segments likely to be important to a viewer. The systems and methods may additionally be augmented with audio data other characteristics associated with the video frames and segments analyzed. | 01-19-2012 |
20120106626 | EFFICIENT CONTENT COMPRESSION AND DECOMPRESSION SYSTEM AND METHOD - A content compression/compression system and method are disclosed in which a pre-processing step is performed before any compression and a post-processing step is performed once a compressed piece of content is decompressed. | 05-03-2012 |
20130223540 | COMPRESSED DOMAIN SYSTEM AND METHOD FOR COMPRESSION GAINS IN ENCODED DATA - A system and method for compressed domain compression are provided for improving compression gains in an encoded image, such as a Joint Photographic Experts Group (JPEG)-encoded images, or encoded video, such as Motion Joint Photographic Experts Group (Motion JPEG)-encoded video, without fully decoding and re-encoding the compressed images or video. | 08-29-2013 |
20130272622 | EFFICIENT CONTENT COMPRESSION AND DECOMPRESSION SYSTEM AND METHOD - A content compression/compression system and method are disclosed in which a pre-processing step is performed before any compression and a post-processing step is performed once a compressed piece of content is decompressed. | 10-17-2013 |
Imranul Islam, Austin, TX US
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20140266336 | CLOCK SIGNAL TIMING-BASED NOISE SUPPRESSION - A method includes generating one of a first clock signal and a second clock signal from the other clock signal. The first clock signal is configured to be used to synchronize an operation of an analog system, and the second clock signal is configured to be used to synchronize an operation of a digital system. The method includes using a phase detector of the analog system to measure a timing of the first clock signal relative to the second clock signal; and the method includes controlling a delay element of the digital system to regulate the timing based on the measurement by the phase detector to suppress noise in the analog system. | 09-18-2014 |
Imranul Islam, San Marcos, TX US
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20160119111 | System and Apparatus for Clock Retiming with Catch-Up Mode and Associated Methods - An apparatus includes analog or mixed-signal circuitry that operates in response to a first signal, and digital circuitry that operates in response to a second signal. The apparatus further includes a signal retiming circuit. The signal retiming circuit retimes an output signal of a digital signal source to reduce interference between the digital circuitry and the analog or mixed-signal circuitry by retiming edges of the output signal of the digital signal source to fall on cycle boundaries of the first signal. | 04-28-2016 |
Mohammad A. Islam, Houston, TX US
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20100068391 | METHODS OF PREPARING THIN FILMS BY ELECTROLESS PLATING - The present invention provides methods of controlling properties of a thin film applied to a substrate whereby the properties of the thin film may be controlled by the surface morphology of the substrate. Methods of increasing a deposition rate of an electroless plating process applied to a substrate, controlling the grain size distribution and/or grain size of a thin film applied to a substrate and maintaining a uniform overpotential of an electroless plating process on a substrate are also provided. | 03-18-2010 |
Mohammed R. Islam, Richardson, TX US
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20090135895 | Self-calibrated adaptive equalization system and methods of performing the same - A self-calibrating, adaptive equalization system for generating an ideal digital signal is disclosed. The adaptive equalization system includes an equalizer and a high-gain buffer. The equalizer includes a first equalizer loop that feeds-back a control voltage to the equalizer and the high-gain buffer that includes a second equalizer loop that feeds-back a high-pass-to-low-pass filter ratio signal. Each of the first and second equalizer loops has a high-pass and a low-pass filter, rectifying circuits for each of the filters, and an integrating circuit that compares signal energy output from the rectifiers. The adaptive equalization system generates an ideal digital signal. | 05-28-2009 |
Nauman Islam, Pearland, TX US
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20090232663 | Compressor-Expander Set Critical Speed Avoidance - A control method and apparatus for critical rotational speed avoidance in a compressor-expander set in a gas refrigeration system. By varying an opening of an antisurge or recycle valve, a shaft power used by the compressor in the compressor-expander set may be varied, thereby varying the rotational speed of the compressor-expander set to move it away from its critical speed zone. Additionally, a feedforward signal may be provided by a compressor-expander set control system to cause an antisurge valve for a recycle compressor to open upon a trip or shutdown of one compressor-expander set. | 09-17-2009 |
20130094974 | Compressor-Expander Set Critical Speed Avoidance - A control method and apparatus for critical rotational speed avoidance in a compressor-expander set in a gas refrigeration system. By varying an opening of an antisurge or recycle valve, a shaft power used by the compressor in the compressor-expander set may be varied, thereby varying the rotational speed of the compressor-expander set to move it away from its critical speed zone. Additionally, a feedforward signal may be provided by a compressor-expander set control system to cause an antisurge valve for a recycle compressor to open upon a trip or shutdown of one compressor-expander set. | 04-18-2013 |
Rabiul Islam, Austin, TX US
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20090243710 | FIREWALL/ISOLATION CELLS FOR ULTRA LOW POWER PRODUCTS - In an integrated circuit (IC) may have several functional blocks adapted to be inactivated independently from each other. At least one firewall cell may be embedded independently of other firewall cells in the vicinity of one functional block. The firewall cell may be electrically isolated from the functional block and may be powered by a constantly supplied voltage source in the IC. Firewall cells may be embedded in free locations on the IC in the functional block domain according to a design that may be free of constraints such as firewall cells array of firewall cells mini-island. | 10-01-2009 |
20140359311 | Controlling Power Delivery To A Processor Via A Bypass - In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed. | 12-04-2014 |
Rakibul Islam, Lewisville, TX US
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20110278887 | SEAT SUPPORT ASSEMBLY - Described are seat support assemblies comprising at least one of a pitch reducer assembly, a fitting assembly, an energy absorption assembly, and an integrated leg assembly. The pitch reducer assembly may include a pitch reducer housing, at least one pitch riser, and at least one pitch stop. The integrated leg assembly may include a forward leg and an aft leg, where the forward leg is coupled to the pitch reducer assembly. The fitting assembly may include a pair of forward housing mating components and a pair of aft housing mating components, where the pairs of mating components are coupled to the forward and aft legs, respectively. The energy absorption assembly may include a tubular member, a die slidingly coupled to the tubular member, and a die holder coupled to the die, wherein the die holder has a hemispherical outer surface that is configured to pivotally mate with a passenger seat housing and rotate about an arc of rotation relative to the tubular member | 11-17-2011 |
Saiful Islam, Austin, TX US
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20080239860 | Apparatus and Method for Providing Multiple Reads/Writes Using a 2Read/2Write Register File Array - An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. The apparatus and method provide a mechanism to write the consecutive entries by only having a 4 to 16 decode of one address. In addition, the apparatus and method provide a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address. The two read word lines are used to access the two read ports of the entries in the sub-arrays. | 10-02-2008 |
20080251888 | Method and Apparatus for Self-Contained Automatic Decoupling Capacitor Switch-Out in Integrated Circuits - An integrated circuit (IC) includes power supply interconnects that couple to a power source. The integrated circuit includes electronic devices that perform desired functions and further includes decoupling capacitor circuits that provide noise reduction throughout the integrated circuit. In one embodiment, each decoupling capacitor circuit includes a decoupling capacitor and a switching circuit. The switching circuit connects the decoupling capacitor to the power supply interconnects during a connect mode when the switching circuit detects no substantial decoupling capacitor leakage. However, the switching circuit effectively disconnects the decoupling capacitor from the power supply interconnects during a disconnect mode when the switching circuit detects substantial decoupling capacitor leakage. The decoupling capacitor circuit self-initializes in the connect mode without external control signals and is thus self-contained. Because of the self-contained nature of the decoupling capacitor circuit, an integrated circuit may contain an array of decoupling capacitor circuits without expenditure of substantial chip real estate for respective decoupling capacitor control lines. | 10-16-2008 |
20080279015 | REGISTER FILE - A register file is often used within integrated circuitry to temporarily hold data. Sometimes this data needs to be retained within the register file for a period of time, such as when there is a stall operation. Conventional register files have utilized a hold multiplexor to perform such a stall operation. The multiplexor however inserts a delay that is undesirable in high performance integrated circuitry. The multiplexor is replaced with a tri-state inverter coupled to the global bit line of the register file, which minimizes this additional delay from the register file data access time. | 11-13-2008 |
20090010077 | SHIFT REGISTER LATCH WITH EMBEDDED DYNAMIC RANDOM ACCESS MEMORY SCAN ONLY CELL - A hybrid shift register latch which uses static memory cells for system operations and a dynamic memory cell for testing operations only. An L1 storage element and an L2 storage element are provided in an array cell. The L1 storage element comprises a static random access memory cell. The L1 storage element is used during system and testing operation of the array cell. The L2 storage element comprises a dynamic random access memory cell. The L2 storage element is used only during testing operation of the array cell. | 01-08-2009 |
20090108920 | ENERGY-SAVING CIRCUIT AND METHOD USING CHARGE EQUALIZATION ACROSS COMPLEMENTARY NODES - An energy-saving circuit and method using charge equalization across complementary nodes reduces power consumption in memory circuits and other circuits such as wide multiplexers having complementary high-capacitance nodes. A change detection circuit detects a state change to be applied to the bitlines, and generates a pulse if a state change is to be applied. A pass gate connected between the nodes is activated in response to the pulse to equalize the charge on the bitlines. The driver circuit enable inputs are also delayed, so that the bitlines are not driven until after the charge has been equalized and the pass gate disabled. In one embodiment, the driver circuits are only enabled momentarily by a pulsed output of the change detector and keeper circuits are employed to retain the bitlines in their asserted states. | 04-30-2009 |
20090251974 | MEMORY CIRCUITS WITH REDUCED LEAKAGE POWER AND DESIGN STRUCTURES FOR SAME - A memory circuit includes a global read bit line, a global read bit line latch, and a plurality of sub-arrays, each of which includes first and second local read bit lines, first and second local write bit lines, and first and second pluralities of memory cells interconnected, respectively, with the first and second local read bit lines and the first and second local write bit lines. The local read bit lines are decoupled from the local write bit lines. A local multiplexing block is interconnected with the first and second local read bit lines and is configured to ground the first and second local read bit lines upon assertion of a SLEEP signal, and to selectively interconnect the local read bit lines to the global read bit line. A global multiplexing block is interconnected with the global read bit line and is configured to maintain the global read bit line in a substantially discharged state upon assertion of the SLEEP signal and to interconnect the global read bit line to the global read bit line latch. Also included are design structures for circuits of the kind described. | 10-08-2009 |
Shafidul Islam, Plano, TX US
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20090215244 | Package Having Exposed Integrated Circuit Device - A package ( | 08-27-2009 |
20100221872 | REVERSIBLE LEADLESS PACKAGE AND METHODS OF MAKING AND USING SAME - A method for manufacturing a semiconductor device package including an electrically conductive lead frame having a plurality of posts disposed at a perimeter of the package. Each of the posts has a first contact surface at the first package face and a second contact surface at the second package face. The lead frame also includes a plurality of post extensions disposed at the second package face. Each of the post extensions includes a bond site formed on a surface of the post extension opposite the second package face. At least one I/O pad on the semiconductor device is electrically connected to the post extension at the bond site using wirebonding, tape automated bonding, or flip-chip methods. The package can be assembled using a lead frame having pre-formed leads, with or without taping, or using partially etched lead frames. A stack of the semiconductor device packages may be formed. | 09-02-2010 |
20110001224 | LEAD FRAME ROUTED CHIP PADS FOR SEMICONDUCTOR PACKAGES - A redistributed lead frame for use in a molded plastic semiconductor package is formed from an electrically conductive substrate by a sequential metal removal process. The process includes patterning a first side of the substrate to form an array of lands separated by channels; disposing a first molding compound within those channels; patterning a second side of the substrate to form an array of chip attach sites and routing circuits electrically interconnecting the array of lands and the array of chip attach sites; directly electrically interconnecting input/output pads on a semiconductor device to the chip attach sites; and encapsulating the semiconductor device, the array of chip attach sites and the routing circuits with a second molding compound. This process is particularly suited for the manufacture of chip scale packages and very thin packages. | 01-06-2011 |
Waseul Islam, Garland, TX US
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20150201002 | ELECTRONIC CONTENT DELIVERY WITH DISTRIBUTED RECIPIENT DELIVERY PREFERENCE - According to some embodiments, a delivery system comprises an interface and one or more processors. The interface is operable to receive a current preference from a recipient. The current preference indicates how the recipient prefers messages to be delivered. The processors determine whether the current preference differs from a previous preference that the delivery system associates with the recipient. The interface communicates the current preference to a plurality of senders if the current preference differs from the previous preference. The senders are configured to store the current preference in local memory and to apply the current preference from local memory in response to a future determination to send a message to the recipient. | 07-16-2015 |
Zahid Islam, Dallas, TX US
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20130114451 | INTRA-CELL AND INTER-CELL INTERFERENCE MITIGATION METHODS FOR ORTHOGONAL FREQUENCY-DIVISION MULTIPLE ACCESS CELLULAR NETWORKS - Various embodiments of a method of mitigating interference in an OFDMA cellular network and a user terminal incorporating various of the embodiments. In one embodiment, the method includes: (1) selecting at least one dominant interfering signal, (2) generating estimates of a desired signal and the at least one dominant interfering signal, (3) jointly deciding based on the estimates such that an energy of a residual error is reduced and (4) mitigating interference based on the estimates. | 05-09-2013 |
20140050315 | HIGH-SPEED IN-MEMORY QR DECOMPOSITION USING FAST PLANE ROTATIONS - A system and method for processing an input matrix and a MIMO receiver employing the system or the method. In one embodiment, the system includes: (1) a transformer configured to receive a frame of complex data representing only some elements of an input matrix and perform a fast plane rotation on the complex data to yield rotated data and (2) a matrix updater coupled to the transformer and configured to update a memory configured to contain an output matrix with the rotated data. In one embodiment, the system and method are to estimate and mitigate alien cross-talk experienced in a vectored DSL communication system. | 02-20-2014 |