Patent application number | Description | Published |
20140372411 | ON-THE-FLY ENCODING METHOD FOR EFFICIENT GROUPING AND AGGREGATION - Embodiments include a method and computer program product for encoding data while it is being processed as part of a query is provided. The method includes receiving a query request and determining a set of values associated with data to be encoded for completing the query request. The method also includes encoding those values such that any subsequent processing operations can be performed on the encoded values to complete the requested query. After performing the subsequent processing operations to complete the requested query, each value is decoded back to its original value. | 12-18-2014 |
20140372470 | ON-THE-FLY ENCODING METHOD FOR EFFICIENT GROUPING AND AGGREGATION - Embodiments include a system for encoding data while it is being processed. The system includes a processor, an encoder and a decoder. The processor is configured to process a query request by determining a set of values. The encoder is configured for encoding the set of values, such that a subsequent processing operation can be performed on the encoded values. The processor performs the subsequent processing operations. The decoder is configured for decoding each value back to its value prior to being encoded upon completion of the processor completing the requested query. | 12-18-2014 |
20140379985 | MULTI-LEVEL AGGREGATION TECHNIQUES FOR MEMORY HIERARCHIES - Embodiments include method, system, and computer program product for providing aggregation hierarchy that is related memory hierarchies. In one embodiment, the method includes determining capacity of a first level memory of a memory hierarchy for processing data relating to completion of an aggregation process and generating a per thread local look-up table in said first level memory upon determining said capacity. Upon the first level memory reaching capacity, a plurality of per thread partitions to store remaining data to complete the aggregation process in a second level memory of the memory hierarchy is generated such that each of said per-thread partitions includes an identical amount of data portion on each thread. The method also includes storing the per thread partitions in said second level memory and providing a single global look up table for each of the identical data portions. | 12-25-2014 |
20150193274 | DATA SHUFFLING IN A NON-UNIFORM MEMORY ACCESS DEVICE - A method of orchestrated shuffling of data in a non-uniform memory access device that includes a plurality of processing nodes includes running an application on a plurality of threads executing on the plurality of processing nodes and identifying data to be shuffled from source threads running on source processing nodes among the processing nodes to target threads executing on target processing nodes among the processing nodes. The method further includes generating a plan for orchestrating the shuffling of the data among the all of the memory devices associated with the threads and shuffling the data among all of the memory devices based on the plan. | 07-09-2015 |
20150193344 | DATA SHUFFLING IN A NON-UNIFORM MEMORY ACCESS DEVICE - Embodiments relate to the orchestration of data shuffling among memory devices of a non-uniform memory access device. An aspect includes a method of orchestrated shuffling of data in a non-uniform memory access device includes running an application on a plurality of threads executing on a plurality of processing nodes and identifying data to be shuffled among the plurality of processing nodes. The method includes registering the data to be shuffled and generating a plan for orchestrating the shuffling of the data. The method further includes disabling cache coherency of cache memory associated with the processing nodes and shuffling the data among all of the memory devices upon disabling the cache coherency, the shuffling performed based on the plan for orchestrating the shuffling. The method further includes restoring the cache coherency of the cache memory based on completing the shuffling of the data among all of the memory devices. | 07-09-2015 |
20160034527 | ACCURATE PARTITION SIZING FOR MEMORY EFFICIENT REDUCTION OPERATIONS - Embodiments of the invention relate to processing data records, and for a multi-phase partitioned data reduction. The first phase relates to processing data records and partitioning the records into a first partition of records having a common characteristic and a second partition of records that are not members of the first partition. The data records in each partition are subject to intra-partition data reduction responsive to a resource constraint. The data records in each partition are also subject to an inter-partition data reduction, also referred to as an aggregation to reduce a footprint for storing the records. Partitions and/or individual records are logically aggregated and a data reduction operation for the logical aggregation of records takes place in response to available resources. | 02-04-2016 |
20160070484 | DATA SHUFFLING IN A NON-UNIFORM MEMORY ACCESS DEVICE - A method of orchestrated shuffling of data in a non-uniform memory access device that includes a plurality of processing nodes that are connected by interconnects. The method includes running an application on a plurality of threads executing on the plurality of processing nodes. Data to be shuffled is identified from source threads running on source processing nodes among the processing nodes to target threads executing on target processing nodes among the processing nodes. The method further includes generating a plan for orchestrating the shuffling of the data among the all of the memory devices associated with the threads and for simultaneously transmitting data over different interconnects to a plurality of different target processing nodes from a plurality of different source processing nodes. The data is shuffled among all of the memory devices based on the plan. | 03-10-2016 |
20160077878 | Logical Data Shuffling - Embodiments relate to data shuffling by logically rotating processing nodes. The nodes are logically arranged in a two or three dimensional matrix. Every time two of the nodes in adjacent rows of the matrix are positionally aligned, these adjacent nodes exchange data. The positional alignment is a logical alignment of the nodes. The nodes are logically arranged and rotated, and data is exchanged in response to the logical rotation. | 03-17-2016 |