Patent application number | Description | Published |
20140172866 | SYSTEM FOR STORAGE, QUERYING, AND ANALYSIS OF TIME SERIES DATA - A system for storing time series data includes an ingester that prepares metadata indices associated with blocks of incoming time series data and stores the blocks of data in a time series database and the indices in a separate index database. The time series database distributes storage of the data blocks among multiple data nodes. A query layer receives queries and uses the index database to determine which data blocks are needed to process the query, and then requests only those data blocks from the time series database. Processing of the query is performed within the time series database only on those data nodes that contain relevant data, and partial results are passed to an output layer for formation into a final query result. | 06-19-2014 |
20140172867 | METHOD FOR STORAGE, QUERYING, AND ANALYSIS OF TIME SERIES DATA - A method for performing queries on a distributed time series data storage system is presented. The time series data storage system has a time series database that stores data blocks containing time stamped data across a plurality of computing devices. The system also includes an index database that stores an index associated with the time stamped data in each data block. The method includes the steps of sending a query, requesting indices, returning the indices, preparing a sub-query, forwarding the sub-query to an evaluator, evaluating the sub-query, performing a logical operation on each sub-query's result, receiving the sub-results at an output handler, and combining the sub-results. | 06-19-2014 |
20140172868 | SYSTEM AND METHOD FOR STORAGE, QUERYING, AND ANALYSIS SERVICE FOR TIME SERIES DATA - A service for storing time series data provides a data pipe for receiving time series data, a query pipe for making requests to the service, and a result pipe for receiving output from the service. Data sent to the query pipe is processed by an ingester that prepares metadata indices associated with blocks of incoming time series data and stores the blocks of data in a time series database and the indices in a separate index database. A query layer receives queries from the query pipe and uses the index database to determine which data blocks are needed to process the query, and then requests only those data blocks from the time series database. Processing of the query is performed within the time series database only on those data nodes that contain relevant data, and partial results are passed to an output layer for formation into a final query result which is sent out by the results pipe. | 06-19-2014 |
20150356154 | SYSTEM FOR STORAGE, QUERYING, AND ANALYSIS OF TIME SERIES DATA - A system for storing time series data includes an ingester that prepares metadata indices associated with blocks of incoming time series data and stores the blocks of data in a time series database and the indices in a separate index database. The time series database distributes storage of the data blocks among multiple data nodes. A query layer receives queries and uses the index database to determine which data blocks are needed to process the query, and then requests only those data blocks from the time series database. Processing of the query is performed within the time series database only on those data nodes that contain relevant data, and partial results are passed to an output layer for formation into a final query result. | 12-10-2015 |
Patent application number | Description | Published |
20080219248 | SYSTEM AND METHOD FOR RAPIDLY CONFIGURING WIRELESS TRANSCEIVERS - A system and method for configuring a wireless transceiver are disclosed. As one example, a system for configuring a wireless transceiver is disclosed, which includes a first data storage unit coupled to a configuration bus disposed in the wireless transceiver, a second data storage unit coupled to the configuration bus, a change detection unit coupled to the second data storage unit, the change detection configured to detect a change to a value stored in the second data storage unit, and output a signal responsive to the change, and a third data storage unit coupled to the first data storage unit, the second data storage unit, and the change detection unit. The third data storage unit is configured to store a plurality of predefined configuration data sets, and convey a predefined configuration data set to the first data storage unit responsive to the signal. | 09-11-2008 |
20120106686 | DIGITAL I/Q IMBALANCE COMPENSATION IN A QUADRATURE RECEIVER - An apparatus and method reduce distortion in a processed signal. The apparatus includes a first receive path, a second receive path, a summation unit, and a compensation unit. The first receive path is configured to process a received analog signal into a first digital signal. The second receive path is configured to process the received analog signal with a phase shift into a second digital signal. The summation unit is configured to sum the first and second digital signals to form a processed digital signal. The compensation unit is configured to identify a conjugate of the processed digital signal, apply a weighting factor to the conjugate of the processed digital signal to form a weighted signal, and subtract the weighted signal from the processed digital signal to reduce the distortion. | 05-03-2012 |
Patent application number | Description | Published |
20080206960 | REWORKABLE CHIP STACK - A method for removing a thinned silicon structure from a substrate, the method includes selecting the silicon structure with soldered connections for removal; applying a silicon structure removal device to the silicon structure and the substrate, wherein the silicon structure removal device comprises a pre-determined temperature setpoint for actuation within a range from about eighty percent of a melting point of the soldered connections to about the melting point; heating the silicon structure removal device and the soldered connections of the silicon structure to within the range to actuate the silicon structure removal device; and removing the thinned silicon structure. Also disclosed is a structure including a plurality of layers, at least one layer including a thinned silicon structure and solder coupling the layer to another layer of the plurality; wherein the solder for each layer has a predetermined melting point. | 08-28-2008 |
20090085202 | Methods and Apparatus for Assembling Integrated Circuit Device Utilizing a Thin Si Interposer - Methods of assembling an integrated circuit are provided. An interposer supported by an integrated handler is solder bumped onto one or more bond pads on a substrate. The integrated handler is removed from the interposer. A side of the interposer opposite that of the substrate is solder bumped to one or more bond pads on a chip. | 04-02-2009 |
20090184407 | METHOD TO RECOVER UNDERFILLED MODULES BY SELECTIVE REMOVAL OF DISCRETE COMPONENTS - Methods and reworked intermediate and resultant electronic modules made thereby, whereby a component in need of rework is located and removed from the module to reveal encapsulated solder connections residing within an underfill matrix. Heights of both the solder connections and underfill matrix are reduced, followed by etching the solder out of the solder connections to form openings within the underfill matrix. The underfill material is then removed to expose metallurgy of the substrate. A blank having a release layer with an array of solder connections is aligned with the exposed metallurgy, and this solder array is transferred from the blank onto the metallurgy. The transferred solder connections are then flattened using heat and pressure, followed by attaching solder connections of a new component to the flattened solder connections and underfilling these reworked solder connections residing between the new chip and substrate. | 07-23-2009 |
20120256313 | SOLDER BALL CONTACT SUSCEPTIBLE TO LOWER STRESS - A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball. | 10-11-2012 |
20120292779 | SEMICONDUCTOR STRUCTURE HAVING OFFSET PASSIVATION TO REDUCE ELECTROMIGRATION - A semiconductor structure which includes a plurality of stacked semiconductor chips in a three dimensional configuration. There is a first semiconductor chip in contact with a second semiconductor chip. The first semiconductor chip includes a through silicon via (TSV) extending through the first semiconductor chip; an electrically conducting pad at a surface of the first semiconductor chip, the TSV terminating in contact at a first side of the electrically conducting pad; a passivation layer covering the electrically conducting pad, the passivation layer having a plurality of openings; and a plurality of electrically conducting structures formed in the plurality of openings and in contact with a second side of the electrically conducting pad, the contact of the plurality of electrically conducting structures with the electrically conducting pad being offset with respect to the contact of the TSV with the electrically conducting pad. | 11-22-2012 |
20130015579 | SOLDER BALL CONTACT SUSCEPTIBLE TO LOWER STRESS - A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball. | 01-17-2013 |
20140256090 | SELECTIVE AREA HEATING FOR 3D CHIP STACK - A method of forming a 3D package. The method may include joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat and first uniform pressure; joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure; heating the 3D package, the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where the first and second selective non-uniform heats being less that the reflow temperature of the first and second pluralities of solder bumps, respectively. | 09-11-2014 |
20150228614 | 3D BOND AND ASSEMBLY PROCESS FOR SEVERELY BOWED INTERPOSER DIE - An interposer structure containing a first set of solder balls is placed in proximity to a vacuum distribution plate which has a planar contact surface and a plurality of openings located therein. A vacuum is then applied through the openings within the vacuum distribution plate such that the first set of solder balls are suspended within the plurality of openings and the interposer structure conforms to the planar contact surface of the vacuum distribution plate. A semiconductor chip containing a second set of solder balls is tacked to a surface of the interposer structure. A substrate is then brought into contact with a surface of the interposer structure containing the first set of solder balls, and then a solder reflow and underfill processes can be performed. Warping of the interposer structure is substantially eliminated using the vacuum distribution plate mentioned above. | 08-13-2015 |
20150235986 | SELECTIVE AREA HEATING FOR 3D CHIP STACK - A method of forming a 3D package. The method may include joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat and first uniform pressure; joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure; heating the 3D package, the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where the first and second selective non-uniform heats being less that the reflow temperature of the first and second pluralities of solder bumps, respectively. | 08-20-2015 |